1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 brw_reg
= dst
.fixed_hw_reg
;
57 brw_reg
= brw_null_reg();
61 assert(!"not reached");
62 brw_reg
= brw_null_reg();
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 assert(!"not reached");
97 brw_reg
= brw_null_reg();
103 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
104 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
105 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
107 brw_reg
= retype(brw_reg
, src
[i
].type
);
108 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
110 brw_reg
= brw_abs(brw_reg
);
112 brw_reg
= negate(brw_reg
);
114 /* This should have been moved to pull constants. */
115 assert(!src
[i
].reladdr
);
119 brw_reg
= src
[i
].fixed_hw_reg
;
123 /* Probably unused. */
124 brw_reg
= brw_null_reg();
128 assert(!"not reached");
129 brw_reg
= brw_null_reg();
136 vec4_generator::vec4_generator(struct brw_context
*brw
,
137 struct gl_shader_program
*shader_prog
,
138 struct gl_program
*prog
,
139 struct brw_vec4_prog_data
*prog_data
,
142 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
143 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
145 shader
= shader_prog
? shader_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
] : NULL
;
147 p
= rzalloc(mem_ctx
, struct brw_compile
);
148 brw_init_compile(brw
, p
, mem_ctx
);
151 vec4_generator::~vec4_generator()
156 vec4_generator::mark_surface_used(unsigned surf_index
)
158 assert(surf_index
< BRW_MAX_VS_SURFACES
);
160 prog_data
->binding_table_size
= MAX2(prog_data
->binding_table_size
,
165 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
171 brw_math_function(inst
->opcode
),
174 BRW_MATH_DATA_VECTOR
,
175 BRW_MATH_PRECISION_FULL
);
179 check_gen6_math_src_arg(struct brw_reg src
)
181 /* Source swizzles are ignored. */
184 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
188 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
192 /* Can't do writemask because math can't be align16. */
193 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
194 check_gen6_math_src_arg(src
);
196 brw_set_access_mode(p
, BRW_ALIGN_1
);
199 brw_math_function(inst
->opcode
),
202 BRW_MATH_DATA_SCALAR
,
203 BRW_MATH_PRECISION_FULL
);
204 brw_set_access_mode(p
, BRW_ALIGN_16
);
208 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
215 brw_math_function(inst
->opcode
),
220 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
225 /* Can't do writemask because math can't be align16. */
226 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0
);
229 check_gen6_math_src_arg(src1
);
231 brw_set_access_mode(p
, BRW_ALIGN_1
);
234 brw_math_function(inst
->opcode
),
236 brw_set_access_mode(p
, BRW_ALIGN_16
);
240 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
248 * "Operand0[7]. For the INT DIV functions, this operand is the
251 * "Operand1[7]. For the INT DIV functions, this operand is the
254 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
255 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
256 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
258 brw_push_insn_state(p
);
259 brw_set_saturate(p
, false);
260 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
262 brw_pop_insn_state(p
);
266 brw_math_function(inst
->opcode
),
269 BRW_MATH_DATA_VECTOR
,
270 BRW_MATH_PRECISION_FULL
);
274 vec4_generator::generate_tex(vec4_instruction
*inst
,
281 switch (inst
->opcode
) {
282 case SHADER_OPCODE_TEX
:
283 case SHADER_OPCODE_TXL
:
284 if (inst
->shadow_compare
) {
285 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
287 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
290 case SHADER_OPCODE_TXD
:
291 if (inst
->shadow_compare
) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw
->is_haswell
);
294 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
296 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
299 case SHADER_OPCODE_TXF
:
300 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
302 case SHADER_OPCODE_TXF_MS
:
304 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
306 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
308 case SHADER_OPCODE_TXS
:
309 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
312 assert(!"should not get here: invalid VS texture opcode");
316 switch (inst
->opcode
) {
317 case SHADER_OPCODE_TEX
:
318 case SHADER_OPCODE_TXL
:
319 if (inst
->shadow_compare
) {
320 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
321 assert(inst
->mlen
== 3);
323 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
324 assert(inst
->mlen
== 2);
327 case SHADER_OPCODE_TXD
:
328 /* There is no sample_d_c message; comparisons are done manually. */
329 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
330 assert(inst
->mlen
== 4);
332 case SHADER_OPCODE_TXF
:
333 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
334 assert(inst
->mlen
== 2);
336 case SHADER_OPCODE_TXS
:
337 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
338 assert(inst
->mlen
== 2);
341 assert(!"should not get here: invalid VS texture opcode");
346 assert(msg_type
!= -1);
348 /* Load the message header if present. If there's a texture offset, we need
349 * to set it up explicitly and load the offset bitfield. Otherwise, we can
350 * use an implied move from g0 to the first message register.
352 if (inst
->texture_offset
) {
353 /* Explicitly set up the message header by copying g0 to the MRF. */
354 brw_push_insn_state(p
);
355 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
356 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
359 /* Then set the offset bits in DWord 2. */
360 brw_set_access_mode(p
, BRW_ALIGN_1
);
362 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
363 BRW_REGISTER_TYPE_UD
),
364 brw_imm_uw(inst
->texture_offset
));
365 brw_pop_insn_state(p
);
366 } else if (inst
->header_present
) {
367 /* Set up an implied move from g0 to the MRF. */
368 src
= brw_vec8_grf(0, 0);
371 uint32_t return_format
;
374 case BRW_REGISTER_TYPE_D
:
375 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
377 case BRW_REGISTER_TYPE_UD
:
378 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
381 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
389 SURF_INDEX_VS_TEXTURE(inst
->sampler
),
392 1, /* response length */
394 inst
->header_present
,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
398 mark_surface_used(SURF_INDEX_VS_TEXTURE(inst
->sampler
));
402 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
405 brw_null_reg(), /* dest */
406 inst
->base_mrf
, /* starting mrf reg nr */
407 brw_vec8_grf(0, 0), /* src */
408 inst
->urb_write_flags
,
410 0, /* response len */
411 inst
->offset
, /* urb destination offset */
412 BRW_URB_SWIZZLE_INTERLEAVE
);
416 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
418 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
420 brw_null_reg(), /* dest */
421 inst
->base_mrf
, /* starting mrf reg nr */
423 inst
->urb_write_flags
,
425 0, /* response len */
426 inst
->offset
, /* urb destination offset */
427 BRW_URB_SWIZZLE_INTERLEAVE
);
431 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
433 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
435 brw_null_reg(), /* dest */
436 inst
->base_mrf
, /* starting mrf reg nr */
440 0, /* response len */
441 0, /* urb destination offset */
442 BRW_URB_SWIZZLE_INTERLEAVE
);
446 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
450 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
453 * Slot 0 Offset. This field, after adding to the Global Offset field
454 * in the message descriptor, specifies the offset (in 256-bit units)
455 * from the start of the URB entry, as referenced by URB Handle 0, at
456 * which the data will be accessed.
458 * Similar text describes DWORD M0.4, which is slot 1 offset.
460 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
461 * of the register for geometry shader invocations 0 and 1) by the
462 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
464 * We can do this with the following EU instruction:
466 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
468 brw_push_insn_state(p
);
469 brw_set_access_mode(p
, BRW_ALIGN_1
);
470 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
471 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
473 brw_set_access_mode(p
, BRW_ALIGN_16
);
474 brw_pop_insn_state(p
);
478 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
481 brw_push_insn_state(p
);
482 brw_set_access_mode(p
, BRW_ALIGN_1
);
483 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
485 /* If we think of the src and dst registers as composed of 8 DWORDs each,
486 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
487 * them to WORDs, and then pack them into DWORD 2 of dst.
489 * It's easier to get the EU to do this if we think of the src and dst
490 * registers as composed of 16 WORDS each; then, we want to pick up the
491 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
494 * We can do that by the following EU instruction:
496 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
498 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
499 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
500 brw_set_access_mode(p
, BRW_ALIGN_16
);
501 brw_pop_insn_state(p
);
505 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
508 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
510 brw_push_insn_state(p
);
511 brw_set_access_mode(p
, BRW_ALIGN_1
);
512 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
513 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
514 brw_set_access_mode(p
, BRW_ALIGN_16
);
515 brw_pop_insn_state(p
);
519 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
520 struct brw_reg index
)
522 int second_vertex_offset
;
525 second_vertex_offset
= 1;
527 second_vertex_offset
= 16;
529 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
531 /* Set up M1 (message payload). Only the block offsets in M1.0 and
532 * M1.4 are used, and the rest are ignored.
534 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
535 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
536 struct brw_reg index_0
= suboffset(vec1(index
), 0);
537 struct brw_reg index_4
= suboffset(vec1(index
), 4);
539 brw_push_insn_state(p
);
540 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
541 brw_set_access_mode(p
, BRW_ALIGN_1
);
543 brw_MOV(p
, m1_0
, index_0
);
545 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
546 index_4
.dw1
.ud
+= second_vertex_offset
;
547 brw_MOV(p
, m1_4
, index_4
);
549 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
552 brw_pop_insn_state(p
);
556 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
559 brw_push_insn_state(p
);
560 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
561 brw_set_access_mode(p
, BRW_ALIGN_1
);
563 struct brw_reg flags
= brw_flag_reg(0, 0);
564 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
565 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
567 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
568 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
569 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
571 brw_pop_insn_state(p
);
575 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
577 struct brw_reg index
)
579 struct brw_reg header
= brw_vec8_grf(0, 0);
581 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
583 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
589 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
590 else if (brw
->gen
== 5 || brw
->is_g4x
)
591 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
593 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
595 /* Each of the 8 channel enables is considered for whether each
598 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
599 brw_set_dest(p
, send
, dst
);
600 brw_set_src0(p
, send
, header
);
602 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
603 brw_set_dp_read_message(p
, send
,
604 255, /* binding table index: stateless access */
605 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
607 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
609 true, /* header_present */
614 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
617 struct brw_reg index
)
619 struct brw_reg header
= brw_vec8_grf(0, 0);
622 /* If the instruction is predicated, we'll predicate the send, not
625 brw_set_predicate_control(p
, false);
627 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
629 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
633 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
634 retype(src
, BRW_REGISTER_TYPE_D
));
639 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
640 else if (brw
->gen
== 6)
641 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
643 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
645 brw_set_predicate_control(p
, inst
->predicate
);
647 /* Pre-gen6, we have to specify write commits to ensure ordering
648 * between reads and writes within a thread. Afterwards, that's
649 * guaranteed and write commits only matter for inter-thread
653 write_commit
= false;
655 /* The visitor set up our destination register to be g0. This
656 * means that when the next read comes along, we will end up
657 * reading from g0 and causing a block on the write commit. For
658 * write-after-read, we are relying on the value of the previous
659 * read being used (and thus blocking on completion) before our
660 * write is executed. This means we have to be careful in
661 * instruction scheduling to not violate this assumption.
666 /* Each of the 8 channel enables is considered for whether each
669 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
670 brw_set_dest(p
, send
, dst
);
671 brw_set_src0(p
, send
, header
);
673 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
674 brw_set_dp_write_message(p
, send
,
675 255, /* binding table index: stateless access */
676 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
679 true, /* header present */
680 false, /* not a render target write */
681 write_commit
, /* rlen */
687 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
689 struct brw_reg index
,
690 struct brw_reg offset
)
692 assert(brw
->gen
<= 7);
693 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
694 index
.type
== BRW_REGISTER_TYPE_UD
);
695 uint32_t surf_index
= index
.dw1
.ud
;
697 struct brw_reg header
= brw_vec8_grf(0, 0);
699 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
701 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
707 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
708 else if (brw
->gen
== 5 || brw
->is_g4x
)
709 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
711 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
713 /* Each of the 8 channel enables is considered for whether each
716 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
717 brw_set_dest(p
, send
, dst
);
718 brw_set_src0(p
, send
, header
);
720 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
721 brw_set_dp_read_message(p
, send
,
723 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
725 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
727 true, /* header_present */
730 mark_surface_used(surf_index
);
734 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
736 struct brw_reg surf_index
,
737 struct brw_reg offset
)
739 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
740 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
742 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
743 brw_set_dest(p
, insn
, dst
);
744 brw_set_src0(p
, insn
, offset
);
745 brw_set_sampler_message(p
, insn
,
747 0, /* LD message ignores sampler unit */
748 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
751 false, /* no header */
752 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
755 mark_surface_used(surf_index
.dw1
.ud
);
759 * Generate assembly for a Vec4 IR instruction.
761 * \param instruction The Vec4 IR instruction to generate code for.
762 * \param dst The destination register.
763 * \param src An array of up to three source registers.
766 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
770 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
772 switch (inst
->opcode
) {
774 brw_MOV(p
, dst
, src
[0]);
777 brw_ADD(p
, dst
, src
[0], src
[1]);
780 brw_MUL(p
, dst
, src
[0], src
[1]);
782 case BRW_OPCODE_MACH
:
783 brw_set_acc_write_control(p
, 1);
784 brw_MACH(p
, dst
, src
[0], src
[1]);
785 brw_set_acc_write_control(p
, 0);
789 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
793 brw_FRC(p
, dst
, src
[0]);
795 case BRW_OPCODE_RNDD
:
796 brw_RNDD(p
, dst
, src
[0]);
798 case BRW_OPCODE_RNDE
:
799 brw_RNDE(p
, dst
, src
[0]);
801 case BRW_OPCODE_RNDZ
:
802 brw_RNDZ(p
, dst
, src
[0]);
806 brw_AND(p
, dst
, src
[0], src
[1]);
809 brw_OR(p
, dst
, src
[0], src
[1]);
812 brw_XOR(p
, dst
, src
[0], src
[1]);
815 brw_NOT(p
, dst
, src
[0]);
818 brw_ASR(p
, dst
, src
[0], src
[1]);
821 brw_SHR(p
, dst
, src
[0], src
[1]);
824 brw_SHL(p
, dst
, src
[0], src
[1]);
828 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
831 brw_SEL(p
, dst
, src
[0], src
[1]);
835 brw_DPH(p
, dst
, src
[0], src
[1]);
839 brw_DP4(p
, dst
, src
[0], src
[1]);
843 brw_DP3(p
, dst
, src
[0], src
[1]);
847 brw_DP2(p
, dst
, src
[0], src
[1]);
850 case BRW_OPCODE_F32TO16
:
851 brw_F32TO16(p
, dst
, src
[0]);
854 case BRW_OPCODE_F16TO32
:
855 brw_F16TO32(p
, dst
, src
[0]);
859 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
862 case BRW_OPCODE_BFREV
:
863 /* BFREV only supports UD type for src and dst. */
864 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
865 retype(src
[0], BRW_REGISTER_TYPE_UD
));
868 /* FBH only supports UD type for dst. */
869 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
872 /* FBL only supports UD type for dst. */
873 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
875 case BRW_OPCODE_CBIT
:
876 /* CBIT only supports UD type for dst. */
877 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
881 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
884 case BRW_OPCODE_BFI1
:
885 brw_BFI1(p
, dst
, src
[0], src
[1]);
887 case BRW_OPCODE_BFI2
:
888 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
892 if (inst
->src
[0].file
!= BAD_FILE
) {
893 /* The instruction has an embedded compare (only allowed on gen6) */
894 assert(brw
->gen
== 6);
895 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
897 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
898 brw_inst
->header
.predicate_control
= inst
->predicate
;
902 case BRW_OPCODE_ELSE
:
905 case BRW_OPCODE_ENDIF
:
910 brw_DO(p
, BRW_EXECUTE_8
);
913 case BRW_OPCODE_BREAK
:
915 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
917 case BRW_OPCODE_CONTINUE
:
918 /* FINISHME: We need to write the loop instruction support still. */
923 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
926 case BRW_OPCODE_WHILE
:
930 case SHADER_OPCODE_RCP
:
931 case SHADER_OPCODE_RSQ
:
932 case SHADER_OPCODE_SQRT
:
933 case SHADER_OPCODE_EXP2
:
934 case SHADER_OPCODE_LOG2
:
935 case SHADER_OPCODE_SIN
:
936 case SHADER_OPCODE_COS
:
938 generate_math1_gen6(inst
, dst
, src
[0]);
940 /* Also works for Gen7. */
941 generate_math1_gen4(inst
, dst
, src
[0]);
945 case SHADER_OPCODE_POW
:
946 case SHADER_OPCODE_INT_QUOTIENT
:
947 case SHADER_OPCODE_INT_REMAINDER
:
949 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
950 } else if (brw
->gen
== 6) {
951 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
953 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
957 case SHADER_OPCODE_TEX
:
958 case SHADER_OPCODE_TXD
:
959 case SHADER_OPCODE_TXF
:
960 case SHADER_OPCODE_TXF_MS
:
961 case SHADER_OPCODE_TXL
:
962 case SHADER_OPCODE_TXS
:
963 generate_tex(inst
, dst
, src
[0]);
966 case VS_OPCODE_URB_WRITE
:
967 generate_vs_urb_write(inst
);
970 case VS_OPCODE_SCRATCH_READ
:
971 generate_scratch_read(inst
, dst
, src
[0]);
974 case VS_OPCODE_SCRATCH_WRITE
:
975 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
978 case VS_OPCODE_PULL_CONSTANT_LOAD
:
979 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
982 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
983 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
986 case GS_OPCODE_URB_WRITE
:
987 generate_gs_urb_write(inst
);
990 case GS_OPCODE_THREAD_END
:
991 generate_gs_thread_end(inst
);
994 case GS_OPCODE_SET_WRITE_OFFSET
:
995 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
998 case GS_OPCODE_SET_VERTEX_COUNT
:
999 generate_gs_set_vertex_count(dst
, src
[0]);
1002 case GS_OPCODE_SET_DWORD_2_IMMED
:
1003 generate_gs_set_dword_2_immed(dst
, src
[0]);
1006 case SHADER_OPCODE_SHADER_TIME_ADD
:
1007 brw_shader_time_add(p
, src
[0], SURF_INDEX_VS_SHADER_TIME
);
1008 mark_surface_used(SURF_INDEX_VS_SHADER_TIME
);
1011 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1012 generate_unpack_flags(inst
, dst
);
1016 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1017 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in VS\n",
1018 opcode_descs
[inst
->opcode
].name
);
1020 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in VS", inst
->opcode
);
1027 vec4_generator::generate_code(exec_list
*instructions
)
1029 int last_native_insn_offset
= 0;
1030 const char *last_annotation_string
= NULL
;
1031 const void *last_annotation_ir
= NULL
;
1033 if (unlikely(debug_flag
)) {
1035 printf("Native code for vertex shader %d:\n", shader_prog
->Name
);
1037 printf("Native code for vertex program %d:\n", prog
->Id
);
1041 foreach_list(node
, instructions
) {
1042 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1043 struct brw_reg src
[3], dst
;
1045 if (unlikely(debug_flag
)) {
1046 if (last_annotation_ir
!= inst
->ir
) {
1047 last_annotation_ir
= inst
->ir
;
1048 if (last_annotation_ir
) {
1051 ((ir_instruction
*) last_annotation_ir
)->print();
1053 const prog_instruction
*vpi
;
1054 vpi
= (const prog_instruction
*) inst
->ir
;
1055 printf("%d: ", (int)(vpi
- prog
->Instructions
));
1056 _mesa_fprint_instruction_opt(stdout
, vpi
, 0,
1057 PROG_PRINT_DEBUG
, NULL
);
1062 if (last_annotation_string
!= inst
->annotation
) {
1063 last_annotation_string
= inst
->annotation
;
1064 if (last_annotation_string
)
1065 printf(" %s\n", last_annotation_string
);
1069 for (unsigned int i
= 0; i
< 3; i
++) {
1070 src
[i
] = inst
->get_src(this->prog_data
, i
);
1072 dst
= inst
->get_dst();
1074 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1075 brw_set_predicate_control(p
, inst
->predicate
);
1076 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1077 brw_set_saturate(p
, inst
->saturate
);
1078 brw_set_mask_control(p
, inst
->force_writemask_all
);
1080 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1082 generate_vec4_instruction(inst
, dst
, src
);
1084 if (inst
->no_dd_clear
|| inst
->no_dd_check
) {
1085 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1086 !"no_dd_check or no_dd_clear set for IR emitting more "
1087 "than 1 instruction");
1089 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
1091 if (inst
->no_dd_clear
)
1092 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
1093 if (inst
->no_dd_check
)
1094 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
1097 if (unlikely(debug_flag
)) {
1098 brw_dump_compile(p
, stdout
,
1099 last_native_insn_offset
, p
->next_insn_offset
);
1102 last_native_insn_offset
= p
->next_insn_offset
;
1105 if (unlikely(debug_flag
)) {
1111 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1112 * emit issues, it doesn't get the jump distances into the output,
1113 * which is often something we want to debug. So this is here in
1114 * case you're doing that.
1116 if (0 && unlikely(debug_flag
)) {
1117 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1122 vec4_generator::generate_assembly(exec_list
*instructions
,
1123 unsigned *assembly_size
)
1125 brw_set_access_mode(p
, BRW_ALIGN_16
);
1126 generate_code(instructions
);
1127 return brw_get_program(p
, assembly_size
);
1130 } /* namespace brw */