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i965: Add a debug flag for counting cycles spent in each compiled shader.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct brw_vs_compile *c,
137 struct gl_shader_program *prog,
138 void *mem_ctx)
139 : brw(brw), c(c), prog(prog), mem_ctx(mem_ctx)
140 {
141 intel = &brw->intel;
142 vp = &c->vp->program;
143
144 shader = prog ? prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
156 struct brw_reg dst,
157 struct brw_reg src)
158 {
159 brw_math(p,
160 dst,
161 brw_math_function(inst->opcode),
162 inst->base_mrf,
163 src,
164 BRW_MATH_DATA_VECTOR,
165 BRW_MATH_PRECISION_FULL);
166 }
167
168 static void
169 check_gen6_math_src_arg(struct brw_reg src)
170 {
171 /* Source swizzles are ignored. */
172 assert(!src.abs);
173 assert(!src.negate);
174 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
175 }
176
177 void
178 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
179 struct brw_reg dst,
180 struct brw_reg src)
181 {
182 /* Can't do writemask because math can't be align16. */
183 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
184 check_gen6_math_src_arg(src);
185
186 brw_set_access_mode(p, BRW_ALIGN_1);
187 brw_math(p,
188 dst,
189 brw_math_function(inst->opcode),
190 inst->base_mrf,
191 src,
192 BRW_MATH_DATA_SCALAR,
193 BRW_MATH_PRECISION_FULL);
194 brw_set_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 brw_math2(p,
204 dst,
205 brw_math_function(inst->opcode),
206 src0, src1);
207 }
208
209 void
210 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
211 struct brw_reg dst,
212 struct brw_reg src0,
213 struct brw_reg src1)
214 {
215 /* Can't do writemask because math can't be align16. */
216 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
217 /* Source swizzles are ignored. */
218 check_gen6_math_src_arg(src0);
219 check_gen6_math_src_arg(src1);
220
221 brw_set_access_mode(p, BRW_ALIGN_1);
222 brw_math2(p,
223 dst,
224 brw_math_function(inst->opcode),
225 src0, src1);
226 brw_set_access_mode(p, BRW_ALIGN_16);
227 }
228
229 void
230 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
231 struct brw_reg dst,
232 struct brw_reg src0,
233 struct brw_reg src1)
234 {
235 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
236 * "Message Payload":
237 *
238 * "Operand0[7]. For the INT DIV functions, this operand is the
239 * denominator."
240 * ...
241 * "Operand1[7]. For the INT DIV functions, this operand is the
242 * numerator."
243 */
244 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
245 struct brw_reg &op0 = is_int_div ? src1 : src0;
246 struct brw_reg &op1 = is_int_div ? src0 : src1;
247
248 brw_push_insn_state(p);
249 brw_set_saturate(p, false);
250 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
251 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
252 brw_pop_insn_state(p);
253
254 brw_math(p,
255 dst,
256 brw_math_function(inst->opcode),
257 inst->base_mrf,
258 op0,
259 BRW_MATH_DATA_VECTOR,
260 BRW_MATH_PRECISION_FULL);
261 }
262
263 void
264 vec4_generator::generate_tex(vec4_instruction *inst,
265 struct brw_reg dst,
266 struct brw_reg src)
267 {
268 int msg_type = -1;
269
270 if (intel->gen >= 5) {
271 switch (inst->opcode) {
272 case SHADER_OPCODE_TEX:
273 case SHADER_OPCODE_TXL:
274 if (inst->shadow_compare) {
275 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
276 } else {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
278 }
279 break;
280 case SHADER_OPCODE_TXD:
281 /* There is no sample_d_c message; comparisons are done manually. */
282 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
283 break;
284 case SHADER_OPCODE_TXF:
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
286 break;
287 case SHADER_OPCODE_TXS:
288 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
289 break;
290 default:
291 assert(!"should not get here: invalid VS texture opcode");
292 break;
293 }
294 } else {
295 switch (inst->opcode) {
296 case SHADER_OPCODE_TEX:
297 case SHADER_OPCODE_TXL:
298 if (inst->shadow_compare) {
299 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
300 assert(inst->mlen == 3);
301 } else {
302 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
303 assert(inst->mlen == 2);
304 }
305 break;
306 case SHADER_OPCODE_TXD:
307 /* There is no sample_d_c message; comparisons are done manually. */
308 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
309 assert(inst->mlen == 4);
310 break;
311 case SHADER_OPCODE_TXF:
312 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
313 assert(inst->mlen == 2);
314 break;
315 case SHADER_OPCODE_TXS:
316 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
317 assert(inst->mlen == 2);
318 break;
319 default:
320 assert(!"should not get here: invalid VS texture opcode");
321 break;
322 }
323 }
324
325 assert(msg_type != -1);
326
327 /* Load the message header if present. If there's a texture offset, we need
328 * to set it up explicitly and load the offset bitfield. Otherwise, we can
329 * use an implied move from g0 to the first message register.
330 */
331 if (inst->texture_offset) {
332 /* Explicitly set up the message header by copying g0 to the MRF. */
333 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
334 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
335
336 /* Then set the offset bits in DWord 2. */
337 brw_set_access_mode(p, BRW_ALIGN_1);
338 brw_MOV(p,
339 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
340 BRW_REGISTER_TYPE_UD),
341 brw_imm_uw(inst->texture_offset));
342 brw_set_access_mode(p, BRW_ALIGN_16);
343 } else if (inst->header_present) {
344 /* Set up an implied move from g0 to the MRF. */
345 src = brw_vec8_grf(0, 0);
346 }
347
348 uint32_t return_format;
349
350 switch (dst.type) {
351 case BRW_REGISTER_TYPE_D:
352 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
353 break;
354 case BRW_REGISTER_TYPE_UD:
355 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
356 break;
357 default:
358 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
359 break;
360 }
361
362 brw_SAMPLE(p,
363 dst,
364 inst->base_mrf,
365 src,
366 SURF_INDEX_VS_TEXTURE(inst->sampler),
367 inst->sampler,
368 WRITEMASK_XYZW,
369 msg_type,
370 1, /* response length */
371 inst->mlen,
372 inst->header_present,
373 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
374 return_format);
375 }
376
377 void
378 vec4_generator::generate_urb_write(vec4_instruction *inst)
379 {
380 brw_urb_WRITE(p,
381 brw_null_reg(), /* dest */
382 inst->base_mrf, /* starting mrf reg nr */
383 brw_vec8_grf(0, 0), /* src */
384 false, /* allocate */
385 true, /* used */
386 inst->mlen,
387 0, /* response len */
388 inst->eot, /* eot */
389 inst->eot, /* writes complete */
390 inst->offset, /* urb destination offset */
391 BRW_URB_SWIZZLE_INTERLEAVE);
392 }
393
394 void
395 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
396 struct brw_reg index)
397 {
398 int second_vertex_offset;
399
400 if (intel->gen >= 6)
401 second_vertex_offset = 1;
402 else
403 second_vertex_offset = 16;
404
405 m1 = retype(m1, BRW_REGISTER_TYPE_D);
406
407 /* Set up M1 (message payload). Only the block offsets in M1.0 and
408 * M1.4 are used, and the rest are ignored.
409 */
410 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
411 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
412 struct brw_reg index_0 = suboffset(vec1(index), 0);
413 struct brw_reg index_4 = suboffset(vec1(index), 4);
414
415 brw_push_insn_state(p);
416 brw_set_mask_control(p, BRW_MASK_DISABLE);
417 brw_set_access_mode(p, BRW_ALIGN_1);
418
419 brw_MOV(p, m1_0, index_0);
420
421 if (index.file == BRW_IMMEDIATE_VALUE) {
422 index_4.dw1.ud += second_vertex_offset;
423 brw_MOV(p, m1_4, index_4);
424 } else {
425 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
426 }
427
428 brw_pop_insn_state(p);
429 }
430
431 void
432 vec4_generator::generate_scratch_read(vec4_instruction *inst,
433 struct brw_reg dst,
434 struct brw_reg index)
435 {
436 struct brw_reg header = brw_vec8_grf(0, 0);
437
438 gen6_resolve_implied_move(p, &header, inst->base_mrf);
439
440 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
441 index);
442
443 uint32_t msg_type;
444
445 if (intel->gen >= 6)
446 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
447 else if (intel->gen == 5 || intel->is_g4x)
448 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
449 else
450 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
451
452 /* Each of the 8 channel enables is considered for whether each
453 * dword is written.
454 */
455 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
456 brw_set_dest(p, send, dst);
457 brw_set_src0(p, send, header);
458 if (intel->gen < 6)
459 send->header.destreg__conditionalmod = inst->base_mrf;
460 brw_set_dp_read_message(p, send,
461 255, /* binding table index: stateless access */
462 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
463 msg_type,
464 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
465 2, /* mlen */
466 true, /* header_present */
467 1 /* rlen */);
468 }
469
470 void
471 vec4_generator::generate_scratch_write(vec4_instruction *inst,
472 struct brw_reg dst,
473 struct brw_reg src,
474 struct brw_reg index)
475 {
476 struct brw_reg header = brw_vec8_grf(0, 0);
477 bool write_commit;
478
479 /* If the instruction is predicated, we'll predicate the send, not
480 * the header setup.
481 */
482 brw_set_predicate_control(p, false);
483
484 gen6_resolve_implied_move(p, &header, inst->base_mrf);
485
486 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
487 index);
488
489 brw_MOV(p,
490 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
491 retype(src, BRW_REGISTER_TYPE_D));
492
493 uint32_t msg_type;
494
495 if (intel->gen >= 7)
496 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
497 else if (intel->gen == 6)
498 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
499 else
500 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
501
502 brw_set_predicate_control(p, inst->predicate);
503
504 /* Pre-gen6, we have to specify write commits to ensure ordering
505 * between reads and writes within a thread. Afterwards, that's
506 * guaranteed and write commits only matter for inter-thread
507 * synchronization.
508 */
509 if (intel->gen >= 6) {
510 write_commit = false;
511 } else {
512 /* The visitor set up our destination register to be g0. This
513 * means that when the next read comes along, we will end up
514 * reading from g0 and causing a block on the write commit. For
515 * write-after-read, we are relying on the value of the previous
516 * read being used (and thus blocking on completion) before our
517 * write is executed. This means we have to be careful in
518 * instruction scheduling to not violate this assumption.
519 */
520 write_commit = true;
521 }
522
523 /* Each of the 8 channel enables is considered for whether each
524 * dword is written.
525 */
526 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
527 brw_set_dest(p, send, dst);
528 brw_set_src0(p, send, header);
529 if (intel->gen < 6)
530 send->header.destreg__conditionalmod = inst->base_mrf;
531 brw_set_dp_write_message(p, send,
532 255, /* binding table index: stateless access */
533 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
534 msg_type,
535 3, /* mlen */
536 true, /* header present */
537 false, /* not a render target write */
538 write_commit, /* rlen */
539 false, /* eot */
540 write_commit);
541 }
542
543 void
544 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
545 struct brw_reg dst,
546 struct brw_reg index,
547 struct brw_reg offset)
548 {
549 assert(index.file == BRW_IMMEDIATE_VALUE &&
550 index.type == BRW_REGISTER_TYPE_UD);
551 uint32_t surf_index = index.dw1.ud;
552
553 if (intel->gen == 7) {
554 gen6_resolve_implied_move(p, &offset, inst->base_mrf);
555 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
556 brw_set_dest(p, insn, dst);
557 brw_set_src0(p, insn, offset);
558 brw_set_sampler_message(p, insn,
559 surf_index,
560 0, /* LD message ignores sampler unit */
561 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
562 1, /* rlen */
563 1, /* mlen */
564 false, /* no header */
565 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
566 0);
567 return;
568 }
569
570 struct brw_reg header = brw_vec8_grf(0, 0);
571
572 gen6_resolve_implied_move(p, &header, inst->base_mrf);
573
574 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
575 offset);
576
577 uint32_t msg_type;
578
579 if (intel->gen >= 6)
580 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
581 else if (intel->gen == 5 || intel->is_g4x)
582 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
583 else
584 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
585
586 /* Each of the 8 channel enables is considered for whether each
587 * dword is written.
588 */
589 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
590 brw_set_dest(p, send, dst);
591 brw_set_src0(p, send, header);
592 if (intel->gen < 6)
593 send->header.destreg__conditionalmod = inst->base_mrf;
594 brw_set_dp_read_message(p, send,
595 surf_index,
596 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
597 msg_type,
598 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
599 2, /* mlen */
600 true, /* header_present */
601 1 /* rlen */);
602 }
603
604 void
605 vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
606 struct brw_reg dst,
607 struct brw_reg *src)
608 {
609 vec4_instruction *inst = (vec4_instruction *)instruction;
610
611 switch (inst->opcode) {
612 case SHADER_OPCODE_RCP:
613 case SHADER_OPCODE_RSQ:
614 case SHADER_OPCODE_SQRT:
615 case SHADER_OPCODE_EXP2:
616 case SHADER_OPCODE_LOG2:
617 case SHADER_OPCODE_SIN:
618 case SHADER_OPCODE_COS:
619 if (intel->gen == 6) {
620 generate_math1_gen6(inst, dst, src[0]);
621 } else {
622 /* Also works for Gen7. */
623 generate_math1_gen4(inst, dst, src[0]);
624 }
625 break;
626
627 case SHADER_OPCODE_POW:
628 case SHADER_OPCODE_INT_QUOTIENT:
629 case SHADER_OPCODE_INT_REMAINDER:
630 if (intel->gen >= 7) {
631 generate_math2_gen7(inst, dst, src[0], src[1]);
632 } else if (intel->gen == 6) {
633 generate_math2_gen6(inst, dst, src[0], src[1]);
634 } else {
635 generate_math2_gen4(inst, dst, src[0], src[1]);
636 }
637 break;
638
639 case SHADER_OPCODE_TEX:
640 case SHADER_OPCODE_TXD:
641 case SHADER_OPCODE_TXF:
642 case SHADER_OPCODE_TXL:
643 case SHADER_OPCODE_TXS:
644 generate_tex(inst, dst, src[0]);
645 break;
646
647 case VS_OPCODE_URB_WRITE:
648 generate_urb_write(inst);
649 break;
650
651 case VS_OPCODE_SCRATCH_READ:
652 generate_scratch_read(inst, dst, src[0]);
653 break;
654
655 case VS_OPCODE_SCRATCH_WRITE:
656 generate_scratch_write(inst, dst, src[0], src[1]);
657 break;
658
659 case VS_OPCODE_PULL_CONSTANT_LOAD:
660 generate_pull_constant_load(inst, dst, src[0], src[1]);
661 break;
662
663 case SHADER_OPCODE_SHADER_TIME_ADD:
664 brw_shader_time_add(p, inst->base_mrf, SURF_INDEX_VS_SHADER_TIME);
665 break;
666
667 default:
668 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
669 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
670 opcode_descs[inst->opcode].name);
671 } else {
672 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
673 }
674 abort();
675 }
676 }
677
678 void
679 vec4_generator::generate_code(exec_list *instructions)
680 {
681 int last_native_insn_offset = 0;
682 const char *last_annotation_string = NULL;
683 const void *last_annotation_ir = NULL;
684
685 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
686 if (shader) {
687 printf("Native code for vertex shader %d:\n", prog->Name);
688 } else {
689 printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
690 }
691 }
692
693 foreach_list(node, instructions) {
694 vec4_instruction *inst = (vec4_instruction *)node;
695 struct brw_reg src[3], dst;
696
697 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
698 if (last_annotation_ir != inst->ir) {
699 last_annotation_ir = inst->ir;
700 if (last_annotation_ir) {
701 printf(" ");
702 if (shader) {
703 ((ir_instruction *) last_annotation_ir)->print();
704 } else {
705 const prog_instruction *vpi;
706 vpi = (const prog_instruction *) inst->ir;
707 printf("%d: ", (int)(vpi - vp->Base.Instructions));
708 _mesa_fprint_instruction_opt(stdout, vpi, 0,
709 PROG_PRINT_DEBUG, NULL);
710 }
711 printf("\n");
712 }
713 }
714 if (last_annotation_string != inst->annotation) {
715 last_annotation_string = inst->annotation;
716 if (last_annotation_string)
717 printf(" %s\n", last_annotation_string);
718 }
719 }
720
721 for (unsigned int i = 0; i < 3; i++) {
722 src[i] = inst->get_src(i);
723 }
724 dst = inst->get_dst();
725
726 brw_set_conditionalmod(p, inst->conditional_mod);
727 brw_set_predicate_control(p, inst->predicate);
728 brw_set_predicate_inverse(p, inst->predicate_inverse);
729 brw_set_saturate(p, inst->saturate);
730 brw_set_mask_control(p, inst->force_writemask_all);
731
732 switch (inst->opcode) {
733 case BRW_OPCODE_MOV:
734 brw_MOV(p, dst, src[0]);
735 break;
736 case BRW_OPCODE_ADD:
737 brw_ADD(p, dst, src[0], src[1]);
738 break;
739 case BRW_OPCODE_MUL:
740 brw_MUL(p, dst, src[0], src[1]);
741 break;
742 case BRW_OPCODE_MACH:
743 brw_set_acc_write_control(p, 1);
744 brw_MACH(p, dst, src[0], src[1]);
745 brw_set_acc_write_control(p, 0);
746 break;
747
748 case BRW_OPCODE_FRC:
749 brw_FRC(p, dst, src[0]);
750 break;
751 case BRW_OPCODE_RNDD:
752 brw_RNDD(p, dst, src[0]);
753 break;
754 case BRW_OPCODE_RNDE:
755 brw_RNDE(p, dst, src[0]);
756 break;
757 case BRW_OPCODE_RNDZ:
758 brw_RNDZ(p, dst, src[0]);
759 break;
760
761 case BRW_OPCODE_AND:
762 brw_AND(p, dst, src[0], src[1]);
763 break;
764 case BRW_OPCODE_OR:
765 brw_OR(p, dst, src[0], src[1]);
766 break;
767 case BRW_OPCODE_XOR:
768 brw_XOR(p, dst, src[0], src[1]);
769 break;
770 case BRW_OPCODE_NOT:
771 brw_NOT(p, dst, src[0]);
772 break;
773 case BRW_OPCODE_ASR:
774 brw_ASR(p, dst, src[0], src[1]);
775 break;
776 case BRW_OPCODE_SHR:
777 brw_SHR(p, dst, src[0], src[1]);
778 break;
779 case BRW_OPCODE_SHL:
780 brw_SHL(p, dst, src[0], src[1]);
781 break;
782
783 case BRW_OPCODE_CMP:
784 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
785 break;
786 case BRW_OPCODE_SEL:
787 brw_SEL(p, dst, src[0], src[1]);
788 break;
789
790 case BRW_OPCODE_DPH:
791 brw_DPH(p, dst, src[0], src[1]);
792 break;
793
794 case BRW_OPCODE_DP4:
795 brw_DP4(p, dst, src[0], src[1]);
796 break;
797
798 case BRW_OPCODE_DP3:
799 brw_DP3(p, dst, src[0], src[1]);
800 break;
801
802 case BRW_OPCODE_DP2:
803 brw_DP2(p, dst, src[0], src[1]);
804 break;
805
806 case BRW_OPCODE_IF:
807 if (inst->src[0].file != BAD_FILE) {
808 /* The instruction has an embedded compare (only allowed on gen6) */
809 assert(intel->gen == 6);
810 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
811 } else {
812 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
813 brw_inst->header.predicate_control = inst->predicate;
814 }
815 break;
816
817 case BRW_OPCODE_ELSE:
818 brw_ELSE(p);
819 break;
820 case BRW_OPCODE_ENDIF:
821 brw_ENDIF(p);
822 break;
823
824 case BRW_OPCODE_DO:
825 brw_DO(p, BRW_EXECUTE_8);
826 break;
827
828 case BRW_OPCODE_BREAK:
829 brw_BREAK(p);
830 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
831 break;
832 case BRW_OPCODE_CONTINUE:
833 /* FINISHME: We need to write the loop instruction support still. */
834 if (intel->gen >= 6)
835 gen6_CONT(p);
836 else
837 brw_CONT(p);
838 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
839 break;
840
841 case BRW_OPCODE_WHILE:
842 brw_WHILE(p);
843 break;
844
845 default:
846 generate_vs_instruction(inst, dst, src);
847 break;
848 }
849
850 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
851 brw_dump_compile(p, stdout,
852 last_native_insn_offset, p->next_insn_offset);
853 }
854
855 last_native_insn_offset = p->next_insn_offset;
856 }
857
858 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
859 printf("\n");
860 }
861
862 brw_set_uip_jip(p);
863
864 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
865 * emit issues, it doesn't get the jump distances into the output,
866 * which is often something we want to debug. So this is here in
867 * case you're doing that.
868 */
869 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
870 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
871 }
872 }
873
874 const unsigned *
875 vec4_generator::generate_assembly(exec_list *instructions,
876 unsigned *assembly_size)
877 {
878 brw_set_access_mode(p, BRW_ALIGN_16);
879 generate_code(instructions);
880 return brw_get_program(p, assembly_size);
881 }
882
883 } /* namespace brw */