src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45
  46          /* Do GL_FIXED rescaling for GLES2.0.  Our GL_FIXED
  47           * attributes come in as floating point conversions of the
  48           * integer values.
  49           */
  50          if (c->key.gl_fixed_input_size[i] != 0) {
  51             struct brw_reg reg = brw_vec8_grf(attribute_map[i], 0);
  52
  53             brw_MUL(p,
  54                     brw_writemask(reg, (1 << c->key.gl_fixed_input_size[i]) - 1),
  55                     reg, brw_imm_f(1.0 / 65536.0));
  56          }
  57       }
  58    }
  59
  60    foreach_list(node, &this->instructions) {
  61       vec4_instruction *inst = (vec4_instruction *)node;
  62
  63       for (int i = 0; i < 3; i++) {
  64          if (inst->src[i].file != ATTR)
  65             continue;
  66
  67          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  68
  69          struct brw_reg reg = brw_vec8_grf(grf, 0);
  70          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  71          if (inst->src[i].abs)
  72             reg = brw_abs(reg);
  73          if (inst->src[i].negate)
  74             reg = negate(reg);
  75
  76          inst->src[i].file = HW_REG;
  77          inst->src[i].fixed_hw_reg = reg;
  78       }
  79    }
  80
  81    /* The BSpec says we always have to read at least one thing from
  82     * the VF, and it appears that the hardware wedges otherwise.
  83     */
  84    if (nr_attributes == 0)
  85       nr_attributes = 1;
  86
  87    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  88
  89    return payload_reg + nr_attributes;
  90 }
  91
  92 int
  93 vec4_visitor::setup_uniforms(int reg)
  94 {
  95    /* User clip planes from curbe:
  96     */
  97    if (c->key.nr_userclip) {
  98       if (intel->gen >= 6) {
  99          for (int i = 0; i < c->key.nr_userclip; i++) {
 100             c->userplane[i] = stride(brw_vec4_grf(reg + i / 2,
 101                                                   (i % 2) * 4), 0, 4, 1);
 102          }
 103          reg += ALIGN(c->key.nr_userclip, 2) / 2;
 104       } else {
 105          for (int i = 0; i < c->key.nr_userclip; i++) {
 106             c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2,
 107                                                   (i % 2) * 4), 0, 4, 1);
 108          }
 109          reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2;
 110       }
 111    }
 112
 113    /* The pre-gen6 VS requires that some push constants get loaded no
 114     * matter what, or the GPU would hang.
 115     */
 116    if (intel->gen < 6 && this->uniforms == 0) {
 117       this->uniform_vector_size[this->uniforms] = 1;
 118
 119       for (unsigned int i = 0; i < 4; i++) {
 120          unsigned int slot = this->uniforms * 4 + i;
 121
 122          c->prog_data.param[slot] = NULL;
 123       }
 124
 125       this->uniforms++;
 126       reg++;
 127    } else {
 128       reg += ALIGN(uniforms, 2) / 2;
 129    }
 130
 131    c->prog_data.nr_params = this->uniforms * 4;
 132
 133    c->prog_data.curb_read_length = reg - 1;
 134    c->prog_data.uses_new_param_layout = true;
 135
 136    return reg;
 137 }
 138
 139 void
 140 vec4_visitor::setup_payload(void)
 141 {
 142    int reg = 0;
 143
 144    /* The payload always contains important data in g0, which contains
 145     * the URB handles that are passed on to the URB write at the end
 146     * of the thread.  So, we always start push constants at g1.
 147     */
 148    reg++;
 149
 150    reg = setup_uniforms(reg);
 151
 152    reg = setup_attributes(reg);
 153
 154    this->first_non_payload_grf = reg;
 155 }
 156
 157 struct brw_reg
 158 vec4_instruction::get_dst(void)
 159 {
 160    struct brw_reg brw_reg;
 161
 162    switch (dst.file) {
 163    case GRF:
 164       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 165       brw_reg = retype(brw_reg, dst.type);
 166       brw_reg.dw1.bits.writemask = dst.writemask;
 167       break;
 168
 169    case HW_REG:
 170       brw_reg = dst.fixed_hw_reg;
 171       break;
 172
 173    case BAD_FILE:
 174       brw_reg = brw_null_reg();
 175       break;
 176
 177    default:
 178       assert(!"not reached");
 179       brw_reg = brw_null_reg();
 180       break;
 181    }
 182    return brw_reg;
 183 }
 184
 185 struct brw_reg
 186 vec4_instruction::get_src(int i)
 187 {
 188    struct brw_reg brw_reg;
 189
 190    switch (src[i].file) {
 191    case GRF:
 192       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 193       brw_reg = retype(brw_reg, src[i].type);
 194       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 195       if (src[i].abs)
 196          brw_reg = brw_abs(brw_reg);
 197       if (src[i].negate)
 198          brw_reg = negate(brw_reg);
 199       break;
 200
 201    case IMM:
 202       switch (src[i].type) {
 203       case BRW_REGISTER_TYPE_F:
 204          brw_reg = brw_imm_f(src[i].imm.f);
 205          break;
 206       case BRW_REGISTER_TYPE_D:
 207          brw_reg = brw_imm_d(src[i].imm.i);
 208          break;
 209       case BRW_REGISTER_TYPE_UD:
 210          brw_reg = brw_imm_ud(src[i].imm.u);
 211          break;
 212       default:
 213          assert(!"not reached");
 214          brw_reg = brw_null_reg();
 215          break;
 216       }
 217       break;
 218
 219    case UNIFORM:
 220       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 221                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 222                        0, 4, 1);
 223       brw_reg = retype(brw_reg, src[i].type);
 224       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 225       if (src[i].abs)
 226          brw_reg = brw_abs(brw_reg);
 227       if (src[i].negate)
 228          brw_reg = negate(brw_reg);
 229
 230       /* This should have been moved to pull constants. */
 231       assert(!src[i].reladdr);
 232       break;
 233
 234    case HW_REG:
 235       brw_reg = src[i].fixed_hw_reg;
 236       break;
 237
 238    case BAD_FILE:
 239       /* Probably unused. */
 240       brw_reg = brw_null_reg();
 241       break;
 242    case ATTR:
 243    default:
 244       assert(!"not reached");
 245       brw_reg = brw_null_reg();
 246       break;
 247    }
 248
 249    return brw_reg;
 250 }
 251
 252 void
 253 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 254                                   struct brw_reg dst,
 255                                   struct brw_reg src)
 256 {
 257    brw_math(p,
 258             dst,
 259             brw_math_function(inst->opcode),
 260             BRW_MATH_SATURATE_NONE,
 261             inst->base_mrf,
 262             src,
 263             BRW_MATH_DATA_SCALAR,
 264             BRW_MATH_PRECISION_FULL);
 265 }
 266
 267 static void
 268 check_gen6_math_src_arg(struct brw_reg src)
 269 {
 270    /* Source swizzles are ignored. */
 271    assert(!src.abs);
 272    assert(!src.negate);
 273    assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
 274 }
 275
 276 void
 277 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 278                                   struct brw_reg dst,
 279                                   struct brw_reg src)
 280 {
 281    /* Can't do writemask because math can't be align16. */
 282    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 283    check_gen6_math_src_arg(src);
 284
 285    brw_set_access_mode(p, BRW_ALIGN_1);
 286    brw_math(p,
 287             dst,
 288             brw_math_function(inst->opcode),
 289             BRW_MATH_SATURATE_NONE,
 290             inst->base_mrf,
 291             src,
 292             BRW_MATH_DATA_SCALAR,
 293             BRW_MATH_PRECISION_FULL);
 294    brw_set_access_mode(p, BRW_ALIGN_16);
 295 }
 296
 297 void
 298 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 299                                   struct brw_reg dst,
 300                                   struct brw_reg src0,
 301                                   struct brw_reg src1)
 302 {
 303    /* Can't do writemask because math can't be align16. */
 304    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 305    /* Source swizzles are ignored. */
 306    check_gen6_math_src_arg(src0);
 307    check_gen6_math_src_arg(src1);
 308
 309    brw_set_access_mode(p, BRW_ALIGN_1);
 310    brw_math2(p,
 311              dst,
 312              brw_math_function(inst->opcode),
 313              src0, src1);
 314    brw_set_access_mode(p, BRW_ALIGN_16);
 315 }
 316
 317 void
 318 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 319                                   struct brw_reg dst,
 320                                   struct brw_reg src0,
 321                                   struct brw_reg src1)
 322 {
 323    /* Can't do writemask because math can't be align16. */
 324    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 325
 326    brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
 327
 328    brw_set_access_mode(p, BRW_ALIGN_1);
 329    brw_math(p,
 330             dst,
 331             brw_math_function(inst->opcode),
 332             BRW_MATH_SATURATE_NONE,
 333             inst->base_mrf,
 334             src0,
 335             BRW_MATH_DATA_VECTOR,
 336             BRW_MATH_PRECISION_FULL);
 337    brw_set_access_mode(p, BRW_ALIGN_16);
 338 }
 339
 340 void
 341 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 342 {
 343    brw_urb_WRITE(p,
 344                  brw_null_reg(), /* dest */
 345                  inst->base_mrf, /* starting mrf reg nr */
 346                  brw_vec8_grf(0, 0), /* src */
 347                  false,         /* allocate */
 348                  true,          /* used */
 349                  inst->mlen,
 350                  0,             /* response len */
 351                  inst->eot,     /* eot */
 352                  inst->eot,     /* writes complete */
 353                  inst->offset,  /* urb destination offset */
 354                  BRW_URB_SWIZZLE_INTERLEAVE);
 355 }
 356
 357 void
 358 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 359                                                 struct brw_reg index)
 360 {
 361    int second_vertex_offset;
 362
 363    if (intel->gen >= 6)
 364       second_vertex_offset = 1;
 365    else
 366       second_vertex_offset = 16;
 367
 368    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 369
 370    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 371     * M1.4 are used, and the rest are ignored.
 372     */
 373    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 374    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 375    struct brw_reg index_0 = suboffset(vec1(index), 0);
 376    struct brw_reg index_4 = suboffset(vec1(index), 4);
 377
 378    brw_push_insn_state(p);
 379    brw_set_mask_control(p, BRW_MASK_DISABLE);
 380    brw_set_access_mode(p, BRW_ALIGN_1);
 381
 382    brw_MOV(p, m1_0, index_0);
 383
 384    brw_set_predicate_inverse(p, true);
 385    if (index.file == BRW_IMMEDIATE_VALUE) {
 386       index_4.dw1.ud++;
 387       brw_MOV(p, m1_4, index_4);
 388    } else {
 389       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 390    }
 391
 392    brw_pop_insn_state(p);
 393 }
 394
 395 void
 396 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 397                                     struct brw_reg dst,
 398                                     struct brw_reg index)
 399 {
 400    if (intel->gen >= 6) {
 401       brw_push_insn_state(p);
 402       brw_set_mask_control(p, BRW_MASK_DISABLE);
 403       brw_MOV(p,
 404               retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
 405               retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
 406       brw_pop_insn_state(p);
 407    }
 408
 409    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 410                                      index);
 411
 412    uint32_t msg_type;
 413
 414    if (intel->gen >= 6)
 415       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 416    else if (intel->gen == 5 || intel->is_g4x)
 417       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 418    else
 419       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 420
 421    /* Each of the 8 channel enables is considered for whether each
 422     * dword is written.
 423     */
 424    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 425    brw_set_dest(p, send, dst);
 426    brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
 427    brw_set_dp_read_message(p, send,
 428                            255, /* binding table index: stateless access */
 429                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 430                            msg_type,
 431                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 432                            2, /* mlen */
 433                            1 /* rlen */);
 434 }
 435
 436 void
 437 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 438                                      struct brw_reg dst,
 439                                      struct brw_reg src,
 440                                      struct brw_reg index)
 441 {
 442    /* If the instruction is predicated, we'll predicate the send, not
 443     * the header setup.
 444     */
 445    brw_set_predicate_control(p, false);
 446
 447    if (intel->gen >= 6) {
 448       brw_push_insn_state(p);
 449       brw_set_mask_control(p, BRW_MASK_DISABLE);
 450       brw_MOV(p,
 451               retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
 452               retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
 453       brw_pop_insn_state(p);
 454    }
 455
 456    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 457                                      index);
 458
 459    brw_MOV(p,
 460            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 461            retype(src, BRW_REGISTER_TYPE_D));
 462
 463    uint32_t msg_type;
 464
 465    if (intel->gen >= 6)
 466       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 467    else
 468       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 469
 470    brw_set_predicate_control(p, inst->predicate);
 471
 472    /* Each of the 8 channel enables is considered for whether each
 473     * dword is written.
 474     */
 475    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 476    brw_set_dest(p, send, dst);
 477    brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
 478    brw_set_dp_write_message(p, send,
 479                             255, /* binding table index: stateless access */
 480                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 481                             msg_type,
 482                             3, /* mlen */
 483                             true, /* header present */
 484                             false, /* pixel scoreboard */
 485                             0, /* rlen */
 486                             false, /* eot */
 487                             false /* commit */);
 488 }
 489
 490 void
 491 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 492                                           struct brw_reg dst,
 493                                           struct brw_reg index)
 494 {
 495    struct brw_reg header = brw_vec8_grf(0, 0);
 496
 497    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 498
 499    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 500            index);
 501
 502    uint32_t msg_type;
 503
 504    if (intel->gen >= 6)
 505       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 506    else if (intel->gen == 5 || intel->is_g4x)
 507       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 508    else
 509       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 510
 511    /* Each of the 8 channel enables is considered for whether each
 512     * dword is written.
 513     */
 514    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 515    brw_set_dest(p, send, dst);
 516    brw_set_src0(p, send, header);
 517    brw_set_dp_read_message(p, send,
 518                            SURF_INDEX_VERT_CONST_BUFFER,
 519                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 520                            msg_type,
 521                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 522                            2, /* mlen */
 523                            1 /* rlen */);
 524 }
 525
 526 void
 527 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 528                                       struct brw_reg dst,
 529                                       struct brw_reg *src)
 530 {
 531    vec4_instruction *inst = (vec4_instruction *)instruction;
 532
 533    switch (inst->opcode) {
 534    case SHADER_OPCODE_RCP:
 535    case SHADER_OPCODE_RSQ:
 536    case SHADER_OPCODE_SQRT:
 537    case SHADER_OPCODE_EXP2:
 538    case SHADER_OPCODE_LOG2:
 539    case SHADER_OPCODE_SIN:
 540    case SHADER_OPCODE_COS:
 541       if (intel->gen >= 6) {
 542          generate_math1_gen6(inst, dst, src[0]);
 543       } else {
 544          generate_math1_gen4(inst, dst, src[0]);
 545       }
 546       break;
 547
 548    case SHADER_OPCODE_POW:
 549       if (intel->gen >= 6) {
 550          generate_math2_gen6(inst, dst, src[0], src[1]);
 551       } else {
 552          generate_math2_gen4(inst, dst, src[0], src[1]);
 553       }
 554       break;
 555
 556    case VS_OPCODE_URB_WRITE:
 557       generate_urb_write(inst);
 558       break;
 559
 560    case VS_OPCODE_SCRATCH_READ:
 561       generate_scratch_read(inst, dst, src[0]);
 562       break;
 563
 564    case VS_OPCODE_SCRATCH_WRITE:
 565       generate_scratch_write(inst, dst, src[0], src[1]);
 566       break;
 567
 568    case VS_OPCODE_PULL_CONSTANT_LOAD:
 569       generate_pull_constant_load(inst, dst, src[0]);
 570       break;
 571
 572    default:
 573       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 574          fail("unsupported opcode in `%s' in VS\n",
 575               brw_opcodes[inst->opcode].name);
 576       } else {
 577          fail("Unsupported opcode %d in VS", inst->opcode);
 578       }
 579    }
 580 }
 581
 582 bool
 583 vec4_visitor::run()
 584 {
 585    /* Generate VS IR for main().  (the visitor only descends into
 586     * functions called "main").
 587     */
 588    visit_instructions(shader->ir);
 589
 590    emit_urb_writes();
 591
 592    /* Before any optimization, push array accesses out to scratch
 593     * space where we need them to be.  This pass may allocate new
 594     * virtual GRFs, so we want to do it early.  It also makes sure
 595     * that we have reladdr computations available for CSE, since we'll
 596     * often do repeated subexpressions for those.
 597     */
 598    move_grf_array_access_to_scratch();
 599    move_uniform_array_access_to_pull_constants();
 600
 601    bool progress;
 602    do {
 603       progress = false;
 604       progress = dead_code_eliminate() || progress;
 605    } while (progress);
 606
 607    pack_uniform_registers();
 608
 609    if (failed)
 610       return false;
 611
 612    setup_payload();
 613    reg_allocate();
 614
 615    if (failed)
 616       return false;
 617
 618    brw_set_access_mode(p, BRW_ALIGN_16);
 619
 620    generate_code();
 621
 622    return !failed;
 623 }
 624
 625 void
 626 vec4_visitor::generate_code()
 627 {
 628    int last_native_inst = p->nr_insn;
 629    const char *last_annotation_string = NULL;
 630    ir_instruction *last_annotation_ir = NULL;
 631
 632    int loop_stack_array_size = 16;
 633    int loop_stack_depth = 0;
 634    brw_instruction **loop_stack =
 635       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 636    int *if_depth_in_loop =
 637       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 638
 639
 640    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 641       printf("Native code for vertex shader %d:\n", prog->Name);
 642    }
 643
 644    foreach_list(node, &this->instructions) {
 645       vec4_instruction *inst = (vec4_instruction *)node;
 646       struct brw_reg src[3], dst;
 647
 648       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 649          if (last_annotation_ir != inst->ir) {
 650             last_annotation_ir = inst->ir;
 651             if (last_annotation_ir) {
 652                printf("   ");
 653                last_annotation_ir->print();
 654                printf("\n");
 655             }
 656          }
 657          if (last_annotation_string != inst->annotation) {
 658             last_annotation_string = inst->annotation;
 659             if (last_annotation_string)
 660                printf("   %s\n", last_annotation_string);
 661          }
 662       }
 663
 664       for (unsigned int i = 0; i < 3; i++) {
 665          src[i] = inst->get_src(i);
 666       }
 667       dst = inst->get_dst();
 668
 669       brw_set_conditionalmod(p, inst->conditional_mod);
 670       brw_set_predicate_control(p, inst->predicate);
 671       brw_set_predicate_inverse(p, inst->predicate_inverse);
 672       brw_set_saturate(p, inst->saturate);
 673
 674       switch (inst->opcode) {
 675       case BRW_OPCODE_MOV:
 676          brw_MOV(p, dst, src[0]);
 677          break;
 678       case BRW_OPCODE_ADD:
 679          brw_ADD(p, dst, src[0], src[1]);
 680          break;
 681       case BRW_OPCODE_MUL:
 682          brw_MUL(p, dst, src[0], src[1]);
 683          break;
 684       case BRW_OPCODE_MACH:
 685          brw_set_acc_write_control(p, 1);
 686          brw_MACH(p, dst, src[0], src[1]);
 687          brw_set_acc_write_control(p, 0);
 688          break;
 689
 690       case BRW_OPCODE_FRC:
 691          brw_FRC(p, dst, src[0]);
 692          break;
 693       case BRW_OPCODE_RNDD:
 694          brw_RNDD(p, dst, src[0]);
 695          break;
 696       case BRW_OPCODE_RNDE:
 697          brw_RNDE(p, dst, src[0]);
 698          break;
 699       case BRW_OPCODE_RNDZ:
 700          brw_RNDZ(p, dst, src[0]);
 701          break;
 702
 703       case BRW_OPCODE_AND:
 704          brw_AND(p, dst, src[0], src[1]);
 705          break;
 706       case BRW_OPCODE_OR:
 707          brw_OR(p, dst, src[0], src[1]);
 708          break;
 709       case BRW_OPCODE_XOR:
 710          brw_XOR(p, dst, src[0], src[1]);
 711          break;
 712       case BRW_OPCODE_NOT:
 713          brw_NOT(p, dst, src[0]);
 714          break;
 715       case BRW_OPCODE_ASR:
 716          brw_ASR(p, dst, src[0], src[1]);
 717          break;
 718       case BRW_OPCODE_SHR:
 719          brw_SHR(p, dst, src[0], src[1]);
 720          break;
 721       case BRW_OPCODE_SHL:
 722          brw_SHL(p, dst, src[0], src[1]);
 723          break;
 724
 725       case BRW_OPCODE_CMP:
 726          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 727          break;
 728       case BRW_OPCODE_SEL:
 729          brw_SEL(p, dst, src[0], src[1]);
 730          break;
 731
 732       case BRW_OPCODE_DP4:
 733          brw_DP4(p, dst, src[0], src[1]);
 734          break;
 735
 736       case BRW_OPCODE_DP3:
 737          brw_DP3(p, dst, src[0], src[1]);
 738          break;
 739
 740       case BRW_OPCODE_DP2:
 741          brw_DP2(p, dst, src[0], src[1]);
 742          break;
 743
 744       case BRW_OPCODE_IF:
 745          if (inst->src[0].file != BAD_FILE) {
 746             /* The instruction has an embedded compare (only allowed on gen6) */
 747             assert(intel->gen == 6);
 748             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 749          } else {
 750             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 751             brw_inst->header.predicate_control = inst->predicate;
 752          }
 753          if_depth_in_loop[loop_stack_depth]++;
 754          break;
 755
 756       case BRW_OPCODE_ELSE:
 757          brw_ELSE(p);
 758          break;
 759       case BRW_OPCODE_ENDIF:
 760          brw_ENDIF(p);
 761          if_depth_in_loop[loop_stack_depth]--;
 762          break;
 763
 764       case BRW_OPCODE_DO:
 765          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 766          if (loop_stack_array_size <= loop_stack_depth) {
 767             loop_stack_array_size *= 2;
 768             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 769                                   loop_stack_array_size);
 770             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 771                                         loop_stack_array_size);
 772          }
 773          if_depth_in_loop[loop_stack_depth] = 0;
 774          break;
 775
 776       case BRW_OPCODE_BREAK:
 777          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 778          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 779          break;
 780       case BRW_OPCODE_CONTINUE:
 781          /* FINISHME: We need to write the loop instruction support still. */
 782          if (intel->gen >= 6)
 783             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 784          else
 785             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 786          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 787          break;
 788
 789       case BRW_OPCODE_WHILE: {
 790          struct brw_instruction *inst0, *inst1;
 791          GLuint br = 1;
 792
 793          if (intel->gen >= 5)
 794             br = 2;
 795
 796          assert(loop_stack_depth > 0);
 797          loop_stack_depth--;
 798          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 799          if (intel->gen < 6) {
 800             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 801             while (inst0 > loop_stack[loop_stack_depth]) {
 802                inst0--;
 803                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 804                    inst0->bits3.if_else.jump_count == 0) {
 805                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 806             }
 807                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 808                         inst0->bits3.if_else.jump_count == 0) {
 809                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 810                }
 811             }
 812          }
 813       }
 814          break;
 815
 816       default:
 817          generate_vs_instruction(inst, dst, src);
 818          break;
 819       }
 820
 821       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 822          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 823             if (0) {
 824                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 825                       ((uint32_t *)&p->store[i])[3],
 826                       ((uint32_t *)&p->store[i])[2],
 827                       ((uint32_t *)&p->store[i])[1],
 828                       ((uint32_t *)&p->store[i])[0]);
 829             }
 830             brw_disasm(stdout, &p->store[i], intel->gen);
 831          }
 832       }
 833
 834       last_native_inst = p->nr_insn;
 835    }
 836
 837    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 838       printf("\n");
 839    }
 840
 841    ralloc_free(loop_stack);
 842    ralloc_free(if_depth_in_loop);
 843
 844    brw_set_uip_jip(p);
 845
 846    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 847     * emit issues, it doesn't get the jump distances into the output,
 848     * which is often something we want to debug.  So this is here in
 849     * case you're doing that.
 850     */
 851    if (0) {
 852       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 853          for (unsigned int i = 0; i < p->nr_insn; i++) {
 854             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 855                    ((uint32_t *)&p->store[i])[3],
 856                    ((uint32_t *)&p->store[i])[2],
 857                    ((uint32_t *)&p->store[i])[1],
 858                    ((uint32_t *)&p->store[i])[0]);
 859             brw_disasm(stdout, &p->store[i], intel->gen);
 860          }
 861       }
 862    }
 863 }
 864
 865 extern "C" {
 866
 867 bool
 868 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 869 {
 870    if (!prog)
 871       return false;
 872
 873    struct brw_shader *shader =
 874      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 875    if (!shader)
 876       return false;
 877
 878    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 879       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 880       _mesa_print_ir(shader->ir, NULL);
 881       printf("\n\n");
 882    }
 883
 884    vec4_visitor v(c, prog, shader);
 885    if (!v.run()) {
 886       prog->LinkStatus = GL_FALSE;
 887       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 888       return false;
 889    }
 890
 891    return true;
 892 }
 893
 894 } /* extern "C" */
 895
 896 } /* namespace brw */