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i965/vs: Rework binding table size calculation.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct gl_shader_program *shader_prog,
137 struct gl_program *prog,
138 struct brw_vec4_prog_data *prog_data,
139 void *mem_ctx,
140 bool debug_flag)
141 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
142 mem_ctx(mem_ctx), debug_flag(debug_flag)
143 {
144 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::mark_surface_used(unsigned surf_index)
156 {
157 assert(surf_index < BRW_MAX_VS_SURFACES);
158
159 prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
160 surf_index + 1);
161 }
162
163 void
164 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
165 struct brw_reg dst,
166 struct brw_reg src)
167 {
168 brw_math(p,
169 dst,
170 brw_math_function(inst->opcode),
171 inst->base_mrf,
172 src,
173 BRW_MATH_DATA_VECTOR,
174 BRW_MATH_PRECISION_FULL);
175 }
176
177 static void
178 check_gen6_math_src_arg(struct brw_reg src)
179 {
180 /* Source swizzles are ignored. */
181 assert(!src.abs);
182 assert(!src.negate);
183 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
184 }
185
186 void
187 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
188 struct brw_reg dst,
189 struct brw_reg src)
190 {
191 /* Can't do writemask because math can't be align16. */
192 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
193 check_gen6_math_src_arg(src);
194
195 brw_set_access_mode(p, BRW_ALIGN_1);
196 brw_math(p,
197 dst,
198 brw_math_function(inst->opcode),
199 inst->base_mrf,
200 src,
201 BRW_MATH_DATA_SCALAR,
202 BRW_MATH_PRECISION_FULL);
203 brw_set_access_mode(p, BRW_ALIGN_16);
204 }
205
206 void
207 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
208 struct brw_reg dst,
209 struct brw_reg src0,
210 struct brw_reg src1)
211 {
212 brw_math2(p,
213 dst,
214 brw_math_function(inst->opcode),
215 src0, src1);
216 }
217
218 void
219 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
220 struct brw_reg dst,
221 struct brw_reg src0,
222 struct brw_reg src1)
223 {
224 /* Can't do writemask because math can't be align16. */
225 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
226 /* Source swizzles are ignored. */
227 check_gen6_math_src_arg(src0);
228 check_gen6_math_src_arg(src1);
229
230 brw_set_access_mode(p, BRW_ALIGN_1);
231 brw_math2(p,
232 dst,
233 brw_math_function(inst->opcode),
234 src0, src1);
235 brw_set_access_mode(p, BRW_ALIGN_16);
236 }
237
238 void
239 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
240 struct brw_reg dst,
241 struct brw_reg src0,
242 struct brw_reg src1)
243 {
244 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
245 * "Message Payload":
246 *
247 * "Operand0[7]. For the INT DIV functions, this operand is the
248 * denominator."
249 * ...
250 * "Operand1[7]. For the INT DIV functions, this operand is the
251 * numerator."
252 */
253 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
254 struct brw_reg &op0 = is_int_div ? src1 : src0;
255 struct brw_reg &op1 = is_int_div ? src0 : src1;
256
257 brw_push_insn_state(p);
258 brw_set_saturate(p, false);
259 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
260 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
261 brw_pop_insn_state(p);
262
263 brw_math(p,
264 dst,
265 brw_math_function(inst->opcode),
266 inst->base_mrf,
267 op0,
268 BRW_MATH_DATA_VECTOR,
269 BRW_MATH_PRECISION_FULL);
270 }
271
272 void
273 vec4_generator::generate_tex(vec4_instruction *inst,
274 struct brw_reg dst,
275 struct brw_reg src)
276 {
277 int msg_type = -1;
278
279 if (brw->gen >= 5) {
280 switch (inst->opcode) {
281 case SHADER_OPCODE_TEX:
282 case SHADER_OPCODE_TXL:
283 if (inst->shadow_compare) {
284 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
285 } else {
286 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
287 }
288 break;
289 case SHADER_OPCODE_TXD:
290 if (inst->shadow_compare) {
291 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
292 assert(brw->is_haswell);
293 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
294 } else {
295 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
296 }
297 break;
298 case SHADER_OPCODE_TXF:
299 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
300 break;
301 case SHADER_OPCODE_TXF_MS:
302 if (brw->gen >= 7)
303 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
304 else
305 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
306 break;
307 case SHADER_OPCODE_TXS:
308 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
309 break;
310 default:
311 assert(!"should not get here: invalid VS texture opcode");
312 break;
313 }
314 } else {
315 switch (inst->opcode) {
316 case SHADER_OPCODE_TEX:
317 case SHADER_OPCODE_TXL:
318 if (inst->shadow_compare) {
319 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
320 assert(inst->mlen == 3);
321 } else {
322 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
323 assert(inst->mlen == 2);
324 }
325 break;
326 case SHADER_OPCODE_TXD:
327 /* There is no sample_d_c message; comparisons are done manually. */
328 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
329 assert(inst->mlen == 4);
330 break;
331 case SHADER_OPCODE_TXF:
332 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
333 assert(inst->mlen == 2);
334 break;
335 case SHADER_OPCODE_TXS:
336 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
337 assert(inst->mlen == 2);
338 break;
339 default:
340 assert(!"should not get here: invalid VS texture opcode");
341 break;
342 }
343 }
344
345 assert(msg_type != -1);
346
347 /* Load the message header if present. If there's a texture offset, we need
348 * to set it up explicitly and load the offset bitfield. Otherwise, we can
349 * use an implied move from g0 to the first message register.
350 */
351 if (inst->texture_offset) {
352 /* Explicitly set up the message header by copying g0 to the MRF. */
353 brw_push_insn_state(p);
354 brw_set_mask_control(p, BRW_MASK_DISABLE);
355 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
356 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
357
358 /* Then set the offset bits in DWord 2. */
359 brw_set_access_mode(p, BRW_ALIGN_1);
360 brw_MOV(p,
361 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
362 BRW_REGISTER_TYPE_UD),
363 brw_imm_uw(inst->texture_offset));
364 brw_pop_insn_state(p);
365 } else if (inst->header_present) {
366 /* Set up an implied move from g0 to the MRF. */
367 src = brw_vec8_grf(0, 0);
368 }
369
370 uint32_t return_format;
371
372 switch (dst.type) {
373 case BRW_REGISTER_TYPE_D:
374 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
375 break;
376 case BRW_REGISTER_TYPE_UD:
377 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
378 break;
379 default:
380 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
381 break;
382 }
383
384 brw_SAMPLE(p,
385 dst,
386 inst->base_mrf,
387 src,
388 SURF_INDEX_VS_TEXTURE(inst->sampler),
389 inst->sampler,
390 msg_type,
391 1, /* response length */
392 inst->mlen,
393 inst->header_present,
394 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
395 return_format);
396
397 mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
398 }
399
400 void
401 vec4_generator::generate_urb_write(vec4_instruction *inst)
402 {
403 brw_urb_WRITE(p,
404 brw_null_reg(), /* dest */
405 inst->base_mrf, /* starting mrf reg nr */
406 brw_vec8_grf(0, 0), /* src */
407 false, /* allocate */
408 true, /* used */
409 inst->mlen,
410 0, /* response len */
411 inst->eot, /* eot */
412 inst->eot, /* writes complete */
413 inst->offset, /* urb destination offset */
414 BRW_URB_SWIZZLE_INTERLEAVE);
415 }
416
417 void
418 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
419 struct brw_reg index)
420 {
421 int second_vertex_offset;
422
423 if (brw->gen >= 6)
424 second_vertex_offset = 1;
425 else
426 second_vertex_offset = 16;
427
428 m1 = retype(m1, BRW_REGISTER_TYPE_D);
429
430 /* Set up M1 (message payload). Only the block offsets in M1.0 and
431 * M1.4 are used, and the rest are ignored.
432 */
433 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
434 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
435 struct brw_reg index_0 = suboffset(vec1(index), 0);
436 struct brw_reg index_4 = suboffset(vec1(index), 4);
437
438 brw_push_insn_state(p);
439 brw_set_mask_control(p, BRW_MASK_DISABLE);
440 brw_set_access_mode(p, BRW_ALIGN_1);
441
442 brw_MOV(p, m1_0, index_0);
443
444 if (index.file == BRW_IMMEDIATE_VALUE) {
445 index_4.dw1.ud += second_vertex_offset;
446 brw_MOV(p, m1_4, index_4);
447 } else {
448 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
449 }
450
451 brw_pop_insn_state(p);
452 }
453
454 void
455 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
456 struct brw_reg dst)
457 {
458 brw_push_insn_state(p);
459 brw_set_mask_control(p, BRW_MASK_DISABLE);
460 brw_set_access_mode(p, BRW_ALIGN_1);
461
462 struct brw_reg flags = brw_flag_reg(0, 0);
463 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
464 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
465
466 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
467 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
468 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
469
470 brw_pop_insn_state(p);
471 }
472
473 void
474 vec4_generator::generate_scratch_read(vec4_instruction *inst,
475 struct brw_reg dst,
476 struct brw_reg index)
477 {
478 struct brw_reg header = brw_vec8_grf(0, 0);
479
480 gen6_resolve_implied_move(p, &header, inst->base_mrf);
481
482 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
483 index);
484
485 uint32_t msg_type;
486
487 if (brw->gen >= 6)
488 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
489 else if (brw->gen == 5 || brw->is_g4x)
490 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
491 else
492 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
493
494 /* Each of the 8 channel enables is considered for whether each
495 * dword is written.
496 */
497 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
498 brw_set_dest(p, send, dst);
499 brw_set_src0(p, send, header);
500 if (brw->gen < 6)
501 send->header.destreg__conditionalmod = inst->base_mrf;
502 brw_set_dp_read_message(p, send,
503 255, /* binding table index: stateless access */
504 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
505 msg_type,
506 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
507 2, /* mlen */
508 true, /* header_present */
509 1 /* rlen */);
510 }
511
512 void
513 vec4_generator::generate_scratch_write(vec4_instruction *inst,
514 struct brw_reg dst,
515 struct brw_reg src,
516 struct brw_reg index)
517 {
518 struct brw_reg header = brw_vec8_grf(0, 0);
519 bool write_commit;
520
521 /* If the instruction is predicated, we'll predicate the send, not
522 * the header setup.
523 */
524 brw_set_predicate_control(p, false);
525
526 gen6_resolve_implied_move(p, &header, inst->base_mrf);
527
528 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
529 index);
530
531 brw_MOV(p,
532 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
533 retype(src, BRW_REGISTER_TYPE_D));
534
535 uint32_t msg_type;
536
537 if (brw->gen >= 7)
538 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
539 else if (brw->gen == 6)
540 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
541 else
542 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
543
544 brw_set_predicate_control(p, inst->predicate);
545
546 /* Pre-gen6, we have to specify write commits to ensure ordering
547 * between reads and writes within a thread. Afterwards, that's
548 * guaranteed and write commits only matter for inter-thread
549 * synchronization.
550 */
551 if (brw->gen >= 6) {
552 write_commit = false;
553 } else {
554 /* The visitor set up our destination register to be g0. This
555 * means that when the next read comes along, we will end up
556 * reading from g0 and causing a block on the write commit. For
557 * write-after-read, we are relying on the value of the previous
558 * read being used (and thus blocking on completion) before our
559 * write is executed. This means we have to be careful in
560 * instruction scheduling to not violate this assumption.
561 */
562 write_commit = true;
563 }
564
565 /* Each of the 8 channel enables is considered for whether each
566 * dword is written.
567 */
568 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
569 brw_set_dest(p, send, dst);
570 brw_set_src0(p, send, header);
571 if (brw->gen < 6)
572 send->header.destreg__conditionalmod = inst->base_mrf;
573 brw_set_dp_write_message(p, send,
574 255, /* binding table index: stateless access */
575 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
576 msg_type,
577 3, /* mlen */
578 true, /* header present */
579 false, /* not a render target write */
580 write_commit, /* rlen */
581 false, /* eot */
582 write_commit);
583 }
584
585 void
586 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
587 struct brw_reg dst,
588 struct brw_reg index,
589 struct brw_reg offset)
590 {
591 assert(brw->gen <= 7);
592 assert(index.file == BRW_IMMEDIATE_VALUE &&
593 index.type == BRW_REGISTER_TYPE_UD);
594 uint32_t surf_index = index.dw1.ud;
595
596 struct brw_reg header = brw_vec8_grf(0, 0);
597
598 gen6_resolve_implied_move(p, &header, inst->base_mrf);
599
600 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
601 offset);
602
603 uint32_t msg_type;
604
605 if (brw->gen >= 6)
606 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
607 else if (brw->gen == 5 || brw->is_g4x)
608 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
609 else
610 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
611
612 /* Each of the 8 channel enables is considered for whether each
613 * dword is written.
614 */
615 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
616 brw_set_dest(p, send, dst);
617 brw_set_src0(p, send, header);
618 if (brw->gen < 6)
619 send->header.destreg__conditionalmod = inst->base_mrf;
620 brw_set_dp_read_message(p, send,
621 surf_index,
622 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
623 msg_type,
624 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
625 2, /* mlen */
626 true, /* header_present */
627 1 /* rlen */);
628
629 mark_surface_used(surf_index);
630 }
631
632 void
633 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
634 struct brw_reg dst,
635 struct brw_reg surf_index,
636 struct brw_reg offset)
637 {
638 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
639 surf_index.type == BRW_REGISTER_TYPE_UD);
640
641 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
642 brw_set_dest(p, insn, dst);
643 brw_set_src0(p, insn, offset);
644 brw_set_sampler_message(p, insn,
645 surf_index.dw1.ud,
646 0, /* LD message ignores sampler unit */
647 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
648 1, /* rlen */
649 1, /* mlen */
650 false, /* no header */
651 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
652 0);
653
654 mark_surface_used(surf_index.dw1.ud);
655 }
656
657 /**
658 * Generate assembly for a Vec4 IR instruction.
659 *
660 * \param instruction The Vec4 IR instruction to generate code for.
661 * \param dst The destination register.
662 * \param src An array of up to three source registers.
663 */
664 void
665 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
666 struct brw_reg dst,
667 struct brw_reg *src)
668 {
669 vec4_instruction *inst = (vec4_instruction *) instruction;
670
671 switch (inst->opcode) {
672 case BRW_OPCODE_MOV:
673 brw_MOV(p, dst, src[0]);
674 break;
675 case BRW_OPCODE_ADD:
676 brw_ADD(p, dst, src[0], src[1]);
677 break;
678 case BRW_OPCODE_MUL:
679 brw_MUL(p, dst, src[0], src[1]);
680 break;
681 case BRW_OPCODE_MACH:
682 brw_set_acc_write_control(p, 1);
683 brw_MACH(p, dst, src[0], src[1]);
684 brw_set_acc_write_control(p, 0);
685 break;
686
687 case BRW_OPCODE_MAD:
688 brw_MAD(p, dst, src[0], src[1], src[2]);
689 break;
690
691 case BRW_OPCODE_FRC:
692 brw_FRC(p, dst, src[0]);
693 break;
694 case BRW_OPCODE_RNDD:
695 brw_RNDD(p, dst, src[0]);
696 break;
697 case BRW_OPCODE_RNDE:
698 brw_RNDE(p, dst, src[0]);
699 break;
700 case BRW_OPCODE_RNDZ:
701 brw_RNDZ(p, dst, src[0]);
702 break;
703
704 case BRW_OPCODE_AND:
705 brw_AND(p, dst, src[0], src[1]);
706 break;
707 case BRW_OPCODE_OR:
708 brw_OR(p, dst, src[0], src[1]);
709 break;
710 case BRW_OPCODE_XOR:
711 brw_XOR(p, dst, src[0], src[1]);
712 break;
713 case BRW_OPCODE_NOT:
714 brw_NOT(p, dst, src[0]);
715 break;
716 case BRW_OPCODE_ASR:
717 brw_ASR(p, dst, src[0], src[1]);
718 break;
719 case BRW_OPCODE_SHR:
720 brw_SHR(p, dst, src[0], src[1]);
721 break;
722 case BRW_OPCODE_SHL:
723 brw_SHL(p, dst, src[0], src[1]);
724 break;
725
726 case BRW_OPCODE_CMP:
727 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
728 break;
729 case BRW_OPCODE_SEL:
730 brw_SEL(p, dst, src[0], src[1]);
731 break;
732
733 case BRW_OPCODE_DPH:
734 brw_DPH(p, dst, src[0], src[1]);
735 break;
736
737 case BRW_OPCODE_DP4:
738 brw_DP4(p, dst, src[0], src[1]);
739 break;
740
741 case BRW_OPCODE_DP3:
742 brw_DP3(p, dst, src[0], src[1]);
743 break;
744
745 case BRW_OPCODE_DP2:
746 brw_DP2(p, dst, src[0], src[1]);
747 break;
748
749 case BRW_OPCODE_F32TO16:
750 brw_F32TO16(p, dst, src[0]);
751 break;
752
753 case BRW_OPCODE_F16TO32:
754 brw_F16TO32(p, dst, src[0]);
755 break;
756
757 case BRW_OPCODE_LRP:
758 brw_LRP(p, dst, src[0], src[1], src[2]);
759 break;
760
761 case BRW_OPCODE_BFREV:
762 /* BFREV only supports UD type for src and dst. */
763 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
764 retype(src[0], BRW_REGISTER_TYPE_UD));
765 break;
766 case BRW_OPCODE_FBH:
767 /* FBH only supports UD type for dst. */
768 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
769 break;
770 case BRW_OPCODE_FBL:
771 /* FBL only supports UD type for dst. */
772 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
773 break;
774 case BRW_OPCODE_CBIT:
775 /* CBIT only supports UD type for dst. */
776 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
777 break;
778
779 case BRW_OPCODE_BFE:
780 brw_BFE(p, dst, src[0], src[1], src[2]);
781 break;
782
783 case BRW_OPCODE_BFI1:
784 brw_BFI1(p, dst, src[0], src[1]);
785 break;
786 case BRW_OPCODE_BFI2:
787 brw_BFI2(p, dst, src[0], src[1], src[2]);
788 break;
789
790 case BRW_OPCODE_IF:
791 if (inst->src[0].file != BAD_FILE) {
792 /* The instruction has an embedded compare (only allowed on gen6) */
793 assert(brw->gen == 6);
794 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
795 } else {
796 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
797 brw_inst->header.predicate_control = inst->predicate;
798 }
799 break;
800
801 case BRW_OPCODE_ELSE:
802 brw_ELSE(p);
803 break;
804 case BRW_OPCODE_ENDIF:
805 brw_ENDIF(p);
806 break;
807
808 case BRW_OPCODE_DO:
809 brw_DO(p, BRW_EXECUTE_8);
810 break;
811
812 case BRW_OPCODE_BREAK:
813 brw_BREAK(p);
814 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
815 break;
816 case BRW_OPCODE_CONTINUE:
817 /* FINISHME: We need to write the loop instruction support still. */
818 if (brw->gen >= 6)
819 gen6_CONT(p);
820 else
821 brw_CONT(p);
822 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
823 break;
824
825 case BRW_OPCODE_WHILE:
826 brw_WHILE(p);
827 break;
828
829 case SHADER_OPCODE_RCP:
830 case SHADER_OPCODE_RSQ:
831 case SHADER_OPCODE_SQRT:
832 case SHADER_OPCODE_EXP2:
833 case SHADER_OPCODE_LOG2:
834 case SHADER_OPCODE_SIN:
835 case SHADER_OPCODE_COS:
836 if (brw->gen == 6) {
837 generate_math1_gen6(inst, dst, src[0]);
838 } else {
839 /* Also works for Gen7. */
840 generate_math1_gen4(inst, dst, src[0]);
841 }
842 break;
843
844 case SHADER_OPCODE_POW:
845 case SHADER_OPCODE_INT_QUOTIENT:
846 case SHADER_OPCODE_INT_REMAINDER:
847 if (brw->gen >= 7) {
848 generate_math2_gen7(inst, dst, src[0], src[1]);
849 } else if (brw->gen == 6) {
850 generate_math2_gen6(inst, dst, src[0], src[1]);
851 } else {
852 generate_math2_gen4(inst, dst, src[0], src[1]);
853 }
854 break;
855
856 case SHADER_OPCODE_TEX:
857 case SHADER_OPCODE_TXD:
858 case SHADER_OPCODE_TXF:
859 case SHADER_OPCODE_TXF_MS:
860 case SHADER_OPCODE_TXL:
861 case SHADER_OPCODE_TXS:
862 generate_tex(inst, dst, src[0]);
863 break;
864
865 case VS_OPCODE_URB_WRITE:
866 generate_urb_write(inst);
867 break;
868
869 case VS_OPCODE_SCRATCH_READ:
870 generate_scratch_read(inst, dst, src[0]);
871 break;
872
873 case VS_OPCODE_SCRATCH_WRITE:
874 generate_scratch_write(inst, dst, src[0], src[1]);
875 break;
876
877 case VS_OPCODE_PULL_CONSTANT_LOAD:
878 generate_pull_constant_load(inst, dst, src[0], src[1]);
879 break;
880
881 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
882 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
883 break;
884
885 case SHADER_OPCODE_SHADER_TIME_ADD:
886 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
887 mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
888 break;
889
890 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
891 generate_unpack_flags(inst, dst);
892 break;
893
894 default:
895 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
896 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
897 opcode_descs[inst->opcode].name);
898 } else {
899 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
900 }
901 abort();
902 }
903 }
904
905 void
906 vec4_generator::generate_code(exec_list *instructions)
907 {
908 int last_native_insn_offset = 0;
909 const char *last_annotation_string = NULL;
910 const void *last_annotation_ir = NULL;
911
912 if (unlikely(debug_flag)) {
913 if (shader) {
914 printf("Native code for vertex shader %d:\n", shader_prog->Name);
915 } else {
916 printf("Native code for vertex program %d:\n", prog->Id);
917 }
918 }
919
920 foreach_list(node, instructions) {
921 vec4_instruction *inst = (vec4_instruction *)node;
922 struct brw_reg src[3], dst;
923
924 if (unlikely(debug_flag)) {
925 if (last_annotation_ir != inst->ir) {
926 last_annotation_ir = inst->ir;
927 if (last_annotation_ir) {
928 printf(" ");
929 if (shader) {
930 ((ir_instruction *) last_annotation_ir)->print();
931 } else {
932 const prog_instruction *vpi;
933 vpi = (const prog_instruction *) inst->ir;
934 printf("%d: ", (int)(vpi - prog->Instructions));
935 _mesa_fprint_instruction_opt(stdout, vpi, 0,
936 PROG_PRINT_DEBUG, NULL);
937 }
938 printf("\n");
939 }
940 }
941 if (last_annotation_string != inst->annotation) {
942 last_annotation_string = inst->annotation;
943 if (last_annotation_string)
944 printf(" %s\n", last_annotation_string);
945 }
946 }
947
948 for (unsigned int i = 0; i < 3; i++) {
949 src[i] = inst->get_src(i);
950 }
951 dst = inst->get_dst();
952
953 brw_set_conditionalmod(p, inst->conditional_mod);
954 brw_set_predicate_control(p, inst->predicate);
955 brw_set_predicate_inverse(p, inst->predicate_inverse);
956 brw_set_saturate(p, inst->saturate);
957 brw_set_mask_control(p, inst->force_writemask_all);
958
959 unsigned pre_emit_nr_insn = p->nr_insn;
960
961 generate_vec4_instruction(inst, dst, src);
962
963 if (inst->no_dd_clear || inst->no_dd_check) {
964 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
965 !"no_dd_check or no_dd_clear set for IR emitting more "
966 "than 1 instruction");
967
968 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
969
970 if (inst->no_dd_clear)
971 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
972 if (inst->no_dd_check)
973 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
974 }
975
976 if (unlikely(debug_flag)) {
977 brw_dump_compile(p, stdout,
978 last_native_insn_offset, p->next_insn_offset);
979 }
980
981 last_native_insn_offset = p->next_insn_offset;
982 }
983
984 if (unlikely(debug_flag)) {
985 printf("\n");
986 }
987
988 brw_set_uip_jip(p);
989
990 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
991 * emit issues, it doesn't get the jump distances into the output,
992 * which is often something we want to debug. So this is here in
993 * case you're doing that.
994 */
995 if (0 && unlikely(debug_flag)) {
996 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
997 }
998 }
999
1000 const unsigned *
1001 vec4_generator::generate_assembly(exec_list *instructions,
1002 unsigned *assembly_size)
1003 {
1004 brw_set_access_mode(p, BRW_ALIGN_16);
1005 generate_code(instructions);
1006 return brw_get_program(p, assembly_size);
1007 }
1008
1009 } /* namespace brw */