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i965: Disable write masking when setting up texturing m0.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct brw_vs_compile *c,
137 struct gl_shader_program *prog,
138 void *mem_ctx)
139 : brw(brw), c(c), prog(prog), mem_ctx(mem_ctx)
140 {
141 intel = &brw->intel;
142 vp = &c->vp->program;
143
144 shader = prog ? prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
156 struct brw_reg dst,
157 struct brw_reg src)
158 {
159 brw_math(p,
160 dst,
161 brw_math_function(inst->opcode),
162 inst->base_mrf,
163 src,
164 BRW_MATH_DATA_VECTOR,
165 BRW_MATH_PRECISION_FULL);
166 }
167
168 static void
169 check_gen6_math_src_arg(struct brw_reg src)
170 {
171 /* Source swizzles are ignored. */
172 assert(!src.abs);
173 assert(!src.negate);
174 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
175 }
176
177 void
178 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
179 struct brw_reg dst,
180 struct brw_reg src)
181 {
182 /* Can't do writemask because math can't be align16. */
183 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
184 check_gen6_math_src_arg(src);
185
186 brw_set_access_mode(p, BRW_ALIGN_1);
187 brw_math(p,
188 dst,
189 brw_math_function(inst->opcode),
190 inst->base_mrf,
191 src,
192 BRW_MATH_DATA_SCALAR,
193 BRW_MATH_PRECISION_FULL);
194 brw_set_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 brw_math2(p,
204 dst,
205 brw_math_function(inst->opcode),
206 src0, src1);
207 }
208
209 void
210 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
211 struct brw_reg dst,
212 struct brw_reg src0,
213 struct brw_reg src1)
214 {
215 /* Can't do writemask because math can't be align16. */
216 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
217 /* Source swizzles are ignored. */
218 check_gen6_math_src_arg(src0);
219 check_gen6_math_src_arg(src1);
220
221 brw_set_access_mode(p, BRW_ALIGN_1);
222 brw_math2(p,
223 dst,
224 brw_math_function(inst->opcode),
225 src0, src1);
226 brw_set_access_mode(p, BRW_ALIGN_16);
227 }
228
229 void
230 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
231 struct brw_reg dst,
232 struct brw_reg src0,
233 struct brw_reg src1)
234 {
235 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
236 * "Message Payload":
237 *
238 * "Operand0[7]. For the INT DIV functions, this operand is the
239 * denominator."
240 * ...
241 * "Operand1[7]. For the INT DIV functions, this operand is the
242 * numerator."
243 */
244 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
245 struct brw_reg &op0 = is_int_div ? src1 : src0;
246 struct brw_reg &op1 = is_int_div ? src0 : src1;
247
248 brw_push_insn_state(p);
249 brw_set_saturate(p, false);
250 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
251 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
252 brw_pop_insn_state(p);
253
254 brw_math(p,
255 dst,
256 brw_math_function(inst->opcode),
257 inst->base_mrf,
258 op0,
259 BRW_MATH_DATA_VECTOR,
260 BRW_MATH_PRECISION_FULL);
261 }
262
263 void
264 vec4_generator::generate_tex(vec4_instruction *inst,
265 struct brw_reg dst,
266 struct brw_reg src)
267 {
268 int msg_type = -1;
269
270 if (intel->gen >= 5) {
271 switch (inst->opcode) {
272 case SHADER_OPCODE_TEX:
273 case SHADER_OPCODE_TXL:
274 if (inst->shadow_compare) {
275 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
276 } else {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
278 }
279 break;
280 case SHADER_OPCODE_TXD:
281 if (inst->shadow_compare) {
282 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
283 assert(intel->is_haswell);
284 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
285 } else {
286 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
287 }
288 break;
289 case SHADER_OPCODE_TXF:
290 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
291 break;
292 case SHADER_OPCODE_TXS:
293 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
294 break;
295 default:
296 assert(!"should not get here: invalid VS texture opcode");
297 break;
298 }
299 } else {
300 switch (inst->opcode) {
301 case SHADER_OPCODE_TEX:
302 case SHADER_OPCODE_TXL:
303 if (inst->shadow_compare) {
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
305 assert(inst->mlen == 3);
306 } else {
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
308 assert(inst->mlen == 2);
309 }
310 break;
311 case SHADER_OPCODE_TXD:
312 /* There is no sample_d_c message; comparisons are done manually. */
313 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
314 assert(inst->mlen == 4);
315 break;
316 case SHADER_OPCODE_TXF:
317 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
318 assert(inst->mlen == 2);
319 break;
320 case SHADER_OPCODE_TXS:
321 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
322 assert(inst->mlen == 2);
323 break;
324 default:
325 assert(!"should not get here: invalid VS texture opcode");
326 break;
327 }
328 }
329
330 assert(msg_type != -1);
331
332 /* Load the message header if present. If there's a texture offset, we need
333 * to set it up explicitly and load the offset bitfield. Otherwise, we can
334 * use an implied move from g0 to the first message register.
335 */
336 if (inst->texture_offset) {
337 /* Explicitly set up the message header by copying g0 to the MRF. */
338 brw_push_insn_state(p);
339 brw_set_mask_control(p, BRW_MASK_DISABLE);
340 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
341 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
342
343 /* Then set the offset bits in DWord 2. */
344 brw_set_access_mode(p, BRW_ALIGN_1);
345 brw_MOV(p,
346 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
347 BRW_REGISTER_TYPE_UD),
348 brw_imm_uw(inst->texture_offset));
349 brw_pop_insn_state(p);
350 } else if (inst->header_present) {
351 /* Set up an implied move from g0 to the MRF. */
352 src = brw_vec8_grf(0, 0);
353 }
354
355 uint32_t return_format;
356
357 switch (dst.type) {
358 case BRW_REGISTER_TYPE_D:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
360 break;
361 case BRW_REGISTER_TYPE_UD:
362 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
363 break;
364 default:
365 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
366 break;
367 }
368
369 brw_SAMPLE(p,
370 dst,
371 inst->base_mrf,
372 src,
373 SURF_INDEX_VS_TEXTURE(inst->sampler),
374 inst->sampler,
375 WRITEMASK_XYZW,
376 msg_type,
377 1, /* response length */
378 inst->mlen,
379 inst->header_present,
380 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
381 return_format);
382 }
383
384 void
385 vec4_generator::generate_urb_write(vec4_instruction *inst)
386 {
387 brw_urb_WRITE(p,
388 brw_null_reg(), /* dest */
389 inst->base_mrf, /* starting mrf reg nr */
390 brw_vec8_grf(0, 0), /* src */
391 false, /* allocate */
392 true, /* used */
393 inst->mlen,
394 0, /* response len */
395 inst->eot, /* eot */
396 inst->eot, /* writes complete */
397 inst->offset, /* urb destination offset */
398 BRW_URB_SWIZZLE_INTERLEAVE);
399 }
400
401 void
402 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
403 struct brw_reg index)
404 {
405 int second_vertex_offset;
406
407 if (intel->gen >= 6)
408 second_vertex_offset = 1;
409 else
410 second_vertex_offset = 16;
411
412 m1 = retype(m1, BRW_REGISTER_TYPE_D);
413
414 /* Set up M1 (message payload). Only the block offsets in M1.0 and
415 * M1.4 are used, and the rest are ignored.
416 */
417 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
418 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
419 struct brw_reg index_0 = suboffset(vec1(index), 0);
420 struct brw_reg index_4 = suboffset(vec1(index), 4);
421
422 brw_push_insn_state(p);
423 brw_set_mask_control(p, BRW_MASK_DISABLE);
424 brw_set_access_mode(p, BRW_ALIGN_1);
425
426 brw_MOV(p, m1_0, index_0);
427
428 if (index.file == BRW_IMMEDIATE_VALUE) {
429 index_4.dw1.ud += second_vertex_offset;
430 brw_MOV(p, m1_4, index_4);
431 } else {
432 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
433 }
434
435 brw_pop_insn_state(p);
436 }
437
438 void
439 vec4_generator::generate_scratch_read(vec4_instruction *inst,
440 struct brw_reg dst,
441 struct brw_reg index)
442 {
443 struct brw_reg header = brw_vec8_grf(0, 0);
444
445 gen6_resolve_implied_move(p, &header, inst->base_mrf);
446
447 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
448 index);
449
450 uint32_t msg_type;
451
452 if (intel->gen >= 6)
453 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
454 else if (intel->gen == 5 || intel->is_g4x)
455 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
456 else
457 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
458
459 /* Each of the 8 channel enables is considered for whether each
460 * dword is written.
461 */
462 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
463 brw_set_dest(p, send, dst);
464 brw_set_src0(p, send, header);
465 if (intel->gen < 6)
466 send->header.destreg__conditionalmod = inst->base_mrf;
467 brw_set_dp_read_message(p, send,
468 255, /* binding table index: stateless access */
469 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
470 msg_type,
471 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
472 2, /* mlen */
473 true, /* header_present */
474 1 /* rlen */);
475 }
476
477 void
478 vec4_generator::generate_scratch_write(vec4_instruction *inst,
479 struct brw_reg dst,
480 struct brw_reg src,
481 struct brw_reg index)
482 {
483 struct brw_reg header = brw_vec8_grf(0, 0);
484 bool write_commit;
485
486 /* If the instruction is predicated, we'll predicate the send, not
487 * the header setup.
488 */
489 brw_set_predicate_control(p, false);
490
491 gen6_resolve_implied_move(p, &header, inst->base_mrf);
492
493 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
494 index);
495
496 brw_MOV(p,
497 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
498 retype(src, BRW_REGISTER_TYPE_D));
499
500 uint32_t msg_type;
501
502 if (intel->gen >= 7)
503 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
504 else if (intel->gen == 6)
505 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
506 else
507 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
508
509 brw_set_predicate_control(p, inst->predicate);
510
511 /* Pre-gen6, we have to specify write commits to ensure ordering
512 * between reads and writes within a thread. Afterwards, that's
513 * guaranteed and write commits only matter for inter-thread
514 * synchronization.
515 */
516 if (intel->gen >= 6) {
517 write_commit = false;
518 } else {
519 /* The visitor set up our destination register to be g0. This
520 * means that when the next read comes along, we will end up
521 * reading from g0 and causing a block on the write commit. For
522 * write-after-read, we are relying on the value of the previous
523 * read being used (and thus blocking on completion) before our
524 * write is executed. This means we have to be careful in
525 * instruction scheduling to not violate this assumption.
526 */
527 write_commit = true;
528 }
529
530 /* Each of the 8 channel enables is considered for whether each
531 * dword is written.
532 */
533 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
534 brw_set_dest(p, send, dst);
535 brw_set_src0(p, send, header);
536 if (intel->gen < 6)
537 send->header.destreg__conditionalmod = inst->base_mrf;
538 brw_set_dp_write_message(p, send,
539 255, /* binding table index: stateless access */
540 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
541 msg_type,
542 3, /* mlen */
543 true, /* header present */
544 false, /* not a render target write */
545 write_commit, /* rlen */
546 false, /* eot */
547 write_commit);
548 }
549
550 void
551 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
552 struct brw_reg dst,
553 struct brw_reg index,
554 struct brw_reg offset)
555 {
556 assert(index.file == BRW_IMMEDIATE_VALUE &&
557 index.type == BRW_REGISTER_TYPE_UD);
558 uint32_t surf_index = index.dw1.ud;
559
560 if (intel->gen == 7) {
561 gen6_resolve_implied_move(p, &offset, inst->base_mrf);
562 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
563 brw_set_dest(p, insn, dst);
564 brw_set_src0(p, insn, offset);
565 brw_set_sampler_message(p, insn,
566 surf_index,
567 0, /* LD message ignores sampler unit */
568 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
569 1, /* rlen */
570 1, /* mlen */
571 false, /* no header */
572 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
573 0);
574 return;
575 }
576
577 struct brw_reg header = brw_vec8_grf(0, 0);
578
579 gen6_resolve_implied_move(p, &header, inst->base_mrf);
580
581 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
582 offset);
583
584 uint32_t msg_type;
585
586 if (intel->gen >= 6)
587 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
588 else if (intel->gen == 5 || intel->is_g4x)
589 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
590 else
591 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
592
593 /* Each of the 8 channel enables is considered for whether each
594 * dword is written.
595 */
596 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
597 brw_set_dest(p, send, dst);
598 brw_set_src0(p, send, header);
599 if (intel->gen < 6)
600 send->header.destreg__conditionalmod = inst->base_mrf;
601 brw_set_dp_read_message(p, send,
602 surf_index,
603 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
604 msg_type,
605 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
606 2, /* mlen */
607 true, /* header_present */
608 1 /* rlen */);
609 }
610
611 void
612 vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
613 struct brw_reg dst,
614 struct brw_reg *src)
615 {
616 vec4_instruction *inst = (vec4_instruction *)instruction;
617
618 switch (inst->opcode) {
619 case SHADER_OPCODE_RCP:
620 case SHADER_OPCODE_RSQ:
621 case SHADER_OPCODE_SQRT:
622 case SHADER_OPCODE_EXP2:
623 case SHADER_OPCODE_LOG2:
624 case SHADER_OPCODE_SIN:
625 case SHADER_OPCODE_COS:
626 if (intel->gen == 6) {
627 generate_math1_gen6(inst, dst, src[0]);
628 } else {
629 /* Also works for Gen7. */
630 generate_math1_gen4(inst, dst, src[0]);
631 }
632 break;
633
634 case SHADER_OPCODE_POW:
635 case SHADER_OPCODE_INT_QUOTIENT:
636 case SHADER_OPCODE_INT_REMAINDER:
637 if (intel->gen >= 7) {
638 generate_math2_gen7(inst, dst, src[0], src[1]);
639 } else if (intel->gen == 6) {
640 generate_math2_gen6(inst, dst, src[0], src[1]);
641 } else {
642 generate_math2_gen4(inst, dst, src[0], src[1]);
643 }
644 break;
645
646 case SHADER_OPCODE_TEX:
647 case SHADER_OPCODE_TXD:
648 case SHADER_OPCODE_TXF:
649 case SHADER_OPCODE_TXL:
650 case SHADER_OPCODE_TXS:
651 generate_tex(inst, dst, src[0]);
652 break;
653
654 case VS_OPCODE_URB_WRITE:
655 generate_urb_write(inst);
656 break;
657
658 case VS_OPCODE_SCRATCH_READ:
659 generate_scratch_read(inst, dst, src[0]);
660 break;
661
662 case VS_OPCODE_SCRATCH_WRITE:
663 generate_scratch_write(inst, dst, src[0], src[1]);
664 break;
665
666 case VS_OPCODE_PULL_CONSTANT_LOAD:
667 generate_pull_constant_load(inst, dst, src[0], src[1]);
668 break;
669
670 case SHADER_OPCODE_SHADER_TIME_ADD:
671 brw_shader_time_add(p, inst->base_mrf, SURF_INDEX_VS_SHADER_TIME);
672 break;
673
674 default:
675 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
676 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
677 opcode_descs[inst->opcode].name);
678 } else {
679 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
680 }
681 abort();
682 }
683 }
684
685 void
686 vec4_generator::generate_code(exec_list *instructions)
687 {
688 int last_native_insn_offset = 0;
689 const char *last_annotation_string = NULL;
690 const void *last_annotation_ir = NULL;
691
692 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
693 if (shader) {
694 printf("Native code for vertex shader %d:\n", prog->Name);
695 } else {
696 printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
697 }
698 }
699
700 foreach_list(node, instructions) {
701 vec4_instruction *inst = (vec4_instruction *)node;
702 struct brw_reg src[3], dst;
703
704 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
705 if (last_annotation_ir != inst->ir) {
706 last_annotation_ir = inst->ir;
707 if (last_annotation_ir) {
708 printf(" ");
709 if (shader) {
710 ((ir_instruction *) last_annotation_ir)->print();
711 } else {
712 const prog_instruction *vpi;
713 vpi = (const prog_instruction *) inst->ir;
714 printf("%d: ", (int)(vpi - vp->Base.Instructions));
715 _mesa_fprint_instruction_opt(stdout, vpi, 0,
716 PROG_PRINT_DEBUG, NULL);
717 }
718 printf("\n");
719 }
720 }
721 if (last_annotation_string != inst->annotation) {
722 last_annotation_string = inst->annotation;
723 if (last_annotation_string)
724 printf(" %s\n", last_annotation_string);
725 }
726 }
727
728 for (unsigned int i = 0; i < 3; i++) {
729 src[i] = inst->get_src(i);
730 }
731 dst = inst->get_dst();
732
733 brw_set_conditionalmod(p, inst->conditional_mod);
734 brw_set_predicate_control(p, inst->predicate);
735 brw_set_predicate_inverse(p, inst->predicate_inverse);
736 brw_set_saturate(p, inst->saturate);
737 brw_set_mask_control(p, inst->force_writemask_all);
738
739 switch (inst->opcode) {
740 case BRW_OPCODE_MOV:
741 brw_MOV(p, dst, src[0]);
742 break;
743 case BRW_OPCODE_ADD:
744 brw_ADD(p, dst, src[0], src[1]);
745 break;
746 case BRW_OPCODE_MUL:
747 brw_MUL(p, dst, src[0], src[1]);
748 break;
749 case BRW_OPCODE_MACH:
750 brw_set_acc_write_control(p, 1);
751 brw_MACH(p, dst, src[0], src[1]);
752 brw_set_acc_write_control(p, 0);
753 break;
754
755 case BRW_OPCODE_FRC:
756 brw_FRC(p, dst, src[0]);
757 break;
758 case BRW_OPCODE_RNDD:
759 brw_RNDD(p, dst, src[0]);
760 break;
761 case BRW_OPCODE_RNDE:
762 brw_RNDE(p, dst, src[0]);
763 break;
764 case BRW_OPCODE_RNDZ:
765 brw_RNDZ(p, dst, src[0]);
766 break;
767
768 case BRW_OPCODE_AND:
769 brw_AND(p, dst, src[0], src[1]);
770 break;
771 case BRW_OPCODE_OR:
772 brw_OR(p, dst, src[0], src[1]);
773 break;
774 case BRW_OPCODE_XOR:
775 brw_XOR(p, dst, src[0], src[1]);
776 break;
777 case BRW_OPCODE_NOT:
778 brw_NOT(p, dst, src[0]);
779 break;
780 case BRW_OPCODE_ASR:
781 brw_ASR(p, dst, src[0], src[1]);
782 break;
783 case BRW_OPCODE_SHR:
784 brw_SHR(p, dst, src[0], src[1]);
785 break;
786 case BRW_OPCODE_SHL:
787 brw_SHL(p, dst, src[0], src[1]);
788 break;
789
790 case BRW_OPCODE_CMP:
791 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
792 break;
793 case BRW_OPCODE_SEL:
794 brw_SEL(p, dst, src[0], src[1]);
795 break;
796
797 case BRW_OPCODE_DPH:
798 brw_DPH(p, dst, src[0], src[1]);
799 break;
800
801 case BRW_OPCODE_DP4:
802 brw_DP4(p, dst, src[0], src[1]);
803 break;
804
805 case BRW_OPCODE_DP3:
806 brw_DP3(p, dst, src[0], src[1]);
807 break;
808
809 case BRW_OPCODE_DP2:
810 brw_DP2(p, dst, src[0], src[1]);
811 break;
812
813 case BRW_OPCODE_F32TO16:
814 brw_F32TO16(p, dst, src[0]);
815 break;
816
817 case BRW_OPCODE_F16TO32:
818 brw_F16TO32(p, dst, src[0]);
819 break;
820
821 case BRW_OPCODE_IF:
822 if (inst->src[0].file != BAD_FILE) {
823 /* The instruction has an embedded compare (only allowed on gen6) */
824 assert(intel->gen == 6);
825 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
826 } else {
827 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
828 brw_inst->header.predicate_control = inst->predicate;
829 }
830 break;
831
832 case BRW_OPCODE_ELSE:
833 brw_ELSE(p);
834 break;
835 case BRW_OPCODE_ENDIF:
836 brw_ENDIF(p);
837 break;
838
839 case BRW_OPCODE_DO:
840 brw_DO(p, BRW_EXECUTE_8);
841 break;
842
843 case BRW_OPCODE_BREAK:
844 brw_BREAK(p);
845 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
846 break;
847 case BRW_OPCODE_CONTINUE:
848 /* FINISHME: We need to write the loop instruction support still. */
849 if (intel->gen >= 6)
850 gen6_CONT(p);
851 else
852 brw_CONT(p);
853 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
854 break;
855
856 case BRW_OPCODE_WHILE:
857 brw_WHILE(p);
858 break;
859
860 default:
861 generate_vs_instruction(inst, dst, src);
862 break;
863 }
864
865 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
866 brw_dump_compile(p, stdout,
867 last_native_insn_offset, p->next_insn_offset);
868 }
869
870 last_native_insn_offset = p->next_insn_offset;
871 }
872
873 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
874 printf("\n");
875 }
876
877 brw_set_uip_jip(p);
878
879 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
880 * emit issues, it doesn't get the jump distances into the output,
881 * which is often something we want to debug. So this is here in
882 * case you're doing that.
883 */
884 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
885 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
886 }
887 }
888
889 const unsigned *
890 vec4_generator::generate_assembly(exec_list *instructions,
891 unsigned *assembly_size)
892 {
893 brw_set_access_mode(p, BRW_ALIGN_16);
894 generate_code(instructions);
895 return brw_get_program(p, assembly_size);
896 }
897
898 } /* namespace brw */