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i965/gs: Add GS_OPCODE_URB_WRITE.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
104 (src[i].reg + src[i].reg_offset) / 2,
105 ((src[i].reg + src[i].reg_offset) % 2) * 4),
106 0, 4, 1);
107 brw_reg = retype(brw_reg, src[i].type);
108 brw_reg.dw1.bits.swizzle = src[i].swizzle;
109 if (src[i].abs)
110 brw_reg = brw_abs(brw_reg);
111 if (src[i].negate)
112 brw_reg = negate(brw_reg);
113
114 /* This should have been moved to pull constants. */
115 assert(!src[i].reladdr);
116 break;
117
118 case HW_REG:
119 brw_reg = src[i].fixed_hw_reg;
120 break;
121
122 case BAD_FILE:
123 /* Probably unused. */
124 brw_reg = brw_null_reg();
125 break;
126 case ATTR:
127 default:
128 assert(!"not reached");
129 brw_reg = brw_null_reg();
130 break;
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
146
147 p = rzalloc(mem_ctx, struct brw_compile);
148 brw_init_compile(brw, p, mem_ctx);
149 }
150
151 vec4_generator::~vec4_generator()
152 {
153 }
154
155 void
156 vec4_generator::mark_surface_used(unsigned surf_index)
157 {
158 assert(surf_index < BRW_MAX_VS_SURFACES);
159
160 prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
161 surf_index + 1);
162 }
163
164 void
165 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
166 struct brw_reg dst,
167 struct brw_reg src)
168 {
169 brw_math(p,
170 dst,
171 brw_math_function(inst->opcode),
172 inst->base_mrf,
173 src,
174 BRW_MATH_DATA_VECTOR,
175 BRW_MATH_PRECISION_FULL);
176 }
177
178 static void
179 check_gen6_math_src_arg(struct brw_reg src)
180 {
181 /* Source swizzles are ignored. */
182 assert(!src.abs);
183 assert(!src.negate);
184 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
185 }
186
187 void
188 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
189 struct brw_reg dst,
190 struct brw_reg src)
191 {
192 /* Can't do writemask because math can't be align16. */
193 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
194 check_gen6_math_src_arg(src);
195
196 brw_set_access_mode(p, BRW_ALIGN_1);
197 brw_math(p,
198 dst,
199 brw_math_function(inst->opcode),
200 inst->base_mrf,
201 src,
202 BRW_MATH_DATA_SCALAR,
203 BRW_MATH_PRECISION_FULL);
204 brw_set_access_mode(p, BRW_ALIGN_16);
205 }
206
207 void
208 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
209 struct brw_reg dst,
210 struct brw_reg src0,
211 struct brw_reg src1)
212 {
213 brw_math2(p,
214 dst,
215 brw_math_function(inst->opcode),
216 src0, src1);
217 }
218
219 void
220 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
221 struct brw_reg dst,
222 struct brw_reg src0,
223 struct brw_reg src1)
224 {
225 /* Can't do writemask because math can't be align16. */
226 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0);
229 check_gen6_math_src_arg(src1);
230
231 brw_set_access_mode(p, BRW_ALIGN_1);
232 brw_math2(p,
233 dst,
234 brw_math_function(inst->opcode),
235 src0, src1);
236 brw_set_access_mode(p, BRW_ALIGN_16);
237 }
238
239 void
240 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
241 struct brw_reg dst,
242 struct brw_reg src0,
243 struct brw_reg src1)
244 {
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
246 * "Message Payload":
247 *
248 * "Operand0[7]. For the INT DIV functions, this operand is the
249 * denominator."
250 * ...
251 * "Operand1[7]. For the INT DIV functions, this operand is the
252 * numerator."
253 */
254 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
255 struct brw_reg &op0 = is_int_div ? src1 : src0;
256 struct brw_reg &op1 = is_int_div ? src0 : src1;
257
258 brw_push_insn_state(p);
259 brw_set_saturate(p, false);
260 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
262 brw_pop_insn_state(p);
263
264 brw_math(p,
265 dst,
266 brw_math_function(inst->opcode),
267 inst->base_mrf,
268 op0,
269 BRW_MATH_DATA_VECTOR,
270 BRW_MATH_PRECISION_FULL);
271 }
272
273 void
274 vec4_generator::generate_tex(vec4_instruction *inst,
275 struct brw_reg dst,
276 struct brw_reg src)
277 {
278 int msg_type = -1;
279
280 if (brw->gen >= 5) {
281 switch (inst->opcode) {
282 case SHADER_OPCODE_TEX:
283 case SHADER_OPCODE_TXL:
284 if (inst->shadow_compare) {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
286 } else {
287 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
288 }
289 break;
290 case SHADER_OPCODE_TXD:
291 if (inst->shadow_compare) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw->is_haswell);
294 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
295 } else {
296 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
297 }
298 break;
299 case SHADER_OPCODE_TXF:
300 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
301 break;
302 case SHADER_OPCODE_TXF_MS:
303 if (brw->gen >= 7)
304 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
305 else
306 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
307 break;
308 case SHADER_OPCODE_TXS:
309 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
310 break;
311 default:
312 assert(!"should not get here: invalid VS texture opcode");
313 break;
314 }
315 } else {
316 switch (inst->opcode) {
317 case SHADER_OPCODE_TEX:
318 case SHADER_OPCODE_TXL:
319 if (inst->shadow_compare) {
320 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
321 assert(inst->mlen == 3);
322 } else {
323 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
324 assert(inst->mlen == 2);
325 }
326 break;
327 case SHADER_OPCODE_TXD:
328 /* There is no sample_d_c message; comparisons are done manually. */
329 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
330 assert(inst->mlen == 4);
331 break;
332 case SHADER_OPCODE_TXF:
333 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
334 assert(inst->mlen == 2);
335 break;
336 case SHADER_OPCODE_TXS:
337 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
338 assert(inst->mlen == 2);
339 break;
340 default:
341 assert(!"should not get here: invalid VS texture opcode");
342 break;
343 }
344 }
345
346 assert(msg_type != -1);
347
348 /* Load the message header if present. If there's a texture offset, we need
349 * to set it up explicitly and load the offset bitfield. Otherwise, we can
350 * use an implied move from g0 to the first message register.
351 */
352 if (inst->texture_offset) {
353 /* Explicitly set up the message header by copying g0 to the MRF. */
354 brw_push_insn_state(p);
355 brw_set_mask_control(p, BRW_MASK_DISABLE);
356 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
358
359 /* Then set the offset bits in DWord 2. */
360 brw_set_access_mode(p, BRW_ALIGN_1);
361 brw_MOV(p,
362 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
363 BRW_REGISTER_TYPE_UD),
364 brw_imm_uw(inst->texture_offset));
365 brw_pop_insn_state(p);
366 } else if (inst->header_present) {
367 /* Set up an implied move from g0 to the MRF. */
368 src = brw_vec8_grf(0, 0);
369 }
370
371 uint32_t return_format;
372
373 switch (dst.type) {
374 case BRW_REGISTER_TYPE_D:
375 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
376 break;
377 case BRW_REGISTER_TYPE_UD:
378 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
379 break;
380 default:
381 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
382 break;
383 }
384
385 brw_SAMPLE(p,
386 dst,
387 inst->base_mrf,
388 src,
389 SURF_INDEX_VS_TEXTURE(inst->sampler),
390 inst->sampler,
391 msg_type,
392 1, /* response length */
393 inst->mlen,
394 inst->header_present,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
396 return_format);
397
398 mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
399 }
400
401 void
402 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
403 {
404 brw_urb_WRITE(p,
405 brw_null_reg(), /* dest */
406 inst->base_mrf, /* starting mrf reg nr */
407 brw_vec8_grf(0, 0), /* src */
408 inst->urb_write_flags,
409 inst->mlen,
410 0, /* response len */
411 inst->offset, /* urb destination offset */
412 BRW_URB_SWIZZLE_INTERLEAVE);
413 }
414
415 void
416 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
417 {
418 struct brw_reg src = brw_message_reg(inst->base_mrf);
419 brw_urb_WRITE(p,
420 brw_null_reg(), /* dest */
421 inst->base_mrf, /* starting mrf reg nr */
422 src,
423 inst->urb_write_flags,
424 inst->mlen,
425 0, /* response len */
426 inst->offset, /* urb destination offset */
427 BRW_URB_SWIZZLE_INTERLEAVE);
428 }
429
430 void
431 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
432 struct brw_reg index)
433 {
434 int second_vertex_offset;
435
436 if (brw->gen >= 6)
437 second_vertex_offset = 1;
438 else
439 second_vertex_offset = 16;
440
441 m1 = retype(m1, BRW_REGISTER_TYPE_D);
442
443 /* Set up M1 (message payload). Only the block offsets in M1.0 and
444 * M1.4 are used, and the rest are ignored.
445 */
446 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
447 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
448 struct brw_reg index_0 = suboffset(vec1(index), 0);
449 struct brw_reg index_4 = suboffset(vec1(index), 4);
450
451 brw_push_insn_state(p);
452 brw_set_mask_control(p, BRW_MASK_DISABLE);
453 brw_set_access_mode(p, BRW_ALIGN_1);
454
455 brw_MOV(p, m1_0, index_0);
456
457 if (index.file == BRW_IMMEDIATE_VALUE) {
458 index_4.dw1.ud += second_vertex_offset;
459 brw_MOV(p, m1_4, index_4);
460 } else {
461 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
462 }
463
464 brw_pop_insn_state(p);
465 }
466
467 void
468 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
469 struct brw_reg dst)
470 {
471 brw_push_insn_state(p);
472 brw_set_mask_control(p, BRW_MASK_DISABLE);
473 brw_set_access_mode(p, BRW_ALIGN_1);
474
475 struct brw_reg flags = brw_flag_reg(0, 0);
476 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
477 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
478
479 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
480 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
481 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
482
483 brw_pop_insn_state(p);
484 }
485
486 void
487 vec4_generator::generate_scratch_read(vec4_instruction *inst,
488 struct brw_reg dst,
489 struct brw_reg index)
490 {
491 struct brw_reg header = brw_vec8_grf(0, 0);
492
493 gen6_resolve_implied_move(p, &header, inst->base_mrf);
494
495 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
496 index);
497
498 uint32_t msg_type;
499
500 if (brw->gen >= 6)
501 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
502 else if (brw->gen == 5 || brw->is_g4x)
503 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
504 else
505 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
506
507 /* Each of the 8 channel enables is considered for whether each
508 * dword is written.
509 */
510 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
511 brw_set_dest(p, send, dst);
512 brw_set_src0(p, send, header);
513 if (brw->gen < 6)
514 send->header.destreg__conditionalmod = inst->base_mrf;
515 brw_set_dp_read_message(p, send,
516 255, /* binding table index: stateless access */
517 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
518 msg_type,
519 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
520 2, /* mlen */
521 true, /* header_present */
522 1 /* rlen */);
523 }
524
525 void
526 vec4_generator::generate_scratch_write(vec4_instruction *inst,
527 struct brw_reg dst,
528 struct brw_reg src,
529 struct brw_reg index)
530 {
531 struct brw_reg header = brw_vec8_grf(0, 0);
532 bool write_commit;
533
534 /* If the instruction is predicated, we'll predicate the send, not
535 * the header setup.
536 */
537 brw_set_predicate_control(p, false);
538
539 gen6_resolve_implied_move(p, &header, inst->base_mrf);
540
541 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
542 index);
543
544 brw_MOV(p,
545 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
546 retype(src, BRW_REGISTER_TYPE_D));
547
548 uint32_t msg_type;
549
550 if (brw->gen >= 7)
551 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
552 else if (brw->gen == 6)
553 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
554 else
555 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
556
557 brw_set_predicate_control(p, inst->predicate);
558
559 /* Pre-gen6, we have to specify write commits to ensure ordering
560 * between reads and writes within a thread. Afterwards, that's
561 * guaranteed and write commits only matter for inter-thread
562 * synchronization.
563 */
564 if (brw->gen >= 6) {
565 write_commit = false;
566 } else {
567 /* The visitor set up our destination register to be g0. This
568 * means that when the next read comes along, we will end up
569 * reading from g0 and causing a block on the write commit. For
570 * write-after-read, we are relying on the value of the previous
571 * read being used (and thus blocking on completion) before our
572 * write is executed. This means we have to be careful in
573 * instruction scheduling to not violate this assumption.
574 */
575 write_commit = true;
576 }
577
578 /* Each of the 8 channel enables is considered for whether each
579 * dword is written.
580 */
581 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
582 brw_set_dest(p, send, dst);
583 brw_set_src0(p, send, header);
584 if (brw->gen < 6)
585 send->header.destreg__conditionalmod = inst->base_mrf;
586 brw_set_dp_write_message(p, send,
587 255, /* binding table index: stateless access */
588 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
589 msg_type,
590 3, /* mlen */
591 true, /* header present */
592 false, /* not a render target write */
593 write_commit, /* rlen */
594 false, /* eot */
595 write_commit);
596 }
597
598 void
599 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
600 struct brw_reg dst,
601 struct brw_reg index,
602 struct brw_reg offset)
603 {
604 assert(brw->gen <= 7);
605 assert(index.file == BRW_IMMEDIATE_VALUE &&
606 index.type == BRW_REGISTER_TYPE_UD);
607 uint32_t surf_index = index.dw1.ud;
608
609 struct brw_reg header = brw_vec8_grf(0, 0);
610
611 gen6_resolve_implied_move(p, &header, inst->base_mrf);
612
613 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
614 offset);
615
616 uint32_t msg_type;
617
618 if (brw->gen >= 6)
619 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
620 else if (brw->gen == 5 || brw->is_g4x)
621 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
622 else
623 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
624
625 /* Each of the 8 channel enables is considered for whether each
626 * dword is written.
627 */
628 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
629 brw_set_dest(p, send, dst);
630 brw_set_src0(p, send, header);
631 if (brw->gen < 6)
632 send->header.destreg__conditionalmod = inst->base_mrf;
633 brw_set_dp_read_message(p, send,
634 surf_index,
635 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
636 msg_type,
637 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
638 2, /* mlen */
639 true, /* header_present */
640 1 /* rlen */);
641
642 mark_surface_used(surf_index);
643 }
644
645 void
646 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
647 struct brw_reg dst,
648 struct brw_reg surf_index,
649 struct brw_reg offset)
650 {
651 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
652 surf_index.type == BRW_REGISTER_TYPE_UD);
653
654 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
655 brw_set_dest(p, insn, dst);
656 brw_set_src0(p, insn, offset);
657 brw_set_sampler_message(p, insn,
658 surf_index.dw1.ud,
659 0, /* LD message ignores sampler unit */
660 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
661 1, /* rlen */
662 1, /* mlen */
663 false, /* no header */
664 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
665 0);
666
667 mark_surface_used(surf_index.dw1.ud);
668 }
669
670 /**
671 * Generate assembly for a Vec4 IR instruction.
672 *
673 * \param instruction The Vec4 IR instruction to generate code for.
674 * \param dst The destination register.
675 * \param src An array of up to three source registers.
676 */
677 void
678 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
679 struct brw_reg dst,
680 struct brw_reg *src)
681 {
682 vec4_instruction *inst = (vec4_instruction *) instruction;
683
684 switch (inst->opcode) {
685 case BRW_OPCODE_MOV:
686 brw_MOV(p, dst, src[0]);
687 break;
688 case BRW_OPCODE_ADD:
689 brw_ADD(p, dst, src[0], src[1]);
690 break;
691 case BRW_OPCODE_MUL:
692 brw_MUL(p, dst, src[0], src[1]);
693 break;
694 case BRW_OPCODE_MACH:
695 brw_set_acc_write_control(p, 1);
696 brw_MACH(p, dst, src[0], src[1]);
697 brw_set_acc_write_control(p, 0);
698 break;
699
700 case BRW_OPCODE_MAD:
701 brw_MAD(p, dst, src[0], src[1], src[2]);
702 break;
703
704 case BRW_OPCODE_FRC:
705 brw_FRC(p, dst, src[0]);
706 break;
707 case BRW_OPCODE_RNDD:
708 brw_RNDD(p, dst, src[0]);
709 break;
710 case BRW_OPCODE_RNDE:
711 brw_RNDE(p, dst, src[0]);
712 break;
713 case BRW_OPCODE_RNDZ:
714 brw_RNDZ(p, dst, src[0]);
715 break;
716
717 case BRW_OPCODE_AND:
718 brw_AND(p, dst, src[0], src[1]);
719 break;
720 case BRW_OPCODE_OR:
721 brw_OR(p, dst, src[0], src[1]);
722 break;
723 case BRW_OPCODE_XOR:
724 brw_XOR(p, dst, src[0], src[1]);
725 break;
726 case BRW_OPCODE_NOT:
727 brw_NOT(p, dst, src[0]);
728 break;
729 case BRW_OPCODE_ASR:
730 brw_ASR(p, dst, src[0], src[1]);
731 break;
732 case BRW_OPCODE_SHR:
733 brw_SHR(p, dst, src[0], src[1]);
734 break;
735 case BRW_OPCODE_SHL:
736 brw_SHL(p, dst, src[0], src[1]);
737 break;
738
739 case BRW_OPCODE_CMP:
740 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
741 break;
742 case BRW_OPCODE_SEL:
743 brw_SEL(p, dst, src[0], src[1]);
744 break;
745
746 case BRW_OPCODE_DPH:
747 brw_DPH(p, dst, src[0], src[1]);
748 break;
749
750 case BRW_OPCODE_DP4:
751 brw_DP4(p, dst, src[0], src[1]);
752 break;
753
754 case BRW_OPCODE_DP3:
755 brw_DP3(p, dst, src[0], src[1]);
756 break;
757
758 case BRW_OPCODE_DP2:
759 brw_DP2(p, dst, src[0], src[1]);
760 break;
761
762 case BRW_OPCODE_F32TO16:
763 brw_F32TO16(p, dst, src[0]);
764 break;
765
766 case BRW_OPCODE_F16TO32:
767 brw_F16TO32(p, dst, src[0]);
768 break;
769
770 case BRW_OPCODE_LRP:
771 brw_LRP(p, dst, src[0], src[1], src[2]);
772 break;
773
774 case BRW_OPCODE_BFREV:
775 /* BFREV only supports UD type for src and dst. */
776 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
777 retype(src[0], BRW_REGISTER_TYPE_UD));
778 break;
779 case BRW_OPCODE_FBH:
780 /* FBH only supports UD type for dst. */
781 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
782 break;
783 case BRW_OPCODE_FBL:
784 /* FBL only supports UD type for dst. */
785 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
786 break;
787 case BRW_OPCODE_CBIT:
788 /* CBIT only supports UD type for dst. */
789 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
790 break;
791
792 case BRW_OPCODE_BFE:
793 brw_BFE(p, dst, src[0], src[1], src[2]);
794 break;
795
796 case BRW_OPCODE_BFI1:
797 brw_BFI1(p, dst, src[0], src[1]);
798 break;
799 case BRW_OPCODE_BFI2:
800 brw_BFI2(p, dst, src[0], src[1], src[2]);
801 break;
802
803 case BRW_OPCODE_IF:
804 if (inst->src[0].file != BAD_FILE) {
805 /* The instruction has an embedded compare (only allowed on gen6) */
806 assert(brw->gen == 6);
807 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
808 } else {
809 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
810 brw_inst->header.predicate_control = inst->predicate;
811 }
812 break;
813
814 case BRW_OPCODE_ELSE:
815 brw_ELSE(p);
816 break;
817 case BRW_OPCODE_ENDIF:
818 brw_ENDIF(p);
819 break;
820
821 case BRW_OPCODE_DO:
822 brw_DO(p, BRW_EXECUTE_8);
823 break;
824
825 case BRW_OPCODE_BREAK:
826 brw_BREAK(p);
827 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
828 break;
829 case BRW_OPCODE_CONTINUE:
830 /* FINISHME: We need to write the loop instruction support still. */
831 if (brw->gen >= 6)
832 gen6_CONT(p);
833 else
834 brw_CONT(p);
835 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
836 break;
837
838 case BRW_OPCODE_WHILE:
839 brw_WHILE(p);
840 break;
841
842 case SHADER_OPCODE_RCP:
843 case SHADER_OPCODE_RSQ:
844 case SHADER_OPCODE_SQRT:
845 case SHADER_OPCODE_EXP2:
846 case SHADER_OPCODE_LOG2:
847 case SHADER_OPCODE_SIN:
848 case SHADER_OPCODE_COS:
849 if (brw->gen == 6) {
850 generate_math1_gen6(inst, dst, src[0]);
851 } else {
852 /* Also works for Gen7. */
853 generate_math1_gen4(inst, dst, src[0]);
854 }
855 break;
856
857 case SHADER_OPCODE_POW:
858 case SHADER_OPCODE_INT_QUOTIENT:
859 case SHADER_OPCODE_INT_REMAINDER:
860 if (brw->gen >= 7) {
861 generate_math2_gen7(inst, dst, src[0], src[1]);
862 } else if (brw->gen == 6) {
863 generate_math2_gen6(inst, dst, src[0], src[1]);
864 } else {
865 generate_math2_gen4(inst, dst, src[0], src[1]);
866 }
867 break;
868
869 case SHADER_OPCODE_TEX:
870 case SHADER_OPCODE_TXD:
871 case SHADER_OPCODE_TXF:
872 case SHADER_OPCODE_TXF_MS:
873 case SHADER_OPCODE_TXL:
874 case SHADER_OPCODE_TXS:
875 generate_tex(inst, dst, src[0]);
876 break;
877
878 case VS_OPCODE_URB_WRITE:
879 generate_vs_urb_write(inst);
880 break;
881
882 case VS_OPCODE_SCRATCH_READ:
883 generate_scratch_read(inst, dst, src[0]);
884 break;
885
886 case VS_OPCODE_SCRATCH_WRITE:
887 generate_scratch_write(inst, dst, src[0], src[1]);
888 break;
889
890 case VS_OPCODE_PULL_CONSTANT_LOAD:
891 generate_pull_constant_load(inst, dst, src[0], src[1]);
892 break;
893
894 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
895 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
896 break;
897
898 case GS_OPCODE_URB_WRITE:
899 generate_gs_urb_write(inst);
900 break;
901
902 case SHADER_OPCODE_SHADER_TIME_ADD:
903 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
904 mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
905 break;
906
907 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
908 generate_unpack_flags(inst, dst);
909 break;
910
911 default:
912 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
913 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
914 opcode_descs[inst->opcode].name);
915 } else {
916 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
917 }
918 abort();
919 }
920 }
921
922 void
923 vec4_generator::generate_code(exec_list *instructions)
924 {
925 int last_native_insn_offset = 0;
926 const char *last_annotation_string = NULL;
927 const void *last_annotation_ir = NULL;
928
929 if (unlikely(debug_flag)) {
930 if (shader) {
931 printf("Native code for vertex shader %d:\n", shader_prog->Name);
932 } else {
933 printf("Native code for vertex program %d:\n", prog->Id);
934 }
935 }
936
937 foreach_list(node, instructions) {
938 vec4_instruction *inst = (vec4_instruction *)node;
939 struct brw_reg src[3], dst;
940
941 if (unlikely(debug_flag)) {
942 if (last_annotation_ir != inst->ir) {
943 last_annotation_ir = inst->ir;
944 if (last_annotation_ir) {
945 printf(" ");
946 if (shader) {
947 ((ir_instruction *) last_annotation_ir)->print();
948 } else {
949 const prog_instruction *vpi;
950 vpi = (const prog_instruction *) inst->ir;
951 printf("%d: ", (int)(vpi - prog->Instructions));
952 _mesa_fprint_instruction_opt(stdout, vpi, 0,
953 PROG_PRINT_DEBUG, NULL);
954 }
955 printf("\n");
956 }
957 }
958 if (last_annotation_string != inst->annotation) {
959 last_annotation_string = inst->annotation;
960 if (last_annotation_string)
961 printf(" %s\n", last_annotation_string);
962 }
963 }
964
965 for (unsigned int i = 0; i < 3; i++) {
966 src[i] = inst->get_src(this->prog_data, i);
967 }
968 dst = inst->get_dst();
969
970 brw_set_conditionalmod(p, inst->conditional_mod);
971 brw_set_predicate_control(p, inst->predicate);
972 brw_set_predicate_inverse(p, inst->predicate_inverse);
973 brw_set_saturate(p, inst->saturate);
974 brw_set_mask_control(p, inst->force_writemask_all);
975
976 unsigned pre_emit_nr_insn = p->nr_insn;
977
978 generate_vec4_instruction(inst, dst, src);
979
980 if (inst->no_dd_clear || inst->no_dd_check) {
981 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
982 !"no_dd_check or no_dd_clear set for IR emitting more "
983 "than 1 instruction");
984
985 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
986
987 if (inst->no_dd_clear)
988 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
989 if (inst->no_dd_check)
990 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
991 }
992
993 if (unlikely(debug_flag)) {
994 brw_dump_compile(p, stdout,
995 last_native_insn_offset, p->next_insn_offset);
996 }
997
998 last_native_insn_offset = p->next_insn_offset;
999 }
1000
1001 if (unlikely(debug_flag)) {
1002 printf("\n");
1003 }
1004
1005 brw_set_uip_jip(p);
1006
1007 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1008 * emit issues, it doesn't get the jump distances into the output,
1009 * which is often something we want to debug. So this is here in
1010 * case you're doing that.
1011 */
1012 if (0 && unlikely(debug_flag)) {
1013 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1014 }
1015 }
1016
1017 const unsigned *
1018 vec4_generator::generate_assembly(exec_list *instructions,
1019 unsigned *assembly_size)
1020 {
1021 brw_set_access_mode(p, BRW_ALIGN_16);
1022 generate_code(instructions);
1023 return brw_get_program(p, assembly_size);
1024 }
1025
1026 } /* namespace brw */