src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 #include "main/macros.h"
  29 };
  30
  31 using namespace brw;
  32
  33 namespace brw {
  34
  35 int
  36 vec4_visitor::setup_attributes(int payload_reg)
  37 {
  38    int nr_attributes;
  39    int attribute_map[VERT_ATTRIB_MAX + 1];
  40
  41    nr_attributes = 0;
  42    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  43       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  44          attribute_map[i] = payload_reg + nr_attributes;
  45          nr_attributes++;
  46       }
  47    }
  48
  49    /* VertexID is stored by the VF as the last vertex element, but we
  50     * don't represent it with a flag in inputs_read, so we call it
  51     * VERT_ATTRIB_MAX.
  52     */
  53    if (prog_data->uses_vertexid) {
  54       attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
  55       nr_attributes++;
  56    }
  57
  58    foreach_list(node, &this->instructions) {
  59       vec4_instruction *inst = (vec4_instruction *)node;
  60
  61       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  62       if (inst->dst.file == ATTR) {
  63          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  64
  65          struct brw_reg reg = brw_vec8_grf(grf, 0);
  66          reg.dw1.bits.writemask = inst->dst.writemask;
  67
  68          inst->dst.file = HW_REG;
  69          inst->dst.fixed_hw_reg = reg;
  70       }
  71
  72       for (int i = 0; i < 3; i++) {
  73          if (inst->src[i].file != ATTR)
  74             continue;
  75
  76          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  77
  78          struct brw_reg reg = brw_vec8_grf(grf, 0);
  79          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  80          reg.type = inst->src[i].type;
  81          if (inst->src[i].abs)
  82             reg = brw_abs(reg);
  83          if (inst->src[i].negate)
  84             reg = negate(reg);
  85
  86          inst->src[i].file = HW_REG;
  87          inst->src[i].fixed_hw_reg = reg;
  88       }
  89    }
  90
  91    /* The BSpec says we always have to read at least one thing from
  92     * the VF, and it appears that the hardware wedges otherwise.
  93     */
  94    if (nr_attributes == 0)
  95       nr_attributes = 1;
  96
  97    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  98
  99    unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
 100
 101    if (intel->gen == 6)
 102       c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
 103    else
 104       c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
 105
 106    return payload_reg + nr_attributes;
 107 }
 108
 109 int
 110 vec4_visitor::setup_uniforms(int reg)
 111 {
 112    /* The pre-gen6 VS requires that some push constants get loaded no
 113     * matter what, or the GPU would hang.
 114     */
 115    if (intel->gen < 6 && this->uniforms == 0) {
 116       this->uniform_vector_size[this->uniforms] = 1;
 117
 118       for (unsigned int i = 0; i < 4; i++) {
 119          unsigned int slot = this->uniforms * 4 + i;
 120          static float zero = 0.0;
 121          c->prog_data.param[slot] = &zero;
 122       }
 123
 124       this->uniforms++;
 125       reg++;
 126    } else {
 127       reg += ALIGN(uniforms, 2) / 2;
 128    }
 129
 130    c->prog_data.nr_params = this->uniforms * 4;
 131
 132    c->prog_data.curb_read_length = reg - 1;
 133    c->prog_data.uses_new_param_layout = true;
 134
 135    return reg;
 136 }
 137
 138 void
 139 vec4_visitor::setup_payload(void)
 140 {
 141    int reg = 0;
 142
 143    /* The payload always contains important data in g0, which contains
 144     * the URB handles that are passed on to the URB write at the end
 145     * of the thread.  So, we always start push constants at g1.
 146     */
 147    reg++;
 148
 149    reg = setup_uniforms(reg);
 150
 151    reg = setup_attributes(reg);
 152
 153    this->first_non_payload_grf = reg;
 154 }
 155
 156 struct brw_reg
 157 vec4_instruction::get_dst(void)
 158 {
 159    struct brw_reg brw_reg;
 160
 161    switch (dst.file) {
 162    case GRF:
 163       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 164       brw_reg = retype(brw_reg, dst.type);
 165       brw_reg.dw1.bits.writemask = dst.writemask;
 166       break;
 167
 168    case MRF:
 169       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 170       brw_reg = retype(brw_reg, dst.type);
 171       brw_reg.dw1.bits.writemask = dst.writemask;
 172       break;
 173
 174    case HW_REG:
 175       brw_reg = dst.fixed_hw_reg;
 176       break;
 177
 178    case BAD_FILE:
 179       brw_reg = brw_null_reg();
 180       break;
 181
 182    default:
 183       assert(!"not reached");
 184       brw_reg = brw_null_reg();
 185       break;
 186    }
 187    return brw_reg;
 188 }
 189
 190 struct brw_reg
 191 vec4_instruction::get_src(int i)
 192 {
 193    struct brw_reg brw_reg;
 194
 195    switch (src[i].file) {
 196    case GRF:
 197       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 198       brw_reg = retype(brw_reg, src[i].type);
 199       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 200       if (src[i].abs)
 201          brw_reg = brw_abs(brw_reg);
 202       if (src[i].negate)
 203          brw_reg = negate(brw_reg);
 204       break;
 205
 206    case IMM:
 207       switch (src[i].type) {
 208       case BRW_REGISTER_TYPE_F:
 209          brw_reg = brw_imm_f(src[i].imm.f);
 210          break;
 211       case BRW_REGISTER_TYPE_D:
 212          brw_reg = brw_imm_d(src[i].imm.i);
 213          break;
 214       case BRW_REGISTER_TYPE_UD:
 215          brw_reg = brw_imm_ud(src[i].imm.u);
 216          break;
 217       default:
 218          assert(!"not reached");
 219          brw_reg = brw_null_reg();
 220          break;
 221       }
 222       break;
 223
 224    case UNIFORM:
 225       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 226                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 227                        0, 4, 1);
 228       brw_reg = retype(brw_reg, src[i].type);
 229       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 230       if (src[i].abs)
 231          brw_reg = brw_abs(brw_reg);
 232       if (src[i].negate)
 233          brw_reg = negate(brw_reg);
 234
 235       /* This should have been moved to pull constants. */
 236       assert(!src[i].reladdr);
 237       break;
 238
 239    case HW_REG:
 240       brw_reg = src[i].fixed_hw_reg;
 241       break;
 242
 243    case BAD_FILE:
 244       /* Probably unused. */
 245       brw_reg = brw_null_reg();
 246       break;
 247    case ATTR:
 248    default:
 249       assert(!"not reached");
 250       brw_reg = brw_null_reg();
 251       break;
 252    }
 253
 254    return brw_reg;
 255 }
 256
 257 void
 258 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 259                                   struct brw_reg dst,
 260                                   struct brw_reg src)
 261 {
 262    brw_math(p,
 263             dst,
 264             brw_math_function(inst->opcode),
 265             inst->base_mrf,
 266             src,
 267             BRW_MATH_DATA_VECTOR,
 268             BRW_MATH_PRECISION_FULL);
 269 }
 270
 271 static void
 272 check_gen6_math_src_arg(struct brw_reg src)
 273 {
 274    /* Source swizzles are ignored. */
 275    assert(!src.abs);
 276    assert(!src.negate);
 277    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 278 }
 279
 280 void
 281 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 282                                   struct brw_reg dst,
 283                                   struct brw_reg src)
 284 {
 285    /* Can't do writemask because math can't be align16. */
 286    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 287    check_gen6_math_src_arg(src);
 288
 289    brw_set_access_mode(p, BRW_ALIGN_1);
 290    brw_math(p,
 291             dst,
 292             brw_math_function(inst->opcode),
 293             inst->base_mrf,
 294             src,
 295             BRW_MATH_DATA_SCALAR,
 296             BRW_MATH_PRECISION_FULL);
 297    brw_set_access_mode(p, BRW_ALIGN_16);
 298 }
 299
 300 void
 301 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 302                                   struct brw_reg dst,
 303                                   struct brw_reg src0,
 304                                   struct brw_reg src1)
 305 {
 306    brw_math2(p,
 307              dst,
 308              brw_math_function(inst->opcode),
 309              src0, src1);
 310 }
 311
 312 void
 313 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 314                                   struct brw_reg dst,
 315                                   struct brw_reg src0,
 316                                   struct brw_reg src1)
 317 {
 318    /* Can't do writemask because math can't be align16. */
 319    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 320    /* Source swizzles are ignored. */
 321    check_gen6_math_src_arg(src0);
 322    check_gen6_math_src_arg(src1);
 323
 324    brw_set_access_mode(p, BRW_ALIGN_1);
 325    brw_math2(p,
 326              dst,
 327              brw_math_function(inst->opcode),
 328              src0, src1);
 329    brw_set_access_mode(p, BRW_ALIGN_16);
 330 }
 331
 332 void
 333 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 334                                   struct brw_reg dst,
 335                                   struct brw_reg src0,
 336                                   struct brw_reg src1)
 337 {
 338    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 339     * "Message Payload":
 340     *
 341     * "Operand0[7].  For the INT DIV functions, this operand is the
 342     *  denominator."
 343     *  ...
 344     * "Operand1[7].  For the INT DIV functions, this operand is the
 345     *  numerator."
 346     */
 347    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 348    struct brw_reg &op0 = is_int_div ? src1 : src0;
 349    struct brw_reg &op1 = is_int_div ? src0 : src1;
 350
 351    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 352
 353    brw_math(p,
 354             dst,
 355             brw_math_function(inst->opcode),
 356             inst->base_mrf,
 357             op0,
 358             BRW_MATH_DATA_VECTOR,
 359             BRW_MATH_PRECISION_FULL);
 360 }
 361
 362 void
 363 vec4_visitor::generate_tex(vec4_instruction *inst,
 364                            struct brw_reg dst,
 365                            struct brw_reg src)
 366 {
 367    int msg_type = -1;
 368
 369    if (intel->gen >= 5) {
 370       switch (inst->opcode) {
 371       case SHADER_OPCODE_TEX:
 372       case SHADER_OPCODE_TXL:
 373          if (inst->shadow_compare) {
 374             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
 375          } else {
 376             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
 377          }
 378          break;
 379       case SHADER_OPCODE_TXD:
 380          /* There is no sample_d_c message; comparisons are done manually. */
 381          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
 382          break;
 383       case SHADER_OPCODE_TXF:
 384          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 385          break;
 386       case SHADER_OPCODE_TXS:
 387          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 388          break;
 389       default:
 390          assert(!"should not get here: invalid VS texture opcode");
 391          break;
 392       }
 393    } else {
 394       switch (inst->opcode) {
 395       case SHADER_OPCODE_TEX:
 396       case SHADER_OPCODE_TXL:
 397          if (inst->shadow_compare) {
 398             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
 399             assert(inst->mlen == 3);
 400          } else {
 401             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
 402             assert(inst->mlen == 2);
 403          }
 404          break;
 405       case SHADER_OPCODE_TXD:
 406          /* There is no sample_d_c message; comparisons are done manually. */
 407          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
 408          assert(inst->mlen == 4);
 409          break;
 410       case SHADER_OPCODE_TXF:
 411          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
 412          assert(inst->mlen == 2);
 413          break;
 414       case SHADER_OPCODE_TXS:
 415          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
 416          assert(inst->mlen == 2);
 417          break;
 418       default:
 419          assert(!"should not get here: invalid VS texture opcode");
 420          break;
 421       }
 422    }
 423
 424    assert(msg_type != -1);
 425
 426    /* Load the message header if present.  If there's a texture offset, we need
 427     * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 428     * use an implied move from g0 to the first message register.
 429     */
 430    if (inst->texture_offset) {
 431       /* Explicitly set up the message header by copying g0 to the MRF. */
 432       brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
 433                  retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 434
 435       /* Then set the offset bits in DWord 2. */
 436       brw_set_access_mode(p, BRW_ALIGN_1);
 437       brw_MOV(p,
 438               retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
 439                      BRW_REGISTER_TYPE_UD),
 440               brw_imm_uw(inst->texture_offset));
 441       brw_set_access_mode(p, BRW_ALIGN_16);
 442    } else if (inst->header_present) {
 443       /* Set up an implied move from g0 to the MRF. */
 444       src = brw_vec8_grf(0, 0);
 445    }
 446
 447    uint32_t return_format;
 448
 449    switch (dst.type) {
 450    case BRW_REGISTER_TYPE_D:
 451       return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
 452       break;
 453    case BRW_REGISTER_TYPE_UD:
 454       return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
 455       break;
 456    default:
 457       return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
 458       break;
 459    }
 460
 461    brw_SAMPLE(p,
 462               dst,
 463               inst->base_mrf,
 464               src,
 465               SURF_INDEX_VS_TEXTURE(inst->sampler),
 466               inst->sampler,
 467               WRITEMASK_XYZW,
 468               msg_type,
 469               1, /* response length */
 470               inst->mlen,
 471               inst->header_present,
 472               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 473               return_format);
 474 }
 475
 476 void
 477 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 478 {
 479    brw_urb_WRITE(p,
 480                  brw_null_reg(), /* dest */
 481                  inst->base_mrf, /* starting mrf reg nr */
 482                  brw_vec8_grf(0, 0), /* src */
 483                  false,         /* allocate */
 484                  true,          /* used */
 485                  inst->mlen,
 486                  0,             /* response len */
 487                  inst->eot,     /* eot */
 488                  inst->eot,     /* writes complete */
 489                  inst->offset,  /* urb destination offset */
 490                  BRW_URB_SWIZZLE_INTERLEAVE);
 491 }
 492
 493 void
 494 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 495                                                 struct brw_reg index)
 496 {
 497    int second_vertex_offset;
 498
 499    if (intel->gen >= 6)
 500       second_vertex_offset = 1;
 501    else
 502       second_vertex_offset = 16;
 503
 504    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 505
 506    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 507     * M1.4 are used, and the rest are ignored.
 508     */
 509    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 510    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 511    struct brw_reg index_0 = suboffset(vec1(index), 0);
 512    struct brw_reg index_4 = suboffset(vec1(index), 4);
 513
 514    brw_push_insn_state(p);
 515    brw_set_mask_control(p, BRW_MASK_DISABLE);
 516    brw_set_access_mode(p, BRW_ALIGN_1);
 517
 518    brw_MOV(p, m1_0, index_0);
 519
 520    brw_set_predicate_inverse(p, true);
 521    if (index.file == BRW_IMMEDIATE_VALUE) {
 522       index_4.dw1.ud += second_vertex_offset;
 523       brw_MOV(p, m1_4, index_4);
 524    } else {
 525       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 526    }
 527
 528    brw_pop_insn_state(p);
 529 }
 530
 531 void
 532 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 533                                     struct brw_reg dst,
 534                                     struct brw_reg index)
 535 {
 536    struct brw_reg header = brw_vec8_grf(0, 0);
 537
 538    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 539
 540    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 541                                      index);
 542
 543    uint32_t msg_type;
 544
 545    if (intel->gen >= 6)
 546       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 547    else if (intel->gen == 5 || intel->is_g4x)
 548       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 549    else
 550       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 551
 552    /* Each of the 8 channel enables is considered for whether each
 553     * dword is written.
 554     */
 555    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 556    brw_set_dest(p, send, dst);
 557    brw_set_src0(p, send, header);
 558    if (intel->gen < 6)
 559       send->header.destreg__conditionalmod = inst->base_mrf;
 560    brw_set_dp_read_message(p, send,
 561                            255, /* binding table index: stateless access */
 562                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 563                            msg_type,
 564                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 565                            2, /* mlen */
 566                            1 /* rlen */);
 567 }
 568
 569 void
 570 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 571                                      struct brw_reg dst,
 572                                      struct brw_reg src,
 573                                      struct brw_reg index)
 574 {
 575    struct brw_reg header = brw_vec8_grf(0, 0);
 576    bool write_commit;
 577
 578    /* If the instruction is predicated, we'll predicate the send, not
 579     * the header setup.
 580     */
 581    brw_set_predicate_control(p, false);
 582
 583    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 584
 585    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 586                                      index);
 587
 588    brw_MOV(p,
 589            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 590            retype(src, BRW_REGISTER_TYPE_D));
 591
 592    uint32_t msg_type;
 593
 594    if (intel->gen >= 7)
 595       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 596    else if (intel->gen == 6)
 597       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 598    else
 599       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 600
 601    brw_set_predicate_control(p, inst->predicate);
 602
 603    /* Pre-gen6, we have to specify write commits to ensure ordering
 604     * between reads and writes within a thread.  Afterwards, that's
 605     * guaranteed and write commits only matter for inter-thread
 606     * synchronization.
 607     */
 608    if (intel->gen >= 6) {
 609       write_commit = false;
 610    } else {
 611       /* The visitor set up our destination register to be g0.  This
 612        * means that when the next read comes along, we will end up
 613        * reading from g0 and causing a block on the write commit.  For
 614        * write-after-read, we are relying on the value of the previous
 615        * read being used (and thus blocking on completion) before our
 616        * write is executed.  This means we have to be careful in
 617        * instruction scheduling to not violate this assumption.
 618        */
 619       write_commit = true;
 620    }
 621
 622    /* Each of the 8 channel enables is considered for whether each
 623     * dword is written.
 624     */
 625    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 626    brw_set_dest(p, send, dst);
 627    brw_set_src0(p, send, header);
 628    if (intel->gen < 6)
 629       send->header.destreg__conditionalmod = inst->base_mrf;
 630    brw_set_dp_write_message(p, send,
 631                             255, /* binding table index: stateless access */
 632                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 633                             msg_type,
 634                             3, /* mlen */
 635                             true, /* header present */
 636                             false, /* not a render target write */
 637                             write_commit, /* rlen */
 638                             false, /* eot */
 639                             write_commit);
 640 }
 641
 642 void
 643 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 644                                           struct brw_reg dst,
 645                                           struct brw_reg index,
 646                                           struct brw_reg offset)
 647 {
 648    assert(index.file == BRW_IMMEDIATE_VALUE &&
 649           index.type == BRW_REGISTER_TYPE_UD);
 650    uint32_t surf_index = index.dw1.ud;
 651
 652    if (intel->gen == 7) {
 653       gen6_resolve_implied_move(p, &offset, inst->base_mrf);
 654       brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
 655       brw_set_dest(p, insn, dst);
 656       brw_set_src0(p, insn, offset);
 657       brw_set_sampler_message(p, insn,
 658                               surf_index,
 659                               0, /* LD message ignores sampler unit */
 660                               GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
 661                               1, /* rlen */
 662                               1, /* mlen */
 663                               false, /* no header */
 664                               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 665                               0);
 666       return;
 667    }
 668
 669    struct brw_reg header = brw_vec8_grf(0, 0);
 670
 671    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 672
 673    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 674            offset);
 675
 676    uint32_t msg_type;
 677
 678    if (intel->gen >= 6)
 679       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 680    else if (intel->gen == 5 || intel->is_g4x)
 681       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 682    else
 683       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 684
 685    /* Each of the 8 channel enables is considered for whether each
 686     * dword is written.
 687     */
 688    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 689    brw_set_dest(p, send, dst);
 690    brw_set_src0(p, send, header);
 691    if (intel->gen < 6)
 692       send->header.destreg__conditionalmod = inst->base_mrf;
 693    brw_set_dp_read_message(p, send,
 694                            surf_index,
 695                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 696                            msg_type,
 697                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 698                            2, /* mlen */
 699                            1 /* rlen */);
 700 }
 701
 702 void
 703 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 704                                       struct brw_reg dst,
 705                                       struct brw_reg *src)
 706 {
 707    vec4_instruction *inst = (vec4_instruction *)instruction;
 708
 709    switch (inst->opcode) {
 710    case SHADER_OPCODE_RCP:
 711    case SHADER_OPCODE_RSQ:
 712    case SHADER_OPCODE_SQRT:
 713    case SHADER_OPCODE_EXP2:
 714    case SHADER_OPCODE_LOG2:
 715    case SHADER_OPCODE_SIN:
 716    case SHADER_OPCODE_COS:
 717       if (intel->gen == 6) {
 718          generate_math1_gen6(inst, dst, src[0]);
 719       } else {
 720          /* Also works for Gen7. */
 721          generate_math1_gen4(inst, dst, src[0]);
 722       }
 723       break;
 724
 725    case SHADER_OPCODE_POW:
 726    case SHADER_OPCODE_INT_QUOTIENT:
 727    case SHADER_OPCODE_INT_REMAINDER:
 728       if (intel->gen >= 7) {
 729          generate_math2_gen7(inst, dst, src[0], src[1]);
 730       } else if (intel->gen == 6) {
 731          generate_math2_gen6(inst, dst, src[0], src[1]);
 732       } else {
 733          generate_math2_gen4(inst, dst, src[0], src[1]);
 734       }
 735       break;
 736
 737    case SHADER_OPCODE_TEX:
 738    case SHADER_OPCODE_TXD:
 739    case SHADER_OPCODE_TXF:
 740    case SHADER_OPCODE_TXL:
 741    case SHADER_OPCODE_TXS:
 742       generate_tex(inst, dst, src[0]);
 743       break;
 744
 745    case VS_OPCODE_URB_WRITE:
 746       generate_urb_write(inst);
 747       break;
 748
 749    case VS_OPCODE_SCRATCH_READ:
 750       generate_scratch_read(inst, dst, src[0]);
 751       break;
 752
 753    case VS_OPCODE_SCRATCH_WRITE:
 754       generate_scratch_write(inst, dst, src[0], src[1]);
 755       break;
 756
 757    case VS_OPCODE_PULL_CONSTANT_LOAD:
 758       generate_pull_constant_load(inst, dst, src[0], src[1]);
 759       break;
 760
 761    default:
 762       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 763          fail("unsupported opcode in `%s' in VS\n",
 764               brw_opcodes[inst->opcode].name);
 765       } else {
 766          fail("Unsupported opcode %d in VS", inst->opcode);
 767       }
 768    }
 769 }
 770
 771 bool
 772 vec4_visitor::run()
 773 {
 774    if (c->key.userclip_active && !c->key.uses_clip_distance)
 775       setup_uniform_clipplane_values();
 776
 777    /* Generate VS IR for main().  (the visitor only descends into
 778     * functions called "main").
 779     */
 780    visit_instructions(shader->ir);
 781
 782    emit_urb_writes();
 783
 784    /* Before any optimization, push array accesses out to scratch
 785     * space where we need them to be.  This pass may allocate new
 786     * virtual GRFs, so we want to do it early.  It also makes sure
 787     * that we have reladdr computations available for CSE, since we'll
 788     * often do repeated subexpressions for those.
 789     */
 790    move_grf_array_access_to_scratch();
 791    move_uniform_array_access_to_pull_constants();
 792    pack_uniform_registers();
 793    move_push_constants_to_pull_constants();
 794
 795    bool progress;
 796    do {
 797       progress = false;
 798       progress = dead_code_eliminate() || progress;
 799       progress = opt_copy_propagation() || progress;
 800       progress = opt_algebraic() || progress;
 801       progress = opt_compute_to_mrf() || progress;
 802    } while (progress);
 803
 804
 805    if (failed)
 806       return false;
 807
 808    setup_payload();
 809    reg_allocate();
 810
 811    if (failed)
 812       return false;
 813
 814    brw_set_access_mode(p, BRW_ALIGN_16);
 815
 816    generate_code();
 817
 818    return !failed;
 819 }
 820
 821 void
 822 vec4_visitor::generate_code()
 823 {
 824    int last_native_inst = 0;
 825    const char *last_annotation_string = NULL;
 826    ir_instruction *last_annotation_ir = NULL;
 827
 828    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 829       printf("Native code for vertex shader %d:\n", prog->Name);
 830    }
 831
 832    foreach_list(node, &this->instructions) {
 833       vec4_instruction *inst = (vec4_instruction *)node;
 834       struct brw_reg src[3], dst;
 835
 836       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 837          if (last_annotation_ir != inst->ir) {
 838             last_annotation_ir = inst->ir;
 839             if (last_annotation_ir) {
 840                printf("   ");
 841                last_annotation_ir->print();
 842                printf("\n");
 843             }
 844          }
 845          if (last_annotation_string != inst->annotation) {
 846             last_annotation_string = inst->annotation;
 847             if (last_annotation_string)
 848                printf("   %s\n", last_annotation_string);
 849          }
 850       }
 851
 852       for (unsigned int i = 0; i < 3; i++) {
 853          src[i] = inst->get_src(i);
 854       }
 855       dst = inst->get_dst();
 856
 857       brw_set_conditionalmod(p, inst->conditional_mod);
 858       brw_set_predicate_control(p, inst->predicate);
 859       brw_set_predicate_inverse(p, inst->predicate_inverse);
 860       brw_set_saturate(p, inst->saturate);
 861
 862       switch (inst->opcode) {
 863       case BRW_OPCODE_MOV:
 864          brw_MOV(p, dst, src[0]);
 865          break;
 866       case BRW_OPCODE_ADD:
 867          brw_ADD(p, dst, src[0], src[1]);
 868          break;
 869       case BRW_OPCODE_MUL:
 870          brw_MUL(p, dst, src[0], src[1]);
 871          break;
 872       case BRW_OPCODE_MACH:
 873          brw_set_acc_write_control(p, 1);
 874          brw_MACH(p, dst, src[0], src[1]);
 875          brw_set_acc_write_control(p, 0);
 876          break;
 877
 878       case BRW_OPCODE_FRC:
 879          brw_FRC(p, dst, src[0]);
 880          break;
 881       case BRW_OPCODE_RNDD:
 882          brw_RNDD(p, dst, src[0]);
 883          break;
 884       case BRW_OPCODE_RNDE:
 885          brw_RNDE(p, dst, src[0]);
 886          break;
 887       case BRW_OPCODE_RNDZ:
 888          brw_RNDZ(p, dst, src[0]);
 889          break;
 890
 891       case BRW_OPCODE_AND:
 892          brw_AND(p, dst, src[0], src[1]);
 893          break;
 894       case BRW_OPCODE_OR:
 895          brw_OR(p, dst, src[0], src[1]);
 896          break;
 897       case BRW_OPCODE_XOR:
 898          brw_XOR(p, dst, src[0], src[1]);
 899          break;
 900       case BRW_OPCODE_NOT:
 901          brw_NOT(p, dst, src[0]);
 902          break;
 903       case BRW_OPCODE_ASR:
 904          brw_ASR(p, dst, src[0], src[1]);
 905          break;
 906       case BRW_OPCODE_SHR:
 907          brw_SHR(p, dst, src[0], src[1]);
 908          break;
 909       case BRW_OPCODE_SHL:
 910          brw_SHL(p, dst, src[0], src[1]);
 911          break;
 912
 913       case BRW_OPCODE_CMP:
 914          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 915          break;
 916       case BRW_OPCODE_SEL:
 917          brw_SEL(p, dst, src[0], src[1]);
 918          break;
 919
 920       case BRW_OPCODE_DP4:
 921          brw_DP4(p, dst, src[0], src[1]);
 922          break;
 923
 924       case BRW_OPCODE_DP3:
 925          brw_DP3(p, dst, src[0], src[1]);
 926          break;
 927
 928       case BRW_OPCODE_DP2:
 929          brw_DP2(p, dst, src[0], src[1]);
 930          break;
 931
 932       case BRW_OPCODE_IF:
 933          if (inst->src[0].file != BAD_FILE) {
 934             /* The instruction has an embedded compare (only allowed on gen6) */
 935             assert(intel->gen == 6);
 936             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 937          } else {
 938             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 939             brw_inst->header.predicate_control = inst->predicate;
 940          }
 941          break;
 942
 943       case BRW_OPCODE_ELSE:
 944          brw_ELSE(p);
 945          break;
 946       case BRW_OPCODE_ENDIF:
 947          brw_ENDIF(p);
 948          break;
 949
 950       case BRW_OPCODE_DO:
 951          brw_DO(p, BRW_EXECUTE_8);
 952          break;
 953
 954       case BRW_OPCODE_BREAK:
 955          brw_BREAK(p);
 956          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 957          break;
 958       case BRW_OPCODE_CONTINUE:
 959          /* FINISHME: We need to write the loop instruction support still. */
 960          if (intel->gen >= 6)
 961             gen6_CONT(p);
 962          else
 963             brw_CONT(p);
 964          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 965          break;
 966
 967       case BRW_OPCODE_WHILE:
 968          brw_WHILE(p);
 969          break;
 970
 971       default:
 972          generate_vs_instruction(inst, dst, src);
 973          break;
 974       }
 975
 976       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 977          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 978             if (0) {
 979                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 980                       ((uint32_t *)&p->store[i])[3],
 981                       ((uint32_t *)&p->store[i])[2],
 982                       ((uint32_t *)&p->store[i])[1],
 983                       ((uint32_t *)&p->store[i])[0]);
 984             }
 985             brw_disasm(stdout, &p->store[i], intel->gen);
 986          }
 987       }
 988
 989       last_native_inst = p->nr_insn;
 990    }
 991
 992    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 993       printf("\n");
 994    }
 995
 996    brw_set_uip_jip(p);
 997
 998    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 999     * emit issues, it doesn't get the jump distances into the output,
1000     * which is often something we want to debug.  So this is here in
1001     * case you're doing that.
1002     */
1003    if (0) {
1004       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1005          for (unsigned int i = 0; i < p->nr_insn; i++) {
1006             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
1007                    ((uint32_t *)&p->store[i])[3],
1008                    ((uint32_t *)&p->store[i])[2],
1009                    ((uint32_t *)&p->store[i])[1],
1010                    ((uint32_t *)&p->store[i])[0]);
1011             brw_disasm(stdout, &p->store[i], intel->gen);
1012          }
1013       }
1014    }
1015 }
1016
1017 extern "C" {
1018
1019 bool
1020 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
1021 {
1022    if (!prog)
1023       return false;
1024
1025    struct brw_shader *shader =
1026      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1027    if (!shader)
1028       return false;
1029
1030    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1031       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1032       _mesa_print_ir(shader->ir, NULL);
1033       printf("\n\n");
1034    }
1035
1036    vec4_visitor v(c, prog, shader);
1037    if (!v.run()) {
1038       prog->LinkStatus = false;
1039       ralloc_strcat(&prog->InfoLog, v.fail_msg);
1040       return false;
1041    }
1042
1043    return true;
1044 }
1045
1046 } /* extern "C" */
1047
1048 } /* namespace brw */