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i965/vs: Generalize data structures pointed to by vec4_generator.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct gl_shader_program *shader_prog,
137 struct gl_program *prog,
138 void *mem_ctx)
139 : brw(brw), shader_prog(shader_prog), prog(prog), mem_ctx(mem_ctx)
140 {
141 intel = &brw->intel;
142
143 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
144
145 p = rzalloc(mem_ctx, struct brw_compile);
146 brw_init_compile(brw, p, mem_ctx);
147 }
148
149 vec4_generator::~vec4_generator()
150 {
151 }
152
153 void
154 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
155 struct brw_reg dst,
156 struct brw_reg src)
157 {
158 brw_math(p,
159 dst,
160 brw_math_function(inst->opcode),
161 inst->base_mrf,
162 src,
163 BRW_MATH_DATA_VECTOR,
164 BRW_MATH_PRECISION_FULL);
165 }
166
167 static void
168 check_gen6_math_src_arg(struct brw_reg src)
169 {
170 /* Source swizzles are ignored. */
171 assert(!src.abs);
172 assert(!src.negate);
173 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
174 }
175
176 void
177 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
178 struct brw_reg dst,
179 struct brw_reg src)
180 {
181 /* Can't do writemask because math can't be align16. */
182 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
183 check_gen6_math_src_arg(src);
184
185 brw_set_access_mode(p, BRW_ALIGN_1);
186 brw_math(p,
187 dst,
188 brw_math_function(inst->opcode),
189 inst->base_mrf,
190 src,
191 BRW_MATH_DATA_SCALAR,
192 BRW_MATH_PRECISION_FULL);
193 brw_set_access_mode(p, BRW_ALIGN_16);
194 }
195
196 void
197 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
198 struct brw_reg dst,
199 struct brw_reg src0,
200 struct brw_reg src1)
201 {
202 brw_math2(p,
203 dst,
204 brw_math_function(inst->opcode),
205 src0, src1);
206 }
207
208 void
209 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
210 struct brw_reg dst,
211 struct brw_reg src0,
212 struct brw_reg src1)
213 {
214 /* Can't do writemask because math can't be align16. */
215 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
216 /* Source swizzles are ignored. */
217 check_gen6_math_src_arg(src0);
218 check_gen6_math_src_arg(src1);
219
220 brw_set_access_mode(p, BRW_ALIGN_1);
221 brw_math2(p,
222 dst,
223 brw_math_function(inst->opcode),
224 src0, src1);
225 brw_set_access_mode(p, BRW_ALIGN_16);
226 }
227
228 void
229 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
230 struct brw_reg dst,
231 struct brw_reg src0,
232 struct brw_reg src1)
233 {
234 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
235 * "Message Payload":
236 *
237 * "Operand0[7]. For the INT DIV functions, this operand is the
238 * denominator."
239 * ...
240 * "Operand1[7]. For the INT DIV functions, this operand is the
241 * numerator."
242 */
243 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
244 struct brw_reg &op0 = is_int_div ? src1 : src0;
245 struct brw_reg &op1 = is_int_div ? src0 : src1;
246
247 brw_push_insn_state(p);
248 brw_set_saturate(p, false);
249 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
250 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
251 brw_pop_insn_state(p);
252
253 brw_math(p,
254 dst,
255 brw_math_function(inst->opcode),
256 inst->base_mrf,
257 op0,
258 BRW_MATH_DATA_VECTOR,
259 BRW_MATH_PRECISION_FULL);
260 }
261
262 void
263 vec4_generator::generate_tex(vec4_instruction *inst,
264 struct brw_reg dst,
265 struct brw_reg src)
266 {
267 int msg_type = -1;
268
269 if (intel->gen >= 5) {
270 switch (inst->opcode) {
271 case SHADER_OPCODE_TEX:
272 case SHADER_OPCODE_TXL:
273 if (inst->shadow_compare) {
274 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
275 } else {
276 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
277 }
278 break;
279 case SHADER_OPCODE_TXD:
280 if (inst->shadow_compare) {
281 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
282 assert(intel->is_haswell);
283 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
284 } else {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
286 }
287 break;
288 case SHADER_OPCODE_TXF:
289 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
290 break;
291 case SHADER_OPCODE_TXF_MS:
292 if (intel->gen >= 7)
293 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
294 else
295 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
296 break;
297 case SHADER_OPCODE_TXS:
298 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
299 break;
300 default:
301 assert(!"should not get here: invalid VS texture opcode");
302 break;
303 }
304 } else {
305 switch (inst->opcode) {
306 case SHADER_OPCODE_TEX:
307 case SHADER_OPCODE_TXL:
308 if (inst->shadow_compare) {
309 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
310 assert(inst->mlen == 3);
311 } else {
312 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
313 assert(inst->mlen == 2);
314 }
315 break;
316 case SHADER_OPCODE_TXD:
317 /* There is no sample_d_c message; comparisons are done manually. */
318 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
319 assert(inst->mlen == 4);
320 break;
321 case SHADER_OPCODE_TXF:
322 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
323 assert(inst->mlen == 2);
324 break;
325 case SHADER_OPCODE_TXS:
326 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
327 assert(inst->mlen == 2);
328 break;
329 default:
330 assert(!"should not get here: invalid VS texture opcode");
331 break;
332 }
333 }
334
335 assert(msg_type != -1);
336
337 /* Load the message header if present. If there's a texture offset, we need
338 * to set it up explicitly and load the offset bitfield. Otherwise, we can
339 * use an implied move from g0 to the first message register.
340 */
341 if (inst->texture_offset) {
342 /* Explicitly set up the message header by copying g0 to the MRF. */
343 brw_push_insn_state(p);
344 brw_set_mask_control(p, BRW_MASK_DISABLE);
345 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
346 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
347
348 /* Then set the offset bits in DWord 2. */
349 brw_set_access_mode(p, BRW_ALIGN_1);
350 brw_MOV(p,
351 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
352 BRW_REGISTER_TYPE_UD),
353 brw_imm_uw(inst->texture_offset));
354 brw_pop_insn_state(p);
355 } else if (inst->header_present) {
356 /* Set up an implied move from g0 to the MRF. */
357 src = brw_vec8_grf(0, 0);
358 }
359
360 uint32_t return_format;
361
362 switch (dst.type) {
363 case BRW_REGISTER_TYPE_D:
364 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
365 break;
366 case BRW_REGISTER_TYPE_UD:
367 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
368 break;
369 default:
370 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
371 break;
372 }
373
374 brw_SAMPLE(p,
375 dst,
376 inst->base_mrf,
377 src,
378 SURF_INDEX_VS_TEXTURE(inst->sampler),
379 inst->sampler,
380 msg_type,
381 1, /* response length */
382 inst->mlen,
383 inst->header_present,
384 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
385 return_format);
386 }
387
388 void
389 vec4_generator::generate_urb_write(vec4_instruction *inst)
390 {
391 brw_urb_WRITE(p,
392 brw_null_reg(), /* dest */
393 inst->base_mrf, /* starting mrf reg nr */
394 brw_vec8_grf(0, 0), /* src */
395 false, /* allocate */
396 true, /* used */
397 inst->mlen,
398 0, /* response len */
399 inst->eot, /* eot */
400 inst->eot, /* writes complete */
401 inst->offset, /* urb destination offset */
402 BRW_URB_SWIZZLE_INTERLEAVE);
403 }
404
405 void
406 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
407 struct brw_reg index)
408 {
409 int second_vertex_offset;
410
411 if (intel->gen >= 6)
412 second_vertex_offset = 1;
413 else
414 second_vertex_offset = 16;
415
416 m1 = retype(m1, BRW_REGISTER_TYPE_D);
417
418 /* Set up M1 (message payload). Only the block offsets in M1.0 and
419 * M1.4 are used, and the rest are ignored.
420 */
421 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
422 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
423 struct brw_reg index_0 = suboffset(vec1(index), 0);
424 struct brw_reg index_4 = suboffset(vec1(index), 4);
425
426 brw_push_insn_state(p);
427 brw_set_mask_control(p, BRW_MASK_DISABLE);
428 brw_set_access_mode(p, BRW_ALIGN_1);
429
430 brw_MOV(p, m1_0, index_0);
431
432 if (index.file == BRW_IMMEDIATE_VALUE) {
433 index_4.dw1.ud += second_vertex_offset;
434 brw_MOV(p, m1_4, index_4);
435 } else {
436 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
437 }
438
439 brw_pop_insn_state(p);
440 }
441
442 void
443 vec4_generator::generate_scratch_read(vec4_instruction *inst,
444 struct brw_reg dst,
445 struct brw_reg index)
446 {
447 struct brw_reg header = brw_vec8_grf(0, 0);
448
449 gen6_resolve_implied_move(p, &header, inst->base_mrf);
450
451 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
452 index);
453
454 uint32_t msg_type;
455
456 if (intel->gen >= 6)
457 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
458 else if (intel->gen == 5 || intel->is_g4x)
459 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
460 else
461 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
462
463 /* Each of the 8 channel enables is considered for whether each
464 * dword is written.
465 */
466 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
467 brw_set_dest(p, send, dst);
468 brw_set_src0(p, send, header);
469 if (intel->gen < 6)
470 send->header.destreg__conditionalmod = inst->base_mrf;
471 brw_set_dp_read_message(p, send,
472 255, /* binding table index: stateless access */
473 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
474 msg_type,
475 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
476 2, /* mlen */
477 true, /* header_present */
478 1 /* rlen */);
479 }
480
481 void
482 vec4_generator::generate_scratch_write(vec4_instruction *inst,
483 struct brw_reg dst,
484 struct brw_reg src,
485 struct brw_reg index)
486 {
487 struct brw_reg header = brw_vec8_grf(0, 0);
488 bool write_commit;
489
490 /* If the instruction is predicated, we'll predicate the send, not
491 * the header setup.
492 */
493 brw_set_predicate_control(p, false);
494
495 gen6_resolve_implied_move(p, &header, inst->base_mrf);
496
497 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
498 index);
499
500 brw_MOV(p,
501 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
502 retype(src, BRW_REGISTER_TYPE_D));
503
504 uint32_t msg_type;
505
506 if (intel->gen >= 7)
507 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
508 else if (intel->gen == 6)
509 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
510 else
511 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
512
513 brw_set_predicate_control(p, inst->predicate);
514
515 /* Pre-gen6, we have to specify write commits to ensure ordering
516 * between reads and writes within a thread. Afterwards, that's
517 * guaranteed and write commits only matter for inter-thread
518 * synchronization.
519 */
520 if (intel->gen >= 6) {
521 write_commit = false;
522 } else {
523 /* The visitor set up our destination register to be g0. This
524 * means that when the next read comes along, we will end up
525 * reading from g0 and causing a block on the write commit. For
526 * write-after-read, we are relying on the value of the previous
527 * read being used (and thus blocking on completion) before our
528 * write is executed. This means we have to be careful in
529 * instruction scheduling to not violate this assumption.
530 */
531 write_commit = true;
532 }
533
534 /* Each of the 8 channel enables is considered for whether each
535 * dword is written.
536 */
537 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
538 brw_set_dest(p, send, dst);
539 brw_set_src0(p, send, header);
540 if (intel->gen < 6)
541 send->header.destreg__conditionalmod = inst->base_mrf;
542 brw_set_dp_write_message(p, send,
543 255, /* binding table index: stateless access */
544 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
545 msg_type,
546 3, /* mlen */
547 true, /* header present */
548 false, /* not a render target write */
549 write_commit, /* rlen */
550 false, /* eot */
551 write_commit);
552 }
553
554 void
555 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
556 struct brw_reg dst,
557 struct brw_reg index,
558 struct brw_reg offset)
559 {
560 assert(intel->gen <= 7);
561 assert(index.file == BRW_IMMEDIATE_VALUE &&
562 index.type == BRW_REGISTER_TYPE_UD);
563 uint32_t surf_index = index.dw1.ud;
564
565 struct brw_reg header = brw_vec8_grf(0, 0);
566
567 gen6_resolve_implied_move(p, &header, inst->base_mrf);
568
569 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
570 offset);
571
572 uint32_t msg_type;
573
574 if (intel->gen >= 6)
575 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
576 else if (intel->gen == 5 || intel->is_g4x)
577 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
578 else
579 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
580
581 /* Each of the 8 channel enables is considered for whether each
582 * dword is written.
583 */
584 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
585 brw_set_dest(p, send, dst);
586 brw_set_src0(p, send, header);
587 if (intel->gen < 6)
588 send->header.destreg__conditionalmod = inst->base_mrf;
589 brw_set_dp_read_message(p, send,
590 surf_index,
591 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
592 msg_type,
593 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
594 2, /* mlen */
595 true, /* header_present */
596 1 /* rlen */);
597 }
598
599 void
600 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
601 struct brw_reg dst,
602 struct brw_reg surf_index,
603 struct brw_reg offset)
604 {
605 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
606 surf_index.type == BRW_REGISTER_TYPE_UD);
607
608 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
609 brw_set_dest(p, insn, dst);
610 brw_set_src0(p, insn, offset);
611 brw_set_sampler_message(p, insn,
612 surf_index.dw1.ud,
613 0, /* LD message ignores sampler unit */
614 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
615 1, /* rlen */
616 1, /* mlen */
617 false, /* no header */
618 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
619 0);
620 }
621
622 void
623 vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
624 struct brw_reg dst,
625 struct brw_reg *src)
626 {
627 vec4_instruction *inst = (vec4_instruction *)instruction;
628
629 switch (inst->opcode) {
630 case SHADER_OPCODE_RCP:
631 case SHADER_OPCODE_RSQ:
632 case SHADER_OPCODE_SQRT:
633 case SHADER_OPCODE_EXP2:
634 case SHADER_OPCODE_LOG2:
635 case SHADER_OPCODE_SIN:
636 case SHADER_OPCODE_COS:
637 if (intel->gen == 6) {
638 generate_math1_gen6(inst, dst, src[0]);
639 } else {
640 /* Also works for Gen7. */
641 generate_math1_gen4(inst, dst, src[0]);
642 }
643 break;
644
645 case SHADER_OPCODE_POW:
646 case SHADER_OPCODE_INT_QUOTIENT:
647 case SHADER_OPCODE_INT_REMAINDER:
648 if (intel->gen >= 7) {
649 generate_math2_gen7(inst, dst, src[0], src[1]);
650 } else if (intel->gen == 6) {
651 generate_math2_gen6(inst, dst, src[0], src[1]);
652 } else {
653 generate_math2_gen4(inst, dst, src[0], src[1]);
654 }
655 break;
656
657 case SHADER_OPCODE_TEX:
658 case SHADER_OPCODE_TXD:
659 case SHADER_OPCODE_TXF:
660 case SHADER_OPCODE_TXF_MS:
661 case SHADER_OPCODE_TXL:
662 case SHADER_OPCODE_TXS:
663 generate_tex(inst, dst, src[0]);
664 break;
665
666 case VS_OPCODE_URB_WRITE:
667 generate_urb_write(inst);
668 break;
669
670 case VS_OPCODE_SCRATCH_READ:
671 generate_scratch_read(inst, dst, src[0]);
672 break;
673
674 case VS_OPCODE_SCRATCH_WRITE:
675 generate_scratch_write(inst, dst, src[0], src[1]);
676 break;
677
678 case VS_OPCODE_PULL_CONSTANT_LOAD:
679 generate_pull_constant_load(inst, dst, src[0], src[1]);
680 break;
681
682 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
683 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
684 break;
685
686 case SHADER_OPCODE_SHADER_TIME_ADD:
687 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
688 break;
689
690 default:
691 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
692 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
693 opcode_descs[inst->opcode].name);
694 } else {
695 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
696 }
697 abort();
698 }
699 }
700
701 void
702 vec4_generator::generate_code(exec_list *instructions)
703 {
704 int last_native_insn_offset = 0;
705 const char *last_annotation_string = NULL;
706 const void *last_annotation_ir = NULL;
707
708 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
709 if (shader) {
710 printf("Native code for vertex shader %d:\n", shader_prog->Name);
711 } else {
712 printf("Native code for vertex program %d:\n", prog->Id);
713 }
714 }
715
716 foreach_list(node, instructions) {
717 vec4_instruction *inst = (vec4_instruction *)node;
718 struct brw_reg src[3], dst;
719
720 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
721 if (last_annotation_ir != inst->ir) {
722 last_annotation_ir = inst->ir;
723 if (last_annotation_ir) {
724 printf(" ");
725 if (shader) {
726 ((ir_instruction *) last_annotation_ir)->print();
727 } else {
728 const prog_instruction *vpi;
729 vpi = (const prog_instruction *) inst->ir;
730 printf("%d: ", (int)(vpi - prog->Instructions));
731 _mesa_fprint_instruction_opt(stdout, vpi, 0,
732 PROG_PRINT_DEBUG, NULL);
733 }
734 printf("\n");
735 }
736 }
737 if (last_annotation_string != inst->annotation) {
738 last_annotation_string = inst->annotation;
739 if (last_annotation_string)
740 printf(" %s\n", last_annotation_string);
741 }
742 }
743
744 for (unsigned int i = 0; i < 3; i++) {
745 src[i] = inst->get_src(i);
746 }
747 dst = inst->get_dst();
748
749 brw_set_conditionalmod(p, inst->conditional_mod);
750 brw_set_predicate_control(p, inst->predicate);
751 brw_set_predicate_inverse(p, inst->predicate_inverse);
752 brw_set_saturate(p, inst->saturate);
753 brw_set_mask_control(p, inst->force_writemask_all);
754
755 unsigned pre_emit_nr_insn = p->nr_insn;
756
757 switch (inst->opcode) {
758 case BRW_OPCODE_MOV:
759 brw_MOV(p, dst, src[0]);
760 break;
761 case BRW_OPCODE_ADD:
762 brw_ADD(p, dst, src[0], src[1]);
763 break;
764 case BRW_OPCODE_MUL:
765 brw_MUL(p, dst, src[0], src[1]);
766 break;
767 case BRW_OPCODE_MACH:
768 brw_set_acc_write_control(p, 1);
769 brw_MACH(p, dst, src[0], src[1]);
770 brw_set_acc_write_control(p, 0);
771 break;
772
773 case BRW_OPCODE_FRC:
774 brw_FRC(p, dst, src[0]);
775 break;
776 case BRW_OPCODE_RNDD:
777 brw_RNDD(p, dst, src[0]);
778 break;
779 case BRW_OPCODE_RNDE:
780 brw_RNDE(p, dst, src[0]);
781 break;
782 case BRW_OPCODE_RNDZ:
783 brw_RNDZ(p, dst, src[0]);
784 break;
785
786 case BRW_OPCODE_AND:
787 brw_AND(p, dst, src[0], src[1]);
788 break;
789 case BRW_OPCODE_OR:
790 brw_OR(p, dst, src[0], src[1]);
791 break;
792 case BRW_OPCODE_XOR:
793 brw_XOR(p, dst, src[0], src[1]);
794 break;
795 case BRW_OPCODE_NOT:
796 brw_NOT(p, dst, src[0]);
797 break;
798 case BRW_OPCODE_ASR:
799 brw_ASR(p, dst, src[0], src[1]);
800 break;
801 case BRW_OPCODE_SHR:
802 brw_SHR(p, dst, src[0], src[1]);
803 break;
804 case BRW_OPCODE_SHL:
805 brw_SHL(p, dst, src[0], src[1]);
806 break;
807
808 case BRW_OPCODE_CMP:
809 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
810 break;
811 case BRW_OPCODE_SEL:
812 brw_SEL(p, dst, src[0], src[1]);
813 break;
814
815 case BRW_OPCODE_DPH:
816 brw_DPH(p, dst, src[0], src[1]);
817 break;
818
819 case BRW_OPCODE_DP4:
820 brw_DP4(p, dst, src[0], src[1]);
821 break;
822
823 case BRW_OPCODE_DP3:
824 brw_DP3(p, dst, src[0], src[1]);
825 break;
826
827 case BRW_OPCODE_DP2:
828 brw_DP2(p, dst, src[0], src[1]);
829 break;
830
831 case BRW_OPCODE_F32TO16:
832 brw_F32TO16(p, dst, src[0]);
833 break;
834
835 case BRW_OPCODE_F16TO32:
836 brw_F16TO32(p, dst, src[0]);
837 break;
838
839 case BRW_OPCODE_IF:
840 if (inst->src[0].file != BAD_FILE) {
841 /* The instruction has an embedded compare (only allowed on gen6) */
842 assert(intel->gen == 6);
843 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
844 } else {
845 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
846 brw_inst->header.predicate_control = inst->predicate;
847 }
848 break;
849
850 case BRW_OPCODE_ELSE:
851 brw_ELSE(p);
852 break;
853 case BRW_OPCODE_ENDIF:
854 brw_ENDIF(p);
855 break;
856
857 case BRW_OPCODE_DO:
858 brw_DO(p, BRW_EXECUTE_8);
859 break;
860
861 case BRW_OPCODE_BREAK:
862 brw_BREAK(p);
863 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
864 break;
865 case BRW_OPCODE_CONTINUE:
866 /* FINISHME: We need to write the loop instruction support still. */
867 if (intel->gen >= 6)
868 gen6_CONT(p);
869 else
870 brw_CONT(p);
871 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
872 break;
873
874 case BRW_OPCODE_WHILE:
875 brw_WHILE(p);
876 break;
877
878 default:
879 generate_vs_instruction(inst, dst, src);
880 break;
881 }
882
883 if (inst->no_dd_clear || inst->no_dd_check) {
884 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
885 !"no_dd_check or no_dd_clear set for IR emitting more "
886 "than 1 instruction");
887
888 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
889
890 if (inst->no_dd_clear)
891 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
892 if (inst->no_dd_check)
893 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
894 }
895
896 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
897 brw_dump_compile(p, stdout,
898 last_native_insn_offset, p->next_insn_offset);
899 }
900
901 last_native_insn_offset = p->next_insn_offset;
902 }
903
904 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
905 printf("\n");
906 }
907
908 brw_set_uip_jip(p);
909
910 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
911 * emit issues, it doesn't get the jump distances into the output,
912 * which is often something we want to debug. So this is here in
913 * case you're doing that.
914 */
915 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
916 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
917 }
918 }
919
920 const unsigned *
921 vec4_generator::generate_assembly(exec_list *instructions,
922 unsigned *assembly_size)
923 {
924 brw_set_access_mode(p, BRW_ALIGN_16);
925 generate_code(instructions);
926 return brw_get_program(p, assembly_size);
927 }
928
929 } /* namespace brw */