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i965: add new VS_OPCODE_UNPACK_FLAGS_SIMD4X2
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct gl_shader_program *shader_prog,
137 struct gl_program *prog,
138 void *mem_ctx,
139 bool debug_flag)
140 : brw(brw), shader_prog(shader_prog), prog(prog), mem_ctx(mem_ctx),
141 debug_flag(debug_flag)
142 {
143 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
144
145 p = rzalloc(mem_ctx, struct brw_compile);
146 brw_init_compile(brw, p, mem_ctx);
147 }
148
149 vec4_generator::~vec4_generator()
150 {
151 }
152
153 void
154 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
155 struct brw_reg dst,
156 struct brw_reg src)
157 {
158 brw_math(p,
159 dst,
160 brw_math_function(inst->opcode),
161 inst->base_mrf,
162 src,
163 BRW_MATH_DATA_VECTOR,
164 BRW_MATH_PRECISION_FULL);
165 }
166
167 static void
168 check_gen6_math_src_arg(struct brw_reg src)
169 {
170 /* Source swizzles are ignored. */
171 assert(!src.abs);
172 assert(!src.negate);
173 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
174 }
175
176 void
177 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
178 struct brw_reg dst,
179 struct brw_reg src)
180 {
181 /* Can't do writemask because math can't be align16. */
182 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
183 check_gen6_math_src_arg(src);
184
185 brw_set_access_mode(p, BRW_ALIGN_1);
186 brw_math(p,
187 dst,
188 brw_math_function(inst->opcode),
189 inst->base_mrf,
190 src,
191 BRW_MATH_DATA_SCALAR,
192 BRW_MATH_PRECISION_FULL);
193 brw_set_access_mode(p, BRW_ALIGN_16);
194 }
195
196 void
197 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
198 struct brw_reg dst,
199 struct brw_reg src0,
200 struct brw_reg src1)
201 {
202 brw_math2(p,
203 dst,
204 brw_math_function(inst->opcode),
205 src0, src1);
206 }
207
208 void
209 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
210 struct brw_reg dst,
211 struct brw_reg src0,
212 struct brw_reg src1)
213 {
214 /* Can't do writemask because math can't be align16. */
215 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
216 /* Source swizzles are ignored. */
217 check_gen6_math_src_arg(src0);
218 check_gen6_math_src_arg(src1);
219
220 brw_set_access_mode(p, BRW_ALIGN_1);
221 brw_math2(p,
222 dst,
223 brw_math_function(inst->opcode),
224 src0, src1);
225 brw_set_access_mode(p, BRW_ALIGN_16);
226 }
227
228 void
229 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
230 struct brw_reg dst,
231 struct brw_reg src0,
232 struct brw_reg src1)
233 {
234 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
235 * "Message Payload":
236 *
237 * "Operand0[7]. For the INT DIV functions, this operand is the
238 * denominator."
239 * ...
240 * "Operand1[7]. For the INT DIV functions, this operand is the
241 * numerator."
242 */
243 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
244 struct brw_reg &op0 = is_int_div ? src1 : src0;
245 struct brw_reg &op1 = is_int_div ? src0 : src1;
246
247 brw_push_insn_state(p);
248 brw_set_saturate(p, false);
249 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
250 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
251 brw_pop_insn_state(p);
252
253 brw_math(p,
254 dst,
255 brw_math_function(inst->opcode),
256 inst->base_mrf,
257 op0,
258 BRW_MATH_DATA_VECTOR,
259 BRW_MATH_PRECISION_FULL);
260 }
261
262 void
263 vec4_generator::generate_tex(vec4_instruction *inst,
264 struct brw_reg dst,
265 struct brw_reg src)
266 {
267 int msg_type = -1;
268
269 if (brw->gen >= 5) {
270 switch (inst->opcode) {
271 case SHADER_OPCODE_TEX:
272 case SHADER_OPCODE_TXL:
273 if (inst->shadow_compare) {
274 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
275 } else {
276 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
277 }
278 break;
279 case SHADER_OPCODE_TXD:
280 if (inst->shadow_compare) {
281 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
282 assert(brw->is_haswell);
283 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
284 } else {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
286 }
287 break;
288 case SHADER_OPCODE_TXF:
289 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
290 break;
291 case SHADER_OPCODE_TXF_MS:
292 if (brw->gen >= 7)
293 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
294 else
295 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
296 break;
297 case SHADER_OPCODE_TXS:
298 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
299 break;
300 default:
301 assert(!"should not get here: invalid VS texture opcode");
302 break;
303 }
304 } else {
305 switch (inst->opcode) {
306 case SHADER_OPCODE_TEX:
307 case SHADER_OPCODE_TXL:
308 if (inst->shadow_compare) {
309 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
310 assert(inst->mlen == 3);
311 } else {
312 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
313 assert(inst->mlen == 2);
314 }
315 break;
316 case SHADER_OPCODE_TXD:
317 /* There is no sample_d_c message; comparisons are done manually. */
318 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
319 assert(inst->mlen == 4);
320 break;
321 case SHADER_OPCODE_TXF:
322 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
323 assert(inst->mlen == 2);
324 break;
325 case SHADER_OPCODE_TXS:
326 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
327 assert(inst->mlen == 2);
328 break;
329 default:
330 assert(!"should not get here: invalid VS texture opcode");
331 break;
332 }
333 }
334
335 assert(msg_type != -1);
336
337 /* Load the message header if present. If there's a texture offset, we need
338 * to set it up explicitly and load the offset bitfield. Otherwise, we can
339 * use an implied move from g0 to the first message register.
340 */
341 if (inst->texture_offset) {
342 /* Explicitly set up the message header by copying g0 to the MRF. */
343 brw_push_insn_state(p);
344 brw_set_mask_control(p, BRW_MASK_DISABLE);
345 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
346 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
347
348 /* Then set the offset bits in DWord 2. */
349 brw_set_access_mode(p, BRW_ALIGN_1);
350 brw_MOV(p,
351 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
352 BRW_REGISTER_TYPE_UD),
353 brw_imm_uw(inst->texture_offset));
354 brw_pop_insn_state(p);
355 } else if (inst->header_present) {
356 /* Set up an implied move from g0 to the MRF. */
357 src = brw_vec8_grf(0, 0);
358 }
359
360 uint32_t return_format;
361
362 switch (dst.type) {
363 case BRW_REGISTER_TYPE_D:
364 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
365 break;
366 case BRW_REGISTER_TYPE_UD:
367 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
368 break;
369 default:
370 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
371 break;
372 }
373
374 brw_SAMPLE(p,
375 dst,
376 inst->base_mrf,
377 src,
378 SURF_INDEX_VS_TEXTURE(inst->sampler),
379 inst->sampler,
380 msg_type,
381 1, /* response length */
382 inst->mlen,
383 inst->header_present,
384 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
385 return_format);
386 }
387
388 void
389 vec4_generator::generate_urb_write(vec4_instruction *inst)
390 {
391 brw_urb_WRITE(p,
392 brw_null_reg(), /* dest */
393 inst->base_mrf, /* starting mrf reg nr */
394 brw_vec8_grf(0, 0), /* src */
395 false, /* allocate */
396 true, /* used */
397 inst->mlen,
398 0, /* response len */
399 inst->eot, /* eot */
400 inst->eot, /* writes complete */
401 inst->offset, /* urb destination offset */
402 BRW_URB_SWIZZLE_INTERLEAVE);
403 }
404
405 void
406 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
407 struct brw_reg index)
408 {
409 int second_vertex_offset;
410
411 if (brw->gen >= 6)
412 second_vertex_offset = 1;
413 else
414 second_vertex_offset = 16;
415
416 m1 = retype(m1, BRW_REGISTER_TYPE_D);
417
418 /* Set up M1 (message payload). Only the block offsets in M1.0 and
419 * M1.4 are used, and the rest are ignored.
420 */
421 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
422 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
423 struct brw_reg index_0 = suboffset(vec1(index), 0);
424 struct brw_reg index_4 = suboffset(vec1(index), 4);
425
426 brw_push_insn_state(p);
427 brw_set_mask_control(p, BRW_MASK_DISABLE);
428 brw_set_access_mode(p, BRW_ALIGN_1);
429
430 brw_MOV(p, m1_0, index_0);
431
432 if (index.file == BRW_IMMEDIATE_VALUE) {
433 index_4.dw1.ud += second_vertex_offset;
434 brw_MOV(p, m1_4, index_4);
435 } else {
436 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
437 }
438
439 brw_pop_insn_state(p);
440 }
441
442 void
443 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
444 struct brw_reg dst)
445 {
446 brw_push_insn_state(p);
447 brw_set_mask_control(p, BRW_MASK_DISABLE);
448 brw_set_access_mode(p, BRW_ALIGN_1);
449
450 struct brw_reg flags = brw_flag_reg(0, 0);
451 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
452 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
453
454 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
455 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
456 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
457
458 brw_pop_insn_state(p);
459 }
460
461 void
462 vec4_generator::generate_scratch_read(vec4_instruction *inst,
463 struct brw_reg dst,
464 struct brw_reg index)
465 {
466 struct brw_reg header = brw_vec8_grf(0, 0);
467
468 gen6_resolve_implied_move(p, &header, inst->base_mrf);
469
470 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
471 index);
472
473 uint32_t msg_type;
474
475 if (brw->gen >= 6)
476 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
477 else if (brw->gen == 5 || brw->is_g4x)
478 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
479 else
480 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
481
482 /* Each of the 8 channel enables is considered for whether each
483 * dword is written.
484 */
485 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
486 brw_set_dest(p, send, dst);
487 brw_set_src0(p, send, header);
488 if (brw->gen < 6)
489 send->header.destreg__conditionalmod = inst->base_mrf;
490 brw_set_dp_read_message(p, send,
491 255, /* binding table index: stateless access */
492 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
493 msg_type,
494 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
495 2, /* mlen */
496 true, /* header_present */
497 1 /* rlen */);
498 }
499
500 void
501 vec4_generator::generate_scratch_write(vec4_instruction *inst,
502 struct brw_reg dst,
503 struct brw_reg src,
504 struct brw_reg index)
505 {
506 struct brw_reg header = brw_vec8_grf(0, 0);
507 bool write_commit;
508
509 /* If the instruction is predicated, we'll predicate the send, not
510 * the header setup.
511 */
512 brw_set_predicate_control(p, false);
513
514 gen6_resolve_implied_move(p, &header, inst->base_mrf);
515
516 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
517 index);
518
519 brw_MOV(p,
520 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
521 retype(src, BRW_REGISTER_TYPE_D));
522
523 uint32_t msg_type;
524
525 if (brw->gen >= 7)
526 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
527 else if (brw->gen == 6)
528 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
529 else
530 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
531
532 brw_set_predicate_control(p, inst->predicate);
533
534 /* Pre-gen6, we have to specify write commits to ensure ordering
535 * between reads and writes within a thread. Afterwards, that's
536 * guaranteed and write commits only matter for inter-thread
537 * synchronization.
538 */
539 if (brw->gen >= 6) {
540 write_commit = false;
541 } else {
542 /* The visitor set up our destination register to be g0. This
543 * means that when the next read comes along, we will end up
544 * reading from g0 and causing a block on the write commit. For
545 * write-after-read, we are relying on the value of the previous
546 * read being used (and thus blocking on completion) before our
547 * write is executed. This means we have to be careful in
548 * instruction scheduling to not violate this assumption.
549 */
550 write_commit = true;
551 }
552
553 /* Each of the 8 channel enables is considered for whether each
554 * dword is written.
555 */
556 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
557 brw_set_dest(p, send, dst);
558 brw_set_src0(p, send, header);
559 if (brw->gen < 6)
560 send->header.destreg__conditionalmod = inst->base_mrf;
561 brw_set_dp_write_message(p, send,
562 255, /* binding table index: stateless access */
563 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
564 msg_type,
565 3, /* mlen */
566 true, /* header present */
567 false, /* not a render target write */
568 write_commit, /* rlen */
569 false, /* eot */
570 write_commit);
571 }
572
573 void
574 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
575 struct brw_reg dst,
576 struct brw_reg index,
577 struct brw_reg offset)
578 {
579 assert(brw->gen <= 7);
580 assert(index.file == BRW_IMMEDIATE_VALUE &&
581 index.type == BRW_REGISTER_TYPE_UD);
582 uint32_t surf_index = index.dw1.ud;
583
584 struct brw_reg header = brw_vec8_grf(0, 0);
585
586 gen6_resolve_implied_move(p, &header, inst->base_mrf);
587
588 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
589 offset);
590
591 uint32_t msg_type;
592
593 if (brw->gen >= 6)
594 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
595 else if (brw->gen == 5 || brw->is_g4x)
596 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
597 else
598 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
599
600 /* Each of the 8 channel enables is considered for whether each
601 * dword is written.
602 */
603 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
604 brw_set_dest(p, send, dst);
605 brw_set_src0(p, send, header);
606 if (brw->gen < 6)
607 send->header.destreg__conditionalmod = inst->base_mrf;
608 brw_set_dp_read_message(p, send,
609 surf_index,
610 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
611 msg_type,
612 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
613 2, /* mlen */
614 true, /* header_present */
615 1 /* rlen */);
616 }
617
618 void
619 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
620 struct brw_reg dst,
621 struct brw_reg surf_index,
622 struct brw_reg offset)
623 {
624 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
625 surf_index.type == BRW_REGISTER_TYPE_UD);
626
627 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
628 brw_set_dest(p, insn, dst);
629 brw_set_src0(p, insn, offset);
630 brw_set_sampler_message(p, insn,
631 surf_index.dw1.ud,
632 0, /* LD message ignores sampler unit */
633 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
634 1, /* rlen */
635 1, /* mlen */
636 false, /* no header */
637 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
638 0);
639 }
640
641 /**
642 * Generate assembly for a Vec4 IR instruction.
643 *
644 * \param instruction The Vec4 IR instruction to generate code for.
645 * \param dst The destination register.
646 * \param src An array of up to three source registers.
647 */
648 void
649 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
650 struct brw_reg dst,
651 struct brw_reg *src)
652 {
653 vec4_instruction *inst = (vec4_instruction *) instruction;
654
655 switch (inst->opcode) {
656 case BRW_OPCODE_MOV:
657 brw_MOV(p, dst, src[0]);
658 break;
659 case BRW_OPCODE_ADD:
660 brw_ADD(p, dst, src[0], src[1]);
661 break;
662 case BRW_OPCODE_MUL:
663 brw_MUL(p, dst, src[0], src[1]);
664 break;
665 case BRW_OPCODE_MACH:
666 brw_set_acc_write_control(p, 1);
667 brw_MACH(p, dst, src[0], src[1]);
668 brw_set_acc_write_control(p, 0);
669 break;
670
671 case BRW_OPCODE_MAD:
672 brw_MAD(p, dst, src[0], src[1], src[2]);
673 break;
674
675 case BRW_OPCODE_FRC:
676 brw_FRC(p, dst, src[0]);
677 break;
678 case BRW_OPCODE_RNDD:
679 brw_RNDD(p, dst, src[0]);
680 break;
681 case BRW_OPCODE_RNDE:
682 brw_RNDE(p, dst, src[0]);
683 break;
684 case BRW_OPCODE_RNDZ:
685 brw_RNDZ(p, dst, src[0]);
686 break;
687
688 case BRW_OPCODE_AND:
689 brw_AND(p, dst, src[0], src[1]);
690 break;
691 case BRW_OPCODE_OR:
692 brw_OR(p, dst, src[0], src[1]);
693 break;
694 case BRW_OPCODE_XOR:
695 brw_XOR(p, dst, src[0], src[1]);
696 break;
697 case BRW_OPCODE_NOT:
698 brw_NOT(p, dst, src[0]);
699 break;
700 case BRW_OPCODE_ASR:
701 brw_ASR(p, dst, src[0], src[1]);
702 break;
703 case BRW_OPCODE_SHR:
704 brw_SHR(p, dst, src[0], src[1]);
705 break;
706 case BRW_OPCODE_SHL:
707 brw_SHL(p, dst, src[0], src[1]);
708 break;
709
710 case BRW_OPCODE_CMP:
711 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
712 break;
713 case BRW_OPCODE_SEL:
714 brw_SEL(p, dst, src[0], src[1]);
715 break;
716
717 case BRW_OPCODE_DPH:
718 brw_DPH(p, dst, src[0], src[1]);
719 break;
720
721 case BRW_OPCODE_DP4:
722 brw_DP4(p, dst, src[0], src[1]);
723 break;
724
725 case BRW_OPCODE_DP3:
726 brw_DP3(p, dst, src[0], src[1]);
727 break;
728
729 case BRW_OPCODE_DP2:
730 brw_DP2(p, dst, src[0], src[1]);
731 break;
732
733 case BRW_OPCODE_F32TO16:
734 brw_F32TO16(p, dst, src[0]);
735 break;
736
737 case BRW_OPCODE_F16TO32:
738 brw_F16TO32(p, dst, src[0]);
739 break;
740
741 case BRW_OPCODE_LRP:
742 brw_LRP(p, dst, src[0], src[1], src[2]);
743 break;
744
745 case BRW_OPCODE_BFREV:
746 /* BFREV only supports UD type for src and dst. */
747 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
748 retype(src[0], BRW_REGISTER_TYPE_UD));
749 break;
750 case BRW_OPCODE_FBH:
751 /* FBH only supports UD type for dst. */
752 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
753 break;
754 case BRW_OPCODE_FBL:
755 /* FBL only supports UD type for dst. */
756 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
757 break;
758 case BRW_OPCODE_CBIT:
759 /* CBIT only supports UD type for dst. */
760 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
761 break;
762
763 case BRW_OPCODE_BFE:
764 brw_BFE(p, dst, src[0], src[1], src[2]);
765 break;
766
767 case BRW_OPCODE_BFI1:
768 brw_BFI1(p, dst, src[0], src[1]);
769 break;
770 case BRW_OPCODE_BFI2:
771 brw_BFI2(p, dst, src[0], src[1], src[2]);
772 break;
773
774 case BRW_OPCODE_IF:
775 if (inst->src[0].file != BAD_FILE) {
776 /* The instruction has an embedded compare (only allowed on gen6) */
777 assert(brw->gen == 6);
778 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
779 } else {
780 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
781 brw_inst->header.predicate_control = inst->predicate;
782 }
783 break;
784
785 case BRW_OPCODE_ELSE:
786 brw_ELSE(p);
787 break;
788 case BRW_OPCODE_ENDIF:
789 brw_ENDIF(p);
790 break;
791
792 case BRW_OPCODE_DO:
793 brw_DO(p, BRW_EXECUTE_8);
794 break;
795
796 case BRW_OPCODE_BREAK:
797 brw_BREAK(p);
798 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
799 break;
800 case BRW_OPCODE_CONTINUE:
801 /* FINISHME: We need to write the loop instruction support still. */
802 if (brw->gen >= 6)
803 gen6_CONT(p);
804 else
805 brw_CONT(p);
806 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
807 break;
808
809 case BRW_OPCODE_WHILE:
810 brw_WHILE(p);
811 break;
812
813 case SHADER_OPCODE_RCP:
814 case SHADER_OPCODE_RSQ:
815 case SHADER_OPCODE_SQRT:
816 case SHADER_OPCODE_EXP2:
817 case SHADER_OPCODE_LOG2:
818 case SHADER_OPCODE_SIN:
819 case SHADER_OPCODE_COS:
820 if (brw->gen == 6) {
821 generate_math1_gen6(inst, dst, src[0]);
822 } else {
823 /* Also works for Gen7. */
824 generate_math1_gen4(inst, dst, src[0]);
825 }
826 break;
827
828 case SHADER_OPCODE_POW:
829 case SHADER_OPCODE_INT_QUOTIENT:
830 case SHADER_OPCODE_INT_REMAINDER:
831 if (brw->gen >= 7) {
832 generate_math2_gen7(inst, dst, src[0], src[1]);
833 } else if (brw->gen == 6) {
834 generate_math2_gen6(inst, dst, src[0], src[1]);
835 } else {
836 generate_math2_gen4(inst, dst, src[0], src[1]);
837 }
838 break;
839
840 case SHADER_OPCODE_TEX:
841 case SHADER_OPCODE_TXD:
842 case SHADER_OPCODE_TXF:
843 case SHADER_OPCODE_TXF_MS:
844 case SHADER_OPCODE_TXL:
845 case SHADER_OPCODE_TXS:
846 generate_tex(inst, dst, src[0]);
847 break;
848
849 case VS_OPCODE_URB_WRITE:
850 generate_urb_write(inst);
851 break;
852
853 case VS_OPCODE_SCRATCH_READ:
854 generate_scratch_read(inst, dst, src[0]);
855 break;
856
857 case VS_OPCODE_SCRATCH_WRITE:
858 generate_scratch_write(inst, dst, src[0], src[1]);
859 break;
860
861 case VS_OPCODE_PULL_CONSTANT_LOAD:
862 generate_pull_constant_load(inst, dst, src[0], src[1]);
863 break;
864
865 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
866 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
867 break;
868
869 case SHADER_OPCODE_SHADER_TIME_ADD:
870 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
871 break;
872
873 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
874 generate_unpack_flags(inst, dst);
875 break;
876
877 default:
878 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
879 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
880 opcode_descs[inst->opcode].name);
881 } else {
882 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
883 }
884 abort();
885 }
886 }
887
888 void
889 vec4_generator::generate_code(exec_list *instructions)
890 {
891 int last_native_insn_offset = 0;
892 const char *last_annotation_string = NULL;
893 const void *last_annotation_ir = NULL;
894
895 if (unlikely(debug_flag)) {
896 if (shader) {
897 printf("Native code for vertex shader %d:\n", shader_prog->Name);
898 } else {
899 printf("Native code for vertex program %d:\n", prog->Id);
900 }
901 }
902
903 foreach_list(node, instructions) {
904 vec4_instruction *inst = (vec4_instruction *)node;
905 struct brw_reg src[3], dst;
906
907 if (unlikely(debug_flag)) {
908 if (last_annotation_ir != inst->ir) {
909 last_annotation_ir = inst->ir;
910 if (last_annotation_ir) {
911 printf(" ");
912 if (shader) {
913 ((ir_instruction *) last_annotation_ir)->print();
914 } else {
915 const prog_instruction *vpi;
916 vpi = (const prog_instruction *) inst->ir;
917 printf("%d: ", (int)(vpi - prog->Instructions));
918 _mesa_fprint_instruction_opt(stdout, vpi, 0,
919 PROG_PRINT_DEBUG, NULL);
920 }
921 printf("\n");
922 }
923 }
924 if (last_annotation_string != inst->annotation) {
925 last_annotation_string = inst->annotation;
926 if (last_annotation_string)
927 printf(" %s\n", last_annotation_string);
928 }
929 }
930
931 for (unsigned int i = 0; i < 3; i++) {
932 src[i] = inst->get_src(i);
933 }
934 dst = inst->get_dst();
935
936 brw_set_conditionalmod(p, inst->conditional_mod);
937 brw_set_predicate_control(p, inst->predicate);
938 brw_set_predicate_inverse(p, inst->predicate_inverse);
939 brw_set_saturate(p, inst->saturate);
940 brw_set_mask_control(p, inst->force_writemask_all);
941
942 unsigned pre_emit_nr_insn = p->nr_insn;
943
944 generate_vec4_instruction(inst, dst, src);
945
946 if (inst->no_dd_clear || inst->no_dd_check) {
947 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
948 !"no_dd_check or no_dd_clear set for IR emitting more "
949 "than 1 instruction");
950
951 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
952
953 if (inst->no_dd_clear)
954 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
955 if (inst->no_dd_check)
956 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
957 }
958
959 if (unlikely(debug_flag)) {
960 brw_dump_compile(p, stdout,
961 last_native_insn_offset, p->next_insn_offset);
962 }
963
964 last_native_insn_offset = p->next_insn_offset;
965 }
966
967 if (unlikely(debug_flag)) {
968 printf("\n");
969 }
970
971 brw_set_uip_jip(p);
972
973 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
974 * emit issues, it doesn't get the jump distances into the output,
975 * which is often something we want to debug. So this is here in
976 * case you're doing that.
977 */
978 if (0 && unlikely(debug_flag)) {
979 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
980 }
981 }
982
983 const unsigned *
984 vec4_generator::generate_assembly(exec_list *instructions,
985 unsigned *assembly_size)
986 {
987 brw_set_access_mode(p, BRW_ALIGN_16);
988 generate_code(instructions);
989 return brw_get_program(p, assembly_size);
990 }
991
992 } /* namespace brw */