src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24
  25 extern "C" {
  26 #include "brw_eu.h"
  27 #include "main/macros.h"
  28 #include "program/prog_print.h"
  29 #include "program/prog_parameter.h"
  30 };
  31
  32 namespace brw {
  33
  34 struct brw_reg
  35 vec4_instruction::get_dst(void)
  36 {
  37    struct brw_reg brw_reg;
  38
  39    switch (dst.file) {
  40    case GRF:
  41       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
  42       brw_reg = retype(brw_reg, dst.type);
  43       brw_reg.dw1.bits.writemask = dst.writemask;
  44       break;
  45
  46    case MRF:
  47       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
  48       brw_reg = retype(brw_reg, dst.type);
  49       brw_reg.dw1.bits.writemask = dst.writemask;
  50       break;
  51
  52    case HW_REG:
  53       brw_reg = dst.fixed_hw_reg;
  54       break;
  55
  56    case BAD_FILE:
  57       brw_reg = brw_null_reg();
  58       break;
  59
  60    default:
  61       assert(!"not reached");
  62       brw_reg = brw_null_reg();
  63       break;
  64    }
  65    return brw_reg;
  66 }
  67
  68 struct brw_reg
  69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
  70 {
  71    struct brw_reg brw_reg;
  72
  73    switch (src[i].file) {
  74    case GRF:
  75       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
  76       brw_reg = retype(brw_reg, src[i].type);
  77       brw_reg.dw1.bits.swizzle = src[i].swizzle;
  78       if (src[i].abs)
  79          brw_reg = brw_abs(brw_reg);
  80       if (src[i].negate)
  81          brw_reg = negate(brw_reg);
  82       break;
  83
  84    case IMM:
  85       switch (src[i].type) {
  86       case BRW_REGISTER_TYPE_F:
  87          brw_reg = brw_imm_f(src[i].imm.f);
  88          break;
  89       case BRW_REGISTER_TYPE_D:
  90          brw_reg = brw_imm_d(src[i].imm.i);
  91          break;
  92       case BRW_REGISTER_TYPE_UD:
  93          brw_reg = brw_imm_ud(src[i].imm.u);
  94          break;
  95       default:
  96          assert(!"not reached");
  97          brw_reg = brw_null_reg();
  98          break;
  99       }
 100       break;
 101
 102    case UNIFORM:
 103       brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
 104                                     (src[i].reg + src[i].reg_offset) / 2,
 105                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 106                        0, 4, 1);
 107       brw_reg = retype(brw_reg, src[i].type);
 108       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 109       if (src[i].abs)
 110          brw_reg = brw_abs(brw_reg);
 111       if (src[i].negate)
 112          brw_reg = negate(brw_reg);
 113
 114       /* This should have been moved to pull constants. */
 115       assert(!src[i].reladdr);
 116       break;
 117
 118    case HW_REG:
 119       brw_reg = src[i].fixed_hw_reg;
 120       break;
 121
 122    case BAD_FILE:
 123       /* Probably unused. */
 124       brw_reg = brw_null_reg();
 125       break;
 126    case ATTR:
 127    default:
 128       assert(!"not reached");
 129       brw_reg = brw_null_reg();
 130       break;
 131    }
 132
 133    return brw_reg;
 134 }
 135
 136 vec4_generator::vec4_generator(struct brw_context *brw,
 137                                struct gl_shader_program *shader_prog,
 138                                struct gl_program *prog,
 139                                struct brw_vec4_prog_data *prog_data,
 140                                void *mem_ctx,
 141                                bool debug_flag)
 142    : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
 143      mem_ctx(mem_ctx), debug_flag(debug_flag)
 144 {
 145    shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
 146
 147    p = rzalloc(mem_ctx, struct brw_compile);
 148    brw_init_compile(brw, p, mem_ctx);
 149 }
 150
 151 vec4_generator::~vec4_generator()
 152 {
 153 }
 154
 155 void
 156 vec4_generator::mark_surface_used(unsigned surf_index)
 157 {
 158    assert(surf_index < BRW_MAX_VS_SURFACES);
 159
 160    prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
 161                                         surf_index + 1);
 162 }
 163
 164 void
 165 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
 166                                     struct brw_reg dst,
 167                                     struct brw_reg src)
 168 {
 169    brw_math(p,
 170             dst,
 171             brw_math_function(inst->opcode),
 172             inst->base_mrf,
 173             src,
 174             BRW_MATH_DATA_VECTOR,
 175             BRW_MATH_PRECISION_FULL);
 176 }
 177
 178 static void
 179 check_gen6_math_src_arg(struct brw_reg src)
 180 {
 181    /* Source swizzles are ignored. */
 182    assert(!src.abs);
 183    assert(!src.negate);
 184    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 185 }
 186
 187 void
 188 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
 189                                     struct brw_reg dst,
 190                                     struct brw_reg src)
 191 {
 192    /* Can't do writemask because math can't be align16. */
 193    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 194    check_gen6_math_src_arg(src);
 195
 196    brw_set_access_mode(p, BRW_ALIGN_1);
 197    brw_math(p,
 198             dst,
 199             brw_math_function(inst->opcode),
 200             inst->base_mrf,
 201             src,
 202             BRW_MATH_DATA_SCALAR,
 203             BRW_MATH_PRECISION_FULL);
 204    brw_set_access_mode(p, BRW_ALIGN_16);
 205 }
 206
 207 void
 208 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
 209                                     struct brw_reg dst,
 210                                     struct brw_reg src0,
 211                                     struct brw_reg src1)
 212 {
 213    brw_math2(p,
 214              dst,
 215              brw_math_function(inst->opcode),
 216              src0, src1);
 217 }
 218
 219 void
 220 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
 221                                     struct brw_reg dst,
 222                                     struct brw_reg src0,
 223                                     struct brw_reg src1)
 224 {
 225    /* Can't do writemask because math can't be align16. */
 226    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 227    /* Source swizzles are ignored. */
 228    check_gen6_math_src_arg(src0);
 229    check_gen6_math_src_arg(src1);
 230
 231    brw_set_access_mode(p, BRW_ALIGN_1);
 232    brw_math2(p,
 233              dst,
 234              brw_math_function(inst->opcode),
 235              src0, src1);
 236    brw_set_access_mode(p, BRW_ALIGN_16);
 237 }
 238
 239 void
 240 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
 241                                     struct brw_reg dst,
 242                                     struct brw_reg src0,
 243                                     struct brw_reg src1)
 244 {
 245    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 246     * "Message Payload":
 247     *
 248     * "Operand0[7].  For the INT DIV functions, this operand is the
 249     *  denominator."
 250     *  ...
 251     * "Operand1[7].  For the INT DIV functions, this operand is the
 252     *  numerator."
 253     */
 254    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 255    struct brw_reg &op0 = is_int_div ? src1 : src0;
 256    struct brw_reg &op1 = is_int_div ? src0 : src1;
 257
 258    brw_push_insn_state(p);
 259    brw_set_saturate(p, false);
 260    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 261    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 262    brw_pop_insn_state(p);
 263
 264    brw_math(p,
 265             dst,
 266             brw_math_function(inst->opcode),
 267             inst->base_mrf,
 268             op0,
 269             BRW_MATH_DATA_VECTOR,
 270             BRW_MATH_PRECISION_FULL);
 271 }
 272
 273 void
 274 vec4_generator::generate_tex(vec4_instruction *inst,
 275                              struct brw_reg dst,
 276                              struct brw_reg src)
 277 {
 278    int msg_type = -1;
 279
 280    if (brw->gen >= 5) {
 281       switch (inst->opcode) {
 282       case SHADER_OPCODE_TEX:
 283       case SHADER_OPCODE_TXL:
 284          if (inst->shadow_compare) {
 285             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
 286          } else {
 287             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
 288          }
 289          break;
 290       case SHADER_OPCODE_TXD:
 291          if (inst->shadow_compare) {
 292             /* Gen7.5+.  Otherwise, lowered by brw_lower_texture_gradients(). */
 293             assert(brw->is_haswell);
 294             msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
 295          } else {
 296             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
 297          }
 298          break;
 299       case SHADER_OPCODE_TXF:
 300          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 301          break;
 302       case SHADER_OPCODE_TXF_MS:
 303          if (brw->gen >= 7)
 304             msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
 305          else
 306             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 307          break;
 308       case SHADER_OPCODE_TXS:
 309          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 310          break;
 311       default:
 312          assert(!"should not get here: invalid VS texture opcode");
 313          break;
 314       }
 315    } else {
 316       switch (inst->opcode) {
 317       case SHADER_OPCODE_TEX:
 318       case SHADER_OPCODE_TXL:
 319          if (inst->shadow_compare) {
 320             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
 321             assert(inst->mlen == 3);
 322          } else {
 323             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
 324             assert(inst->mlen == 2);
 325          }
 326          break;
 327       case SHADER_OPCODE_TXD:
 328          /* There is no sample_d_c message; comparisons are done manually. */
 329          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
 330          assert(inst->mlen == 4);
 331          break;
 332       case SHADER_OPCODE_TXF:
 333          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
 334          assert(inst->mlen == 2);
 335          break;
 336       case SHADER_OPCODE_TXS:
 337          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
 338          assert(inst->mlen == 2);
 339          break;
 340       default:
 341          assert(!"should not get here: invalid VS texture opcode");
 342          break;
 343       }
 344    }
 345
 346    assert(msg_type != -1);
 347
 348    /* Load the message header if present.  If there's a texture offset, we need
 349     * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 350     * use an implied move from g0 to the first message register.
 351     */
 352    if (inst->texture_offset) {
 353       /* Explicitly set up the message header by copying g0 to the MRF. */
 354       brw_push_insn_state(p);
 355       brw_set_mask_control(p, BRW_MASK_DISABLE);
 356       brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
 357                  retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 358
 359       /* Then set the offset bits in DWord 2. */
 360       brw_set_access_mode(p, BRW_ALIGN_1);
 361       brw_MOV(p,
 362               retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
 363                      BRW_REGISTER_TYPE_UD),
 364               brw_imm_uw(inst->texture_offset));
 365       brw_pop_insn_state(p);
 366    } else if (inst->header_present) {
 367       /* Set up an implied move from g0 to the MRF. */
 368       src = brw_vec8_grf(0, 0);
 369    }
 370
 371    uint32_t return_format;
 372
 373    switch (dst.type) {
 374    case BRW_REGISTER_TYPE_D:
 375       return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
 376       break;
 377    case BRW_REGISTER_TYPE_UD:
 378       return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
 379       break;
 380    default:
 381       return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
 382       break;
 383    }
 384
 385    brw_SAMPLE(p,
 386               dst,
 387               inst->base_mrf,
 388               src,
 389               SURF_INDEX_VS_TEXTURE(inst->sampler),
 390               inst->sampler,
 391               msg_type,
 392               1, /* response length */
 393               inst->mlen,
 394               inst->header_present,
 395               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 396               return_format);
 397
 398    mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
 399 }
 400
 401 void
 402 vec4_generator::generate_urb_write(vec4_instruction *inst)
 403 {
 404    brw_urb_WRITE(p,
 405                  brw_null_reg(), /* dest */
 406                  inst->base_mrf, /* starting mrf reg nr */
 407                  brw_vec8_grf(0, 0), /* src */
 408                  inst->urb_write_flags,
 409                  inst->mlen,
 410                  0,             /* response len */
 411                  inst->offset,  /* urb destination offset */
 412                  BRW_URB_SWIZZLE_INTERLEAVE);
 413 }
 414
 415 void
 416 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
 417                                                   struct brw_reg index)
 418 {
 419    int second_vertex_offset;
 420
 421    if (brw->gen >= 6)
 422       second_vertex_offset = 1;
 423    else
 424       second_vertex_offset = 16;
 425
 426    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 427
 428    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 429     * M1.4 are used, and the rest are ignored.
 430     */
 431    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 432    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 433    struct brw_reg index_0 = suboffset(vec1(index), 0);
 434    struct brw_reg index_4 = suboffset(vec1(index), 4);
 435
 436    brw_push_insn_state(p);
 437    brw_set_mask_control(p, BRW_MASK_DISABLE);
 438    brw_set_access_mode(p, BRW_ALIGN_1);
 439
 440    brw_MOV(p, m1_0, index_0);
 441
 442    if (index.file == BRW_IMMEDIATE_VALUE) {
 443       index_4.dw1.ud += second_vertex_offset;
 444       brw_MOV(p, m1_4, index_4);
 445    } else {
 446       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 447    }
 448
 449    brw_pop_insn_state(p);
 450 }
 451
 452 void
 453 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
 454                                       struct brw_reg dst)
 455 {
 456    brw_push_insn_state(p);
 457    brw_set_mask_control(p, BRW_MASK_DISABLE);
 458    brw_set_access_mode(p, BRW_ALIGN_1);
 459
 460    struct brw_reg flags = brw_flag_reg(0, 0);
 461    struct brw_reg dst_0 = suboffset(vec1(dst), 0);
 462    struct brw_reg dst_4 = suboffset(vec1(dst), 4);
 463
 464    brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
 465    brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
 466    brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
 467
 468    brw_pop_insn_state(p);
 469 }
 470
 471 void
 472 vec4_generator::generate_scratch_read(vec4_instruction *inst,
 473                                       struct brw_reg dst,
 474                                       struct brw_reg index)
 475 {
 476    struct brw_reg header = brw_vec8_grf(0, 0);
 477
 478    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 479
 480    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 481                                      index);
 482
 483    uint32_t msg_type;
 484
 485    if (brw->gen >= 6)
 486       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 487    else if (brw->gen == 5 || brw->is_g4x)
 488       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 489    else
 490       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 491
 492    /* Each of the 8 channel enables is considered for whether each
 493     * dword is written.
 494     */
 495    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 496    brw_set_dest(p, send, dst);
 497    brw_set_src0(p, send, header);
 498    if (brw->gen < 6)
 499       send->header.destreg__conditionalmod = inst->base_mrf;
 500    brw_set_dp_read_message(p, send,
 501                            255, /* binding table index: stateless access */
 502                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 503                            msg_type,
 504                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 505                            2, /* mlen */
 506                            true, /* header_present */
 507                            1 /* rlen */);
 508 }
 509
 510 void
 511 vec4_generator::generate_scratch_write(vec4_instruction *inst,
 512                                        struct brw_reg dst,
 513                                        struct brw_reg src,
 514                                        struct brw_reg index)
 515 {
 516    struct brw_reg header = brw_vec8_grf(0, 0);
 517    bool write_commit;
 518
 519    /* If the instruction is predicated, we'll predicate the send, not
 520     * the header setup.
 521     */
 522    brw_set_predicate_control(p, false);
 523
 524    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 525
 526    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 527                                      index);
 528
 529    brw_MOV(p,
 530            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 531            retype(src, BRW_REGISTER_TYPE_D));
 532
 533    uint32_t msg_type;
 534
 535    if (brw->gen >= 7)
 536       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 537    else if (brw->gen == 6)
 538       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 539    else
 540       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 541
 542    brw_set_predicate_control(p, inst->predicate);
 543
 544    /* Pre-gen6, we have to specify write commits to ensure ordering
 545     * between reads and writes within a thread.  Afterwards, that's
 546     * guaranteed and write commits only matter for inter-thread
 547     * synchronization.
 548     */
 549    if (brw->gen >= 6) {
 550       write_commit = false;
 551    } else {
 552       /* The visitor set up our destination register to be g0.  This
 553        * means that when the next read comes along, we will end up
 554        * reading from g0 and causing a block on the write commit.  For
 555        * write-after-read, we are relying on the value of the previous
 556        * read being used (and thus blocking on completion) before our
 557        * write is executed.  This means we have to be careful in
 558        * instruction scheduling to not violate this assumption.
 559        */
 560       write_commit = true;
 561    }
 562
 563    /* Each of the 8 channel enables is considered for whether each
 564     * dword is written.
 565     */
 566    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 567    brw_set_dest(p, send, dst);
 568    brw_set_src0(p, send, header);
 569    if (brw->gen < 6)
 570       send->header.destreg__conditionalmod = inst->base_mrf;
 571    brw_set_dp_write_message(p, send,
 572                             255, /* binding table index: stateless access */
 573                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 574                             msg_type,
 575                             3, /* mlen */
 576                             true, /* header present */
 577                             false, /* not a render target write */
 578                             write_commit, /* rlen */
 579                             false, /* eot */
 580                             write_commit);
 581 }
 582
 583 void
 584 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
 585                                             struct brw_reg dst,
 586                                             struct brw_reg index,
 587                                             struct brw_reg offset)
 588 {
 589    assert(brw->gen <= 7);
 590    assert(index.file == BRW_IMMEDIATE_VALUE &&
 591           index.type == BRW_REGISTER_TYPE_UD);
 592    uint32_t surf_index = index.dw1.ud;
 593
 594    struct brw_reg header = brw_vec8_grf(0, 0);
 595
 596    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 597
 598    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 599            offset);
 600
 601    uint32_t msg_type;
 602
 603    if (brw->gen >= 6)
 604       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 605    else if (brw->gen == 5 || brw->is_g4x)
 606       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 607    else
 608       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 609
 610    /* Each of the 8 channel enables is considered for whether each
 611     * dword is written.
 612     */
 613    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 614    brw_set_dest(p, send, dst);
 615    brw_set_src0(p, send, header);
 616    if (brw->gen < 6)
 617       send->header.destreg__conditionalmod = inst->base_mrf;
 618    brw_set_dp_read_message(p, send,
 619                            surf_index,
 620                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 621                            msg_type,
 622                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 623                            2, /* mlen */
 624                            true, /* header_present */
 625                            1 /* rlen */);
 626
 627    mark_surface_used(surf_index);
 628 }
 629
 630 void
 631 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
 632                                                  struct brw_reg dst,
 633                                                  struct brw_reg surf_index,
 634                                                  struct brw_reg offset)
 635 {
 636    assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
 637           surf_index.type == BRW_REGISTER_TYPE_UD);
 638
 639    brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
 640    brw_set_dest(p, insn, dst);
 641    brw_set_src0(p, insn, offset);
 642    brw_set_sampler_message(p, insn,
 643                            surf_index.dw1.ud,
 644                            0, /* LD message ignores sampler unit */
 645                            GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
 646                            1, /* rlen */
 647                            1, /* mlen */
 648                            false, /* no header */
 649                            BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 650                            0);
 651
 652    mark_surface_used(surf_index.dw1.ud);
 653 }
 654
 655 /**
 656  * Generate assembly for a Vec4 IR instruction.
 657  *
 658  * \param instruction The Vec4 IR instruction to generate code for.
 659  * \param dst         The destination register.
 660  * \param src         An array of up to three source registers.
 661  */
 662 void
 663 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 664                                           struct brw_reg dst,
 665                                           struct brw_reg *src)
 666 {
 667    vec4_instruction *inst = (vec4_instruction *) instruction;
 668
 669    switch (inst->opcode) {
 670    case BRW_OPCODE_MOV:
 671       brw_MOV(p, dst, src[0]);
 672       break;
 673    case BRW_OPCODE_ADD:
 674       brw_ADD(p, dst, src[0], src[1]);
 675       break;
 676    case BRW_OPCODE_MUL:
 677       brw_MUL(p, dst, src[0], src[1]);
 678       break;
 679    case BRW_OPCODE_MACH:
 680       brw_set_acc_write_control(p, 1);
 681       brw_MACH(p, dst, src[0], src[1]);
 682       brw_set_acc_write_control(p, 0);
 683       break;
 684
 685    case BRW_OPCODE_MAD:
 686       brw_MAD(p, dst, src[0], src[1], src[2]);
 687       break;
 688
 689    case BRW_OPCODE_FRC:
 690       brw_FRC(p, dst, src[0]);
 691       break;
 692    case BRW_OPCODE_RNDD:
 693       brw_RNDD(p, dst, src[0]);
 694       break;
 695    case BRW_OPCODE_RNDE:
 696       brw_RNDE(p, dst, src[0]);
 697       break;
 698    case BRW_OPCODE_RNDZ:
 699       brw_RNDZ(p, dst, src[0]);
 700       break;
 701
 702    case BRW_OPCODE_AND:
 703       brw_AND(p, dst, src[0], src[1]);
 704       break;
 705    case BRW_OPCODE_OR:
 706       brw_OR(p, dst, src[0], src[1]);
 707       break;
 708    case BRW_OPCODE_XOR:
 709       brw_XOR(p, dst, src[0], src[1]);
 710       break;
 711    case BRW_OPCODE_NOT:
 712       brw_NOT(p, dst, src[0]);
 713       break;
 714    case BRW_OPCODE_ASR:
 715       brw_ASR(p, dst, src[0], src[1]);
 716       break;
 717    case BRW_OPCODE_SHR:
 718       brw_SHR(p, dst, src[0], src[1]);
 719       break;
 720    case BRW_OPCODE_SHL:
 721       brw_SHL(p, dst, src[0], src[1]);
 722       break;
 723
 724    case BRW_OPCODE_CMP:
 725       brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 726       break;
 727    case BRW_OPCODE_SEL:
 728       brw_SEL(p, dst, src[0], src[1]);
 729       break;
 730
 731    case BRW_OPCODE_DPH:
 732       brw_DPH(p, dst, src[0], src[1]);
 733       break;
 734
 735    case BRW_OPCODE_DP4:
 736       brw_DP4(p, dst, src[0], src[1]);
 737       break;
 738
 739    case BRW_OPCODE_DP3:
 740       brw_DP3(p, dst, src[0], src[1]);
 741       break;
 742
 743    case BRW_OPCODE_DP2:
 744       brw_DP2(p, dst, src[0], src[1]);
 745       break;
 746
 747    case BRW_OPCODE_F32TO16:
 748       brw_F32TO16(p, dst, src[0]);
 749       break;
 750
 751    case BRW_OPCODE_F16TO32:
 752       brw_F16TO32(p, dst, src[0]);
 753       break;
 754
 755    case BRW_OPCODE_LRP:
 756       brw_LRP(p, dst, src[0], src[1], src[2]);
 757       break;
 758
 759    case BRW_OPCODE_BFREV:
 760       /* BFREV only supports UD type for src and dst. */
 761       brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
 762                    retype(src[0], BRW_REGISTER_TYPE_UD));
 763       break;
 764    case BRW_OPCODE_FBH:
 765       /* FBH only supports UD type for dst. */
 766       brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
 767       break;
 768    case BRW_OPCODE_FBL:
 769       /* FBL only supports UD type for dst. */
 770       brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
 771       break;
 772    case BRW_OPCODE_CBIT:
 773       /* CBIT only supports UD type for dst. */
 774       brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
 775       break;
 776
 777    case BRW_OPCODE_BFE:
 778       brw_BFE(p, dst, src[0], src[1], src[2]);
 779       break;
 780
 781    case BRW_OPCODE_BFI1:
 782       brw_BFI1(p, dst, src[0], src[1]);
 783       break;
 784    case BRW_OPCODE_BFI2:
 785       brw_BFI2(p, dst, src[0], src[1], src[2]);
 786       break;
 787
 788    case BRW_OPCODE_IF:
 789       if (inst->src[0].file != BAD_FILE) {
 790          /* The instruction has an embedded compare (only allowed on gen6) */
 791          assert(brw->gen == 6);
 792          gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 793       } else {
 794          struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 795          brw_inst->header.predicate_control = inst->predicate;
 796       }
 797       break;
 798
 799    case BRW_OPCODE_ELSE:
 800       brw_ELSE(p);
 801       break;
 802    case BRW_OPCODE_ENDIF:
 803       brw_ENDIF(p);
 804       break;
 805
 806    case BRW_OPCODE_DO:
 807       brw_DO(p, BRW_EXECUTE_8);
 808       break;
 809
 810    case BRW_OPCODE_BREAK:
 811       brw_BREAK(p);
 812       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 813       break;
 814    case BRW_OPCODE_CONTINUE:
 815       /* FINISHME: We need to write the loop instruction support still. */
 816       if (brw->gen >= 6)
 817          gen6_CONT(p);
 818       else
 819          brw_CONT(p);
 820       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 821       break;
 822
 823    case BRW_OPCODE_WHILE:
 824       brw_WHILE(p);
 825       break;
 826
 827    case SHADER_OPCODE_RCP:
 828    case SHADER_OPCODE_RSQ:
 829    case SHADER_OPCODE_SQRT:
 830    case SHADER_OPCODE_EXP2:
 831    case SHADER_OPCODE_LOG2:
 832    case SHADER_OPCODE_SIN:
 833    case SHADER_OPCODE_COS:
 834       if (brw->gen == 6) {
 835          generate_math1_gen6(inst, dst, src[0]);
 836       } else {
 837          /* Also works for Gen7. */
 838          generate_math1_gen4(inst, dst, src[0]);
 839       }
 840       break;
 841
 842    case SHADER_OPCODE_POW:
 843    case SHADER_OPCODE_INT_QUOTIENT:
 844    case SHADER_OPCODE_INT_REMAINDER:
 845       if (brw->gen >= 7) {
 846          generate_math2_gen7(inst, dst, src[0], src[1]);
 847       } else if (brw->gen == 6) {
 848          generate_math2_gen6(inst, dst, src[0], src[1]);
 849       } else {
 850          generate_math2_gen4(inst, dst, src[0], src[1]);
 851       }
 852       break;
 853
 854    case SHADER_OPCODE_TEX:
 855    case SHADER_OPCODE_TXD:
 856    case SHADER_OPCODE_TXF:
 857    case SHADER_OPCODE_TXF_MS:
 858    case SHADER_OPCODE_TXL:
 859    case SHADER_OPCODE_TXS:
 860       generate_tex(inst, dst, src[0]);
 861       break;
 862
 863    case VS_OPCODE_URB_WRITE:
 864       generate_urb_write(inst);
 865       break;
 866
 867    case VS_OPCODE_SCRATCH_READ:
 868       generate_scratch_read(inst, dst, src[0]);
 869       break;
 870
 871    case VS_OPCODE_SCRATCH_WRITE:
 872       generate_scratch_write(inst, dst, src[0], src[1]);
 873       break;
 874
 875    case VS_OPCODE_PULL_CONSTANT_LOAD:
 876       generate_pull_constant_load(inst, dst, src[0], src[1]);
 877       break;
 878
 879    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 880       generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
 881       break;
 882
 883    case SHADER_OPCODE_SHADER_TIME_ADD:
 884       brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
 885       mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
 886       break;
 887
 888    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 889       generate_unpack_flags(inst, dst);
 890       break;
 891
 892    default:
 893       if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
 894          _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
 895                        opcode_descs[inst->opcode].name);
 896       } else {
 897          _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
 898       }
 899       abort();
 900    }
 901 }
 902
 903 void
 904 vec4_generator::generate_code(exec_list *instructions)
 905 {
 906    int last_native_insn_offset = 0;
 907    const char *last_annotation_string = NULL;
 908    const void *last_annotation_ir = NULL;
 909
 910    if (unlikely(debug_flag)) {
 911       if (shader) {
 912          printf("Native code for vertex shader %d:\n", shader_prog->Name);
 913       } else {
 914          printf("Native code for vertex program %d:\n", prog->Id);
 915       }
 916    }
 917
 918    foreach_list(node, instructions) {
 919       vec4_instruction *inst = (vec4_instruction *)node;
 920       struct brw_reg src[3], dst;
 921
 922       if (unlikely(debug_flag)) {
 923          if (last_annotation_ir != inst->ir) {
 924             last_annotation_ir = inst->ir;
 925             if (last_annotation_ir) {
 926                printf("   ");
 927                if (shader) {
 928                   ((ir_instruction *) last_annotation_ir)->print();
 929                } else {
 930                   const prog_instruction *vpi;
 931                   vpi = (const prog_instruction *) inst->ir;
 932                   printf("%d: ", (int)(vpi - prog->Instructions));
 933                   _mesa_fprint_instruction_opt(stdout, vpi, 0,
 934                                                PROG_PRINT_DEBUG, NULL);
 935                }
 936                printf("\n");
 937             }
 938          }
 939          if (last_annotation_string != inst->annotation) {
 940             last_annotation_string = inst->annotation;
 941             if (last_annotation_string)
 942                printf("   %s\n", last_annotation_string);
 943          }
 944       }
 945
 946       for (unsigned int i = 0; i < 3; i++) {
 947          src[i] = inst->get_src(this->prog_data, i);
 948       }
 949       dst = inst->get_dst();
 950
 951       brw_set_conditionalmod(p, inst->conditional_mod);
 952       brw_set_predicate_control(p, inst->predicate);
 953       brw_set_predicate_inverse(p, inst->predicate_inverse);
 954       brw_set_saturate(p, inst->saturate);
 955       brw_set_mask_control(p, inst->force_writemask_all);
 956
 957       unsigned pre_emit_nr_insn = p->nr_insn;
 958
 959       generate_vec4_instruction(inst, dst, src);
 960
 961       if (inst->no_dd_clear || inst->no_dd_check) {
 962          assert(p->nr_insn == pre_emit_nr_insn + 1 ||
 963                 !"no_dd_check or no_dd_clear set for IR emitting more "
 964                 "than 1 instruction");
 965
 966          struct brw_instruction *last = &p->store[pre_emit_nr_insn];
 967
 968          if (inst->no_dd_clear)
 969             last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
 970          if (inst->no_dd_check)
 971             last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
 972       }
 973
 974       if (unlikely(debug_flag)) {
 975          brw_dump_compile(p, stdout,
 976                           last_native_insn_offset, p->next_insn_offset);
 977       }
 978
 979       last_native_insn_offset = p->next_insn_offset;
 980    }
 981
 982    if (unlikely(debug_flag)) {
 983       printf("\n");
 984    }
 985
 986    brw_set_uip_jip(p);
 987
 988    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 989     * emit issues, it doesn't get the jump distances into the output,
 990     * which is often something we want to debug.  So this is here in
 991     * case you're doing that.
 992     */
 993    if (0 && unlikely(debug_flag)) {
 994       brw_dump_compile(p, stdout, 0, p->next_insn_offset);
 995    }
 996 }
 997
 998 const unsigned *
 999 vec4_generator::generate_assembly(exec_list *instructions,
1000                                   unsigned *assembly_size)
1001 {
1002    brw_set_access_mode(p, BRW_ALIGN_16);
1003    generate_code(instructions);
1004    return brw_get_program(p, assembly_size);
1005 }
1006
1007 } /* namespace brw */