src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 #include "main/macros.h"
  29 #include "program/prog_print.h"
  30 #include "program/prog_parameter.h"
  31 };
  32
  33 using namespace brw;
  34
  35 namespace brw {
  36
  37 int
  38 vec4_visitor::setup_attributes(int payload_reg)
  39 {
  40    int nr_attributes;
  41    int attribute_map[VERT_ATTRIB_MAX + 1];
  42
  43    nr_attributes = 0;
  44    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  45       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  46          attribute_map[i] = payload_reg + nr_attributes;
  47          nr_attributes++;
  48       }
  49    }
  50
  51    /* VertexID is stored by the VF as the last vertex element, but we
  52     * don't represent it with a flag in inputs_read, so we call it
  53     * VERT_ATTRIB_MAX.
  54     */
  55    if (prog_data->uses_vertexid) {
  56       attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
  57       nr_attributes++;
  58    }
  59
  60    foreach_list(node, &this->instructions) {
  61       vec4_instruction *inst = (vec4_instruction *)node;
  62
  63       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  64       if (inst->dst.file == ATTR) {
  65          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  66
  67          struct brw_reg reg = brw_vec8_grf(grf, 0);
  68          reg.dw1.bits.writemask = inst->dst.writemask;
  69
  70          inst->dst.file = HW_REG;
  71          inst->dst.fixed_hw_reg = reg;
  72       }
  73
  74       for (int i = 0; i < 3; i++) {
  75          if (inst->src[i].file != ATTR)
  76             continue;
  77
  78          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  79
  80          struct brw_reg reg = brw_vec8_grf(grf, 0);
  81          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  82          reg.type = inst->src[i].type;
  83          if (inst->src[i].abs)
  84             reg = brw_abs(reg);
  85          if (inst->src[i].negate)
  86             reg = negate(reg);
  87
  88          inst->src[i].file = HW_REG;
  89          inst->src[i].fixed_hw_reg = reg;
  90       }
  91    }
  92
  93    /* The BSpec says we always have to read at least one thing from
  94     * the VF, and it appears that the hardware wedges otherwise.
  95     */
  96    if (nr_attributes == 0)
  97       nr_attributes = 1;
  98
  99    prog_data->urb_read_length = (nr_attributes + 1) / 2;
 100
 101    unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
 102
 103    if (intel->gen == 6)
 104       c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
 105    else
 106       c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
 107
 108    return payload_reg + nr_attributes;
 109 }
 110
 111 int
 112 vec4_visitor::setup_uniforms(int reg)
 113 {
 114    /* The pre-gen6 VS requires that some push constants get loaded no
 115     * matter what, or the GPU would hang.
 116     */
 117    if (intel->gen < 6 && this->uniforms == 0) {
 118       this->uniform_vector_size[this->uniforms] = 1;
 119
 120       for (unsigned int i = 0; i < 4; i++) {
 121          unsigned int slot = this->uniforms * 4 + i;
 122          static float zero = 0.0;
 123          c->prog_data.param[slot] = &zero;
 124       }
 125
 126       this->uniforms++;
 127       reg++;
 128    } else {
 129       reg += ALIGN(uniforms, 2) / 2;
 130    }
 131
 132    c->prog_data.nr_params = this->uniforms * 4;
 133
 134    c->prog_data.curb_read_length = reg - 1;
 135
 136    return reg;
 137 }
 138
 139 void
 140 vec4_visitor::setup_payload(void)
 141 {
 142    int reg = 0;
 143
 144    /* The payload always contains important data in g0, which contains
 145     * the URB handles that are passed on to the URB write at the end
 146     * of the thread.  So, we always start push constants at g1.
 147     */
 148    reg++;
 149
 150    reg = setup_uniforms(reg);
 151
 152    reg = setup_attributes(reg);
 153
 154    this->first_non_payload_grf = reg;
 155 }
 156
 157 struct brw_reg
 158 vec4_instruction::get_dst(void)
 159 {
 160    struct brw_reg brw_reg;
 161
 162    switch (dst.file) {
 163    case GRF:
 164       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 165       brw_reg = retype(brw_reg, dst.type);
 166       brw_reg.dw1.bits.writemask = dst.writemask;
 167       break;
 168
 169    case MRF:
 170       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 171       brw_reg = retype(brw_reg, dst.type);
 172       brw_reg.dw1.bits.writemask = dst.writemask;
 173       break;
 174
 175    case HW_REG:
 176       brw_reg = dst.fixed_hw_reg;
 177       break;
 178
 179    case BAD_FILE:
 180       brw_reg = brw_null_reg();
 181       break;
 182
 183    default:
 184       assert(!"not reached");
 185       brw_reg = brw_null_reg();
 186       break;
 187    }
 188    return brw_reg;
 189 }
 190
 191 struct brw_reg
 192 vec4_instruction::get_src(int i)
 193 {
 194    struct brw_reg brw_reg;
 195
 196    switch (src[i].file) {
 197    case GRF:
 198       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 199       brw_reg = retype(brw_reg, src[i].type);
 200       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 201       if (src[i].abs)
 202          brw_reg = brw_abs(brw_reg);
 203       if (src[i].negate)
 204          brw_reg = negate(brw_reg);
 205       break;
 206
 207    case IMM:
 208       switch (src[i].type) {
 209       case BRW_REGISTER_TYPE_F:
 210          brw_reg = brw_imm_f(src[i].imm.f);
 211          break;
 212       case BRW_REGISTER_TYPE_D:
 213          brw_reg = brw_imm_d(src[i].imm.i);
 214          break;
 215       case BRW_REGISTER_TYPE_UD:
 216          brw_reg = brw_imm_ud(src[i].imm.u);
 217          break;
 218       default:
 219          assert(!"not reached");
 220          brw_reg = brw_null_reg();
 221          break;
 222       }
 223       break;
 224
 225    case UNIFORM:
 226       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 227                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 228                        0, 4, 1);
 229       brw_reg = retype(brw_reg, src[i].type);
 230       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 231       if (src[i].abs)
 232          brw_reg = brw_abs(brw_reg);
 233       if (src[i].negate)
 234          brw_reg = negate(brw_reg);
 235
 236       /* This should have been moved to pull constants. */
 237       assert(!src[i].reladdr);
 238       break;
 239
 240    case HW_REG:
 241       brw_reg = src[i].fixed_hw_reg;
 242       break;
 243
 244    case BAD_FILE:
 245       /* Probably unused. */
 246       brw_reg = brw_null_reg();
 247       break;
 248    case ATTR:
 249    default:
 250       assert(!"not reached");
 251       brw_reg = brw_null_reg();
 252       break;
 253    }
 254
 255    return brw_reg;
 256 }
 257
 258 void
 259 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 260                                   struct brw_reg dst,
 261                                   struct brw_reg src)
 262 {
 263    brw_math(p,
 264             dst,
 265             brw_math_function(inst->opcode),
 266             inst->base_mrf,
 267             src,
 268             BRW_MATH_DATA_VECTOR,
 269             BRW_MATH_PRECISION_FULL);
 270 }
 271
 272 static void
 273 check_gen6_math_src_arg(struct brw_reg src)
 274 {
 275    /* Source swizzles are ignored. */
 276    assert(!src.abs);
 277    assert(!src.negate);
 278    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 279 }
 280
 281 void
 282 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 283                                   struct brw_reg dst,
 284                                   struct brw_reg src)
 285 {
 286    /* Can't do writemask because math can't be align16. */
 287    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 288    check_gen6_math_src_arg(src);
 289
 290    brw_set_access_mode(p, BRW_ALIGN_1);
 291    brw_math(p,
 292             dst,
 293             brw_math_function(inst->opcode),
 294             inst->base_mrf,
 295             src,
 296             BRW_MATH_DATA_SCALAR,
 297             BRW_MATH_PRECISION_FULL);
 298    brw_set_access_mode(p, BRW_ALIGN_16);
 299 }
 300
 301 void
 302 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 303                                   struct brw_reg dst,
 304                                   struct brw_reg src0,
 305                                   struct brw_reg src1)
 306 {
 307    brw_math2(p,
 308              dst,
 309              brw_math_function(inst->opcode),
 310              src0, src1);
 311 }
 312
 313 void
 314 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 315                                   struct brw_reg dst,
 316                                   struct brw_reg src0,
 317                                   struct brw_reg src1)
 318 {
 319    /* Can't do writemask because math can't be align16. */
 320    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 321    /* Source swizzles are ignored. */
 322    check_gen6_math_src_arg(src0);
 323    check_gen6_math_src_arg(src1);
 324
 325    brw_set_access_mode(p, BRW_ALIGN_1);
 326    brw_math2(p,
 327              dst,
 328              brw_math_function(inst->opcode),
 329              src0, src1);
 330    brw_set_access_mode(p, BRW_ALIGN_16);
 331 }
 332
 333 void
 334 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 335                                   struct brw_reg dst,
 336                                   struct brw_reg src0,
 337                                   struct brw_reg src1)
 338 {
 339    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 340     * "Message Payload":
 341     *
 342     * "Operand0[7].  For the INT DIV functions, this operand is the
 343     *  denominator."
 344     *  ...
 345     * "Operand1[7].  For the INT DIV functions, this operand is the
 346     *  numerator."
 347     */
 348    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 349    struct brw_reg &op0 = is_int_div ? src1 : src0;
 350    struct brw_reg &op1 = is_int_div ? src0 : src1;
 351
 352    brw_push_insn_state(p);
 353    brw_set_saturate(p, false);
 354    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 355    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 356    brw_pop_insn_state(p);
 357
 358    brw_math(p,
 359             dst,
 360             brw_math_function(inst->opcode),
 361             inst->base_mrf,
 362             op0,
 363             BRW_MATH_DATA_VECTOR,
 364             BRW_MATH_PRECISION_FULL);
 365 }
 366
 367 void
 368 vec4_visitor::generate_tex(vec4_instruction *inst,
 369                            struct brw_reg dst,
 370                            struct brw_reg src)
 371 {
 372    int msg_type = -1;
 373
 374    if (intel->gen >= 5) {
 375       switch (inst->opcode) {
 376       case SHADER_OPCODE_TEX:
 377       case SHADER_OPCODE_TXL:
 378          if (inst->shadow_compare) {
 379             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
 380          } else {
 381             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
 382          }
 383          break;
 384       case SHADER_OPCODE_TXD:
 385          /* There is no sample_d_c message; comparisons are done manually. */
 386          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
 387          break;
 388       case SHADER_OPCODE_TXF:
 389          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 390          break;
 391       case SHADER_OPCODE_TXS:
 392          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 393          break;
 394       default:
 395          assert(!"should not get here: invalid VS texture opcode");
 396          break;
 397       }
 398    } else {
 399       switch (inst->opcode) {
 400       case SHADER_OPCODE_TEX:
 401       case SHADER_OPCODE_TXL:
 402          if (inst->shadow_compare) {
 403             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
 404             assert(inst->mlen == 3);
 405          } else {
 406             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
 407             assert(inst->mlen == 2);
 408          }
 409          break;
 410       case SHADER_OPCODE_TXD:
 411          /* There is no sample_d_c message; comparisons are done manually. */
 412          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
 413          assert(inst->mlen == 4);
 414          break;
 415       case SHADER_OPCODE_TXF:
 416          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
 417          assert(inst->mlen == 2);
 418          break;
 419       case SHADER_OPCODE_TXS:
 420          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
 421          assert(inst->mlen == 2);
 422          break;
 423       default:
 424          assert(!"should not get here: invalid VS texture opcode");
 425          break;
 426       }
 427    }
 428
 429    assert(msg_type != -1);
 430
 431    /* Load the message header if present.  If there's a texture offset, we need
 432     * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 433     * use an implied move from g0 to the first message register.
 434     */
 435    if (inst->texture_offset) {
 436       /* Explicitly set up the message header by copying g0 to the MRF. */
 437       brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
 438                  retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 439
 440       /* Then set the offset bits in DWord 2. */
 441       brw_set_access_mode(p, BRW_ALIGN_1);
 442       brw_MOV(p,
 443               retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
 444                      BRW_REGISTER_TYPE_UD),
 445               brw_imm_uw(inst->texture_offset));
 446       brw_set_access_mode(p, BRW_ALIGN_16);
 447    } else if (inst->header_present) {
 448       /* Set up an implied move from g0 to the MRF. */
 449       src = brw_vec8_grf(0, 0);
 450    }
 451
 452    uint32_t return_format;
 453
 454    switch (dst.type) {
 455    case BRW_REGISTER_TYPE_D:
 456       return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
 457       break;
 458    case BRW_REGISTER_TYPE_UD:
 459       return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
 460       break;
 461    default:
 462       return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
 463       break;
 464    }
 465
 466    brw_SAMPLE(p,
 467               dst,
 468               inst->base_mrf,
 469               src,
 470               SURF_INDEX_VS_TEXTURE(inst->sampler),
 471               inst->sampler,
 472               WRITEMASK_XYZW,
 473               msg_type,
 474               1, /* response length */
 475               inst->mlen,
 476               inst->header_present,
 477               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 478               return_format);
 479 }
 480
 481 void
 482 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 483 {
 484    brw_urb_WRITE(p,
 485                  brw_null_reg(), /* dest */
 486                  inst->base_mrf, /* starting mrf reg nr */
 487                  brw_vec8_grf(0, 0), /* src */
 488                  false,         /* allocate */
 489                  true,          /* used */
 490                  inst->mlen,
 491                  0,             /* response len */
 492                  inst->eot,     /* eot */
 493                  inst->eot,     /* writes complete */
 494                  inst->offset,  /* urb destination offset */
 495                  BRW_URB_SWIZZLE_INTERLEAVE);
 496 }
 497
 498 void
 499 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 500                                                 struct brw_reg index)
 501 {
 502    int second_vertex_offset;
 503
 504    if (intel->gen >= 6)
 505       second_vertex_offset = 1;
 506    else
 507       second_vertex_offset = 16;
 508
 509    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 510
 511    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 512     * M1.4 are used, and the rest are ignored.
 513     */
 514    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 515    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 516    struct brw_reg index_0 = suboffset(vec1(index), 0);
 517    struct brw_reg index_4 = suboffset(vec1(index), 4);
 518
 519    brw_push_insn_state(p);
 520    brw_set_mask_control(p, BRW_MASK_DISABLE);
 521    brw_set_access_mode(p, BRW_ALIGN_1);
 522
 523    brw_MOV(p, m1_0, index_0);
 524
 525    if (index.file == BRW_IMMEDIATE_VALUE) {
 526       index_4.dw1.ud += second_vertex_offset;
 527       brw_MOV(p, m1_4, index_4);
 528    } else {
 529       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 530    }
 531
 532    brw_pop_insn_state(p);
 533 }
 534
 535 void
 536 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 537                                     struct brw_reg dst,
 538                                     struct brw_reg index)
 539 {
 540    struct brw_reg header = brw_vec8_grf(0, 0);
 541
 542    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 543
 544    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 545                                      index);
 546
 547    uint32_t msg_type;
 548
 549    if (intel->gen >= 6)
 550       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 551    else if (intel->gen == 5 || intel->is_g4x)
 552       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 553    else
 554       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 555
 556    /* Each of the 8 channel enables is considered for whether each
 557     * dword is written.
 558     */
 559    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 560    brw_set_dest(p, send, dst);
 561    brw_set_src0(p, send, header);
 562    if (intel->gen < 6)
 563       send->header.destreg__conditionalmod = inst->base_mrf;
 564    brw_set_dp_read_message(p, send,
 565                            255, /* binding table index: stateless access */
 566                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 567                            msg_type,
 568                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 569                            2, /* mlen */
 570                            1 /* rlen */);
 571 }
 572
 573 void
 574 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 575                                      struct brw_reg dst,
 576                                      struct brw_reg src,
 577                                      struct brw_reg index)
 578 {
 579    struct brw_reg header = brw_vec8_grf(0, 0);
 580    bool write_commit;
 581
 582    /* If the instruction is predicated, we'll predicate the send, not
 583     * the header setup.
 584     */
 585    brw_set_predicate_control(p, false);
 586
 587    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 588
 589    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 590                                      index);
 591
 592    brw_MOV(p,
 593            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 594            retype(src, BRW_REGISTER_TYPE_D));
 595
 596    uint32_t msg_type;
 597
 598    if (intel->gen >= 7)
 599       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 600    else if (intel->gen == 6)
 601       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 602    else
 603       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 604
 605    brw_set_predicate_control(p, inst->predicate);
 606
 607    /* Pre-gen6, we have to specify write commits to ensure ordering
 608     * between reads and writes within a thread.  Afterwards, that's
 609     * guaranteed and write commits only matter for inter-thread
 610     * synchronization.
 611     */
 612    if (intel->gen >= 6) {
 613       write_commit = false;
 614    } else {
 615       /* The visitor set up our destination register to be g0.  This
 616        * means that when the next read comes along, we will end up
 617        * reading from g0 and causing a block on the write commit.  For
 618        * write-after-read, we are relying on the value of the previous
 619        * read being used (and thus blocking on completion) before our
 620        * write is executed.  This means we have to be careful in
 621        * instruction scheduling to not violate this assumption.
 622        */
 623       write_commit = true;
 624    }
 625
 626    /* Each of the 8 channel enables is considered for whether each
 627     * dword is written.
 628     */
 629    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 630    brw_set_dest(p, send, dst);
 631    brw_set_src0(p, send, header);
 632    if (intel->gen < 6)
 633       send->header.destreg__conditionalmod = inst->base_mrf;
 634    brw_set_dp_write_message(p, send,
 635                             255, /* binding table index: stateless access */
 636                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 637                             msg_type,
 638                             3, /* mlen */
 639                             true, /* header present */
 640                             false, /* not a render target write */
 641                             write_commit, /* rlen */
 642                             false, /* eot */
 643                             write_commit);
 644 }
 645
 646 void
 647 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 648                                           struct brw_reg dst,
 649                                           struct brw_reg index,
 650                                           struct brw_reg offset)
 651 {
 652    assert(index.file == BRW_IMMEDIATE_VALUE &&
 653           index.type == BRW_REGISTER_TYPE_UD);
 654    uint32_t surf_index = index.dw1.ud;
 655
 656    if (intel->gen == 7) {
 657       gen6_resolve_implied_move(p, &offset, inst->base_mrf);
 658       brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
 659       brw_set_dest(p, insn, dst);
 660       brw_set_src0(p, insn, offset);
 661       brw_set_sampler_message(p, insn,
 662                               surf_index,
 663                               0, /* LD message ignores sampler unit */
 664                               GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
 665                               1, /* rlen */
 666                               1, /* mlen */
 667                               false, /* no header */
 668                               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 669                               0);
 670       return;
 671    }
 672
 673    struct brw_reg header = brw_vec8_grf(0, 0);
 674
 675    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 676
 677    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 678            offset);
 679
 680    uint32_t msg_type;
 681
 682    if (intel->gen >= 6)
 683       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 684    else if (intel->gen == 5 || intel->is_g4x)
 685       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 686    else
 687       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 688
 689    /* Each of the 8 channel enables is considered for whether each
 690     * dword is written.
 691     */
 692    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 693    brw_set_dest(p, send, dst);
 694    brw_set_src0(p, send, header);
 695    if (intel->gen < 6)
 696       send->header.destreg__conditionalmod = inst->base_mrf;
 697    brw_set_dp_read_message(p, send,
 698                            surf_index,
 699                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 700                            msg_type,
 701                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 702                            2, /* mlen */
 703                            1 /* rlen */);
 704 }
 705
 706 void
 707 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 708                                       struct brw_reg dst,
 709                                       struct brw_reg *src)
 710 {
 711    vec4_instruction *inst = (vec4_instruction *)instruction;
 712
 713    switch (inst->opcode) {
 714    case SHADER_OPCODE_RCP:
 715    case SHADER_OPCODE_RSQ:
 716    case SHADER_OPCODE_SQRT:
 717    case SHADER_OPCODE_EXP2:
 718    case SHADER_OPCODE_LOG2:
 719    case SHADER_OPCODE_SIN:
 720    case SHADER_OPCODE_COS:
 721       if (intel->gen == 6) {
 722          generate_math1_gen6(inst, dst, src[0]);
 723       } else {
 724          /* Also works for Gen7. */
 725          generate_math1_gen4(inst, dst, src[0]);
 726       }
 727       break;
 728
 729    case SHADER_OPCODE_POW:
 730    case SHADER_OPCODE_INT_QUOTIENT:
 731    case SHADER_OPCODE_INT_REMAINDER:
 732       if (intel->gen >= 7) {
 733          generate_math2_gen7(inst, dst, src[0], src[1]);
 734       } else if (intel->gen == 6) {
 735          generate_math2_gen6(inst, dst, src[0], src[1]);
 736       } else {
 737          generate_math2_gen4(inst, dst, src[0], src[1]);
 738       }
 739       break;
 740
 741    case SHADER_OPCODE_TEX:
 742    case SHADER_OPCODE_TXD:
 743    case SHADER_OPCODE_TXF:
 744    case SHADER_OPCODE_TXL:
 745    case SHADER_OPCODE_TXS:
 746       generate_tex(inst, dst, src[0]);
 747       break;
 748
 749    case VS_OPCODE_URB_WRITE:
 750       generate_urb_write(inst);
 751       break;
 752
 753    case VS_OPCODE_SCRATCH_READ:
 754       generate_scratch_read(inst, dst, src[0]);
 755       break;
 756
 757    case VS_OPCODE_SCRATCH_WRITE:
 758       generate_scratch_write(inst, dst, src[0], src[1]);
 759       break;
 760
 761    case VS_OPCODE_PULL_CONSTANT_LOAD:
 762       generate_pull_constant_load(inst, dst, src[0], src[1]);
 763       break;
 764
 765    default:
 766       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 767          fail("unsupported opcode in `%s' in VS\n",
 768               brw_opcodes[inst->opcode].name);
 769       } else {
 770          fail("Unsupported opcode %d in VS", inst->opcode);
 771       }
 772    }
 773 }
 774
 775 bool
 776 vec4_visitor::run()
 777 {
 778    /* Generate VS IR for main().  (the visitor only descends into
 779     * functions called "main").
 780     */
 781    if (shader) {
 782       visit_instructions(shader->ir);
 783    } else {
 784       emit_vertex_program_code();
 785    }
 786
 787    if (c->key.userclip_active && !c->key.uses_clip_distance)
 788       setup_uniform_clipplane_values();
 789
 790    emit_urb_writes();
 791
 792    /* Before any optimization, push array accesses out to scratch
 793     * space where we need them to be.  This pass may allocate new
 794     * virtual GRFs, so we want to do it early.  It also makes sure
 795     * that we have reladdr computations available for CSE, since we'll
 796     * often do repeated subexpressions for those.
 797     */
 798    if (shader) {
 799       move_grf_array_access_to_scratch();
 800       move_uniform_array_access_to_pull_constants();
 801    } else {
 802       /* The ARB_vertex_program frontend emits pull constant loads directly
 803        * rather than using reladdr, so we don't need to walk through all the
 804        * instructions looking for things to move.  There isn't anything.
 805        *
 806        * We do still need to split things to vec4 size.
 807        */
 808       split_uniform_registers();
 809    }
 810    pack_uniform_registers();
 811    move_push_constants_to_pull_constants();
 812    split_virtual_grfs();
 813
 814    bool progress;
 815    do {
 816       progress = false;
 817       progress = dead_code_eliminate() || progress;
 818       progress = opt_copy_propagation() || progress;
 819       progress = opt_algebraic() || progress;
 820       progress = opt_compute_to_mrf() || progress;
 821    } while (progress);
 822
 823
 824    if (failed)
 825       return false;
 826
 827    setup_payload();
 828
 829    if (false) {
 830       /* Debug of register spilling: Go spill everything. */
 831       const int grf_count = virtual_grf_count;
 832       float spill_costs[virtual_grf_count];
 833       bool no_spill[virtual_grf_count];
 834       evaluate_spill_costs(spill_costs, no_spill);
 835       for (int i = 0; i < grf_count; i++) {
 836          if (no_spill[i])
 837             continue;
 838          spill_reg(i);
 839       }
 840    }
 841
 842    while (!reg_allocate()) {
 843       if (failed)
 844          break;
 845    }
 846
 847    if (failed)
 848       return false;
 849
 850    brw_set_access_mode(p, BRW_ALIGN_16);
 851
 852    generate_code();
 853
 854    return !failed;
 855 }
 856
 857 void
 858 vec4_visitor::generate_code()
 859 {
 860    int last_native_insn_offset = 0;
 861    const char *last_annotation_string = NULL;
 862    const void *last_annotation_ir = NULL;
 863
 864    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 865       if (shader) {
 866          printf("Native code for vertex shader %d:\n", prog->Name);
 867       } else {
 868          printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
 869       }
 870    }
 871
 872    foreach_list(node, &this->instructions) {
 873       vec4_instruction *inst = (vec4_instruction *)node;
 874       struct brw_reg src[3], dst;
 875
 876       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 877          if (last_annotation_ir != inst->ir) {
 878             last_annotation_ir = inst->ir;
 879             if (last_annotation_ir) {
 880                printf("   ");
 881                if (shader) {
 882                   ((ir_instruction *) last_annotation_ir)->print();
 883                } else {
 884                   const prog_instruction *vpi;
 885                   vpi = (const prog_instruction *) inst->ir;
 886                   printf("%d: ", (int)(vpi - vp->Base.Instructions));
 887                   _mesa_fprint_instruction_opt(stdout, vpi, 0,
 888                                                PROG_PRINT_DEBUG, NULL);
 889                }
 890                printf("\n");
 891             }
 892          }
 893          if (last_annotation_string != inst->annotation) {
 894             last_annotation_string = inst->annotation;
 895             if (last_annotation_string)
 896                printf("   %s\n", last_annotation_string);
 897          }
 898       }
 899
 900       for (unsigned int i = 0; i < 3; i++) {
 901          src[i] = inst->get_src(i);
 902       }
 903       dst = inst->get_dst();
 904
 905       brw_set_conditionalmod(p, inst->conditional_mod);
 906       brw_set_predicate_control(p, inst->predicate);
 907       brw_set_predicate_inverse(p, inst->predicate_inverse);
 908       brw_set_saturate(p, inst->saturate);
 909
 910       switch (inst->opcode) {
 911       case BRW_OPCODE_MOV:
 912          brw_MOV(p, dst, src[0]);
 913          break;
 914       case BRW_OPCODE_ADD:
 915          brw_ADD(p, dst, src[0], src[1]);
 916          break;
 917       case BRW_OPCODE_MUL:
 918          brw_MUL(p, dst, src[0], src[1]);
 919          break;
 920       case BRW_OPCODE_MACH:
 921          brw_set_acc_write_control(p, 1);
 922          brw_MACH(p, dst, src[0], src[1]);
 923          brw_set_acc_write_control(p, 0);
 924          break;
 925
 926       case BRW_OPCODE_FRC:
 927          brw_FRC(p, dst, src[0]);
 928          break;
 929       case BRW_OPCODE_RNDD:
 930          brw_RNDD(p, dst, src[0]);
 931          break;
 932       case BRW_OPCODE_RNDE:
 933          brw_RNDE(p, dst, src[0]);
 934          break;
 935       case BRW_OPCODE_RNDZ:
 936          brw_RNDZ(p, dst, src[0]);
 937          break;
 938
 939       case BRW_OPCODE_AND:
 940          brw_AND(p, dst, src[0], src[1]);
 941          break;
 942       case BRW_OPCODE_OR:
 943          brw_OR(p, dst, src[0], src[1]);
 944          break;
 945       case BRW_OPCODE_XOR:
 946          brw_XOR(p, dst, src[0], src[1]);
 947          break;
 948       case BRW_OPCODE_NOT:
 949          brw_NOT(p, dst, src[0]);
 950          break;
 951       case BRW_OPCODE_ASR:
 952          brw_ASR(p, dst, src[0], src[1]);
 953          break;
 954       case BRW_OPCODE_SHR:
 955          brw_SHR(p, dst, src[0], src[1]);
 956          break;
 957       case BRW_OPCODE_SHL:
 958          brw_SHL(p, dst, src[0], src[1]);
 959          break;
 960
 961       case BRW_OPCODE_CMP:
 962          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 963          break;
 964       case BRW_OPCODE_SEL:
 965          brw_SEL(p, dst, src[0], src[1]);
 966          break;
 967
 968       case BRW_OPCODE_DPH:
 969          brw_DPH(p, dst, src[0], src[1]);
 970          break;
 971
 972       case BRW_OPCODE_DP4:
 973          brw_DP4(p, dst, src[0], src[1]);
 974          break;
 975
 976       case BRW_OPCODE_DP3:
 977          brw_DP3(p, dst, src[0], src[1]);
 978          break;
 979
 980       case BRW_OPCODE_DP2:
 981          brw_DP2(p, dst, src[0], src[1]);
 982          break;
 983
 984       case BRW_OPCODE_IF:
 985          if (inst->src[0].file != BAD_FILE) {
 986             /* The instruction has an embedded compare (only allowed on gen6) */
 987             assert(intel->gen == 6);
 988             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 989          } else {
 990             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 991             brw_inst->header.predicate_control = inst->predicate;
 992          }
 993          break;
 994
 995       case BRW_OPCODE_ELSE:
 996          brw_ELSE(p);
 997          break;
 998       case BRW_OPCODE_ENDIF:
 999          brw_ENDIF(p);
1000          break;
1001
1002       case BRW_OPCODE_DO:
1003          brw_DO(p, BRW_EXECUTE_8);
1004          break;
1005
1006       case BRW_OPCODE_BREAK:
1007          brw_BREAK(p);
1008          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1009          break;
1010       case BRW_OPCODE_CONTINUE:
1011          /* FINISHME: We need to write the loop instruction support still. */
1012          if (intel->gen >= 6)
1013             gen6_CONT(p);
1014          else
1015             brw_CONT(p);
1016          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1017          break;
1018
1019       case BRW_OPCODE_WHILE:
1020          brw_WHILE(p);
1021          break;
1022
1023       default:
1024          generate_vs_instruction(inst, dst, src);
1025          break;
1026       }
1027
1028       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1029          brw_dump_compile(p, stdout,
1030                           last_native_insn_offset, p->next_insn_offset);
1031       }
1032
1033       last_native_insn_offset = p->next_insn_offset;
1034    }
1035
1036    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1037       printf("\n");
1038    }
1039
1040    brw_set_uip_jip(p);
1041
1042    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1043     * emit issues, it doesn't get the jump distances into the output,
1044     * which is often something we want to debug.  So this is here in
1045     * case you're doing that.
1046     */
1047    if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
1048       brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1049    }
1050 }
1051
1052 extern "C" {
1053
1054 bool
1055 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
1056 {
1057    struct brw_context *brw = c->func.brw;
1058    struct intel_context *intel = &c->func.brw->intel;
1059    bool start_busy = false;
1060    float start_time = 0;
1061
1062    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
1063       start_busy = (intel->batch.last_bo &&
1064                     drm_intel_bo_busy(intel->batch.last_bo));
1065       start_time = get_time();
1066    }
1067
1068    struct brw_shader *shader = NULL;
1069    if (prog)
1070       shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1071
1072    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1073       if (shader) {
1074          printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1075          _mesa_print_ir(shader->ir, NULL);
1076          printf("\n\n");
1077       } else {
1078          printf("ARB_vertex_program %d for native vertex shader\n",
1079                 c->vp->program.Base.Id);
1080          _mesa_print_program(&c->vp->program.Base);
1081       }
1082    }
1083
1084    if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
1085       if (shader->compiled_once) {
1086          brw_vs_debug_recompile(brw, prog, &c->key);
1087       }
1088       if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
1089          perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1090                     (get_time() - start_time) * 1000);
1091       }
1092       shader->compiled_once = true;
1093    }
1094
1095    vec4_visitor v(c, prog, shader);
1096    if (!v.run()) {
1097       prog->LinkStatus = false;
1098       ralloc_strcat(&prog->InfoLog, v.fail_msg);
1099       return false;
1100    }
1101
1102    return true;
1103 }
1104
1105 } /* extern "C" */
1106
1107 } /* namespace brw */