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i965/vs: Plumb brw_vec4_prog_data into vec4_generator().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct gl_shader_program *shader_prog,
137 struct gl_program *prog,
138 struct brw_vec4_prog_data *prog_data,
139 void *mem_ctx,
140 bool debug_flag)
141 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
142 mem_ctx(mem_ctx), debug_flag(debug_flag)
143 {
144 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
156 struct brw_reg dst,
157 struct brw_reg src)
158 {
159 brw_math(p,
160 dst,
161 brw_math_function(inst->opcode),
162 inst->base_mrf,
163 src,
164 BRW_MATH_DATA_VECTOR,
165 BRW_MATH_PRECISION_FULL);
166 }
167
168 static void
169 check_gen6_math_src_arg(struct brw_reg src)
170 {
171 /* Source swizzles are ignored. */
172 assert(!src.abs);
173 assert(!src.negate);
174 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
175 }
176
177 void
178 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
179 struct brw_reg dst,
180 struct brw_reg src)
181 {
182 /* Can't do writemask because math can't be align16. */
183 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
184 check_gen6_math_src_arg(src);
185
186 brw_set_access_mode(p, BRW_ALIGN_1);
187 brw_math(p,
188 dst,
189 brw_math_function(inst->opcode),
190 inst->base_mrf,
191 src,
192 BRW_MATH_DATA_SCALAR,
193 BRW_MATH_PRECISION_FULL);
194 brw_set_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 brw_math2(p,
204 dst,
205 brw_math_function(inst->opcode),
206 src0, src1);
207 }
208
209 void
210 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
211 struct brw_reg dst,
212 struct brw_reg src0,
213 struct brw_reg src1)
214 {
215 /* Can't do writemask because math can't be align16. */
216 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
217 /* Source swizzles are ignored. */
218 check_gen6_math_src_arg(src0);
219 check_gen6_math_src_arg(src1);
220
221 brw_set_access_mode(p, BRW_ALIGN_1);
222 brw_math2(p,
223 dst,
224 brw_math_function(inst->opcode),
225 src0, src1);
226 brw_set_access_mode(p, BRW_ALIGN_16);
227 }
228
229 void
230 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
231 struct brw_reg dst,
232 struct brw_reg src0,
233 struct brw_reg src1)
234 {
235 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
236 * "Message Payload":
237 *
238 * "Operand0[7]. For the INT DIV functions, this operand is the
239 * denominator."
240 * ...
241 * "Operand1[7]. For the INT DIV functions, this operand is the
242 * numerator."
243 */
244 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
245 struct brw_reg &op0 = is_int_div ? src1 : src0;
246 struct brw_reg &op1 = is_int_div ? src0 : src1;
247
248 brw_push_insn_state(p);
249 brw_set_saturate(p, false);
250 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
251 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
252 brw_pop_insn_state(p);
253
254 brw_math(p,
255 dst,
256 brw_math_function(inst->opcode),
257 inst->base_mrf,
258 op0,
259 BRW_MATH_DATA_VECTOR,
260 BRW_MATH_PRECISION_FULL);
261 }
262
263 void
264 vec4_generator::generate_tex(vec4_instruction *inst,
265 struct brw_reg dst,
266 struct brw_reg src)
267 {
268 int msg_type = -1;
269
270 if (brw->gen >= 5) {
271 switch (inst->opcode) {
272 case SHADER_OPCODE_TEX:
273 case SHADER_OPCODE_TXL:
274 if (inst->shadow_compare) {
275 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
276 } else {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
278 }
279 break;
280 case SHADER_OPCODE_TXD:
281 if (inst->shadow_compare) {
282 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
283 assert(brw->is_haswell);
284 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
285 } else {
286 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
287 }
288 break;
289 case SHADER_OPCODE_TXF:
290 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
291 break;
292 case SHADER_OPCODE_TXF_MS:
293 if (brw->gen >= 7)
294 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
295 else
296 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
297 break;
298 case SHADER_OPCODE_TXS:
299 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
300 break;
301 default:
302 assert(!"should not get here: invalid VS texture opcode");
303 break;
304 }
305 } else {
306 switch (inst->opcode) {
307 case SHADER_OPCODE_TEX:
308 case SHADER_OPCODE_TXL:
309 if (inst->shadow_compare) {
310 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
311 assert(inst->mlen == 3);
312 } else {
313 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
314 assert(inst->mlen == 2);
315 }
316 break;
317 case SHADER_OPCODE_TXD:
318 /* There is no sample_d_c message; comparisons are done manually. */
319 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
320 assert(inst->mlen == 4);
321 break;
322 case SHADER_OPCODE_TXF:
323 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
324 assert(inst->mlen == 2);
325 break;
326 case SHADER_OPCODE_TXS:
327 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
328 assert(inst->mlen == 2);
329 break;
330 default:
331 assert(!"should not get here: invalid VS texture opcode");
332 break;
333 }
334 }
335
336 assert(msg_type != -1);
337
338 /* Load the message header if present. If there's a texture offset, we need
339 * to set it up explicitly and load the offset bitfield. Otherwise, we can
340 * use an implied move from g0 to the first message register.
341 */
342 if (inst->texture_offset) {
343 /* Explicitly set up the message header by copying g0 to the MRF. */
344 brw_push_insn_state(p);
345 brw_set_mask_control(p, BRW_MASK_DISABLE);
346 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
347 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
348
349 /* Then set the offset bits in DWord 2. */
350 brw_set_access_mode(p, BRW_ALIGN_1);
351 brw_MOV(p,
352 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
353 BRW_REGISTER_TYPE_UD),
354 brw_imm_uw(inst->texture_offset));
355 brw_pop_insn_state(p);
356 } else if (inst->header_present) {
357 /* Set up an implied move from g0 to the MRF. */
358 src = brw_vec8_grf(0, 0);
359 }
360
361 uint32_t return_format;
362
363 switch (dst.type) {
364 case BRW_REGISTER_TYPE_D:
365 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
366 break;
367 case BRW_REGISTER_TYPE_UD:
368 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
369 break;
370 default:
371 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
372 break;
373 }
374
375 brw_SAMPLE(p,
376 dst,
377 inst->base_mrf,
378 src,
379 SURF_INDEX_VS_TEXTURE(inst->sampler),
380 inst->sampler,
381 msg_type,
382 1, /* response length */
383 inst->mlen,
384 inst->header_present,
385 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
386 return_format);
387 }
388
389 void
390 vec4_generator::generate_urb_write(vec4_instruction *inst)
391 {
392 brw_urb_WRITE(p,
393 brw_null_reg(), /* dest */
394 inst->base_mrf, /* starting mrf reg nr */
395 brw_vec8_grf(0, 0), /* src */
396 false, /* allocate */
397 true, /* used */
398 inst->mlen,
399 0, /* response len */
400 inst->eot, /* eot */
401 inst->eot, /* writes complete */
402 inst->offset, /* urb destination offset */
403 BRW_URB_SWIZZLE_INTERLEAVE);
404 }
405
406 void
407 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
408 struct brw_reg index)
409 {
410 int second_vertex_offset;
411
412 if (brw->gen >= 6)
413 second_vertex_offset = 1;
414 else
415 second_vertex_offset = 16;
416
417 m1 = retype(m1, BRW_REGISTER_TYPE_D);
418
419 /* Set up M1 (message payload). Only the block offsets in M1.0 and
420 * M1.4 are used, and the rest are ignored.
421 */
422 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
423 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
424 struct brw_reg index_0 = suboffset(vec1(index), 0);
425 struct brw_reg index_4 = suboffset(vec1(index), 4);
426
427 brw_push_insn_state(p);
428 brw_set_mask_control(p, BRW_MASK_DISABLE);
429 brw_set_access_mode(p, BRW_ALIGN_1);
430
431 brw_MOV(p, m1_0, index_0);
432
433 if (index.file == BRW_IMMEDIATE_VALUE) {
434 index_4.dw1.ud += second_vertex_offset;
435 brw_MOV(p, m1_4, index_4);
436 } else {
437 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
438 }
439
440 brw_pop_insn_state(p);
441 }
442
443 void
444 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
445 struct brw_reg dst)
446 {
447 brw_push_insn_state(p);
448 brw_set_mask_control(p, BRW_MASK_DISABLE);
449 brw_set_access_mode(p, BRW_ALIGN_1);
450
451 struct brw_reg flags = brw_flag_reg(0, 0);
452 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
453 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
454
455 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
456 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
457 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
458
459 brw_pop_insn_state(p);
460 }
461
462 void
463 vec4_generator::generate_scratch_read(vec4_instruction *inst,
464 struct brw_reg dst,
465 struct brw_reg index)
466 {
467 struct brw_reg header = brw_vec8_grf(0, 0);
468
469 gen6_resolve_implied_move(p, &header, inst->base_mrf);
470
471 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
472 index);
473
474 uint32_t msg_type;
475
476 if (brw->gen >= 6)
477 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
478 else if (brw->gen == 5 || brw->is_g4x)
479 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
480 else
481 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
482
483 /* Each of the 8 channel enables is considered for whether each
484 * dword is written.
485 */
486 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
487 brw_set_dest(p, send, dst);
488 brw_set_src0(p, send, header);
489 if (brw->gen < 6)
490 send->header.destreg__conditionalmod = inst->base_mrf;
491 brw_set_dp_read_message(p, send,
492 255, /* binding table index: stateless access */
493 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
494 msg_type,
495 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
496 2, /* mlen */
497 true, /* header_present */
498 1 /* rlen */);
499 }
500
501 void
502 vec4_generator::generate_scratch_write(vec4_instruction *inst,
503 struct brw_reg dst,
504 struct brw_reg src,
505 struct brw_reg index)
506 {
507 struct brw_reg header = brw_vec8_grf(0, 0);
508 bool write_commit;
509
510 /* If the instruction is predicated, we'll predicate the send, not
511 * the header setup.
512 */
513 brw_set_predicate_control(p, false);
514
515 gen6_resolve_implied_move(p, &header, inst->base_mrf);
516
517 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
518 index);
519
520 brw_MOV(p,
521 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
522 retype(src, BRW_REGISTER_TYPE_D));
523
524 uint32_t msg_type;
525
526 if (brw->gen >= 7)
527 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
528 else if (brw->gen == 6)
529 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
530 else
531 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
532
533 brw_set_predicate_control(p, inst->predicate);
534
535 /* Pre-gen6, we have to specify write commits to ensure ordering
536 * between reads and writes within a thread. Afterwards, that's
537 * guaranteed and write commits only matter for inter-thread
538 * synchronization.
539 */
540 if (brw->gen >= 6) {
541 write_commit = false;
542 } else {
543 /* The visitor set up our destination register to be g0. This
544 * means that when the next read comes along, we will end up
545 * reading from g0 and causing a block on the write commit. For
546 * write-after-read, we are relying on the value of the previous
547 * read being used (and thus blocking on completion) before our
548 * write is executed. This means we have to be careful in
549 * instruction scheduling to not violate this assumption.
550 */
551 write_commit = true;
552 }
553
554 /* Each of the 8 channel enables is considered for whether each
555 * dword is written.
556 */
557 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
558 brw_set_dest(p, send, dst);
559 brw_set_src0(p, send, header);
560 if (brw->gen < 6)
561 send->header.destreg__conditionalmod = inst->base_mrf;
562 brw_set_dp_write_message(p, send,
563 255, /* binding table index: stateless access */
564 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
565 msg_type,
566 3, /* mlen */
567 true, /* header present */
568 false, /* not a render target write */
569 write_commit, /* rlen */
570 false, /* eot */
571 write_commit);
572 }
573
574 void
575 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
576 struct brw_reg dst,
577 struct brw_reg index,
578 struct brw_reg offset)
579 {
580 assert(brw->gen <= 7);
581 assert(index.file == BRW_IMMEDIATE_VALUE &&
582 index.type == BRW_REGISTER_TYPE_UD);
583 uint32_t surf_index = index.dw1.ud;
584
585 struct brw_reg header = brw_vec8_grf(0, 0);
586
587 gen6_resolve_implied_move(p, &header, inst->base_mrf);
588
589 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
590 offset);
591
592 uint32_t msg_type;
593
594 if (brw->gen >= 6)
595 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
596 else if (brw->gen == 5 || brw->is_g4x)
597 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
598 else
599 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
600
601 /* Each of the 8 channel enables is considered for whether each
602 * dword is written.
603 */
604 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
605 brw_set_dest(p, send, dst);
606 brw_set_src0(p, send, header);
607 if (brw->gen < 6)
608 send->header.destreg__conditionalmod = inst->base_mrf;
609 brw_set_dp_read_message(p, send,
610 surf_index,
611 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
612 msg_type,
613 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
614 2, /* mlen */
615 true, /* header_present */
616 1 /* rlen */);
617 }
618
619 void
620 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
621 struct brw_reg dst,
622 struct brw_reg surf_index,
623 struct brw_reg offset)
624 {
625 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
626 surf_index.type == BRW_REGISTER_TYPE_UD);
627
628 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
629 brw_set_dest(p, insn, dst);
630 brw_set_src0(p, insn, offset);
631 brw_set_sampler_message(p, insn,
632 surf_index.dw1.ud,
633 0, /* LD message ignores sampler unit */
634 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
635 1, /* rlen */
636 1, /* mlen */
637 false, /* no header */
638 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
639 0);
640 }
641
642 /**
643 * Generate assembly for a Vec4 IR instruction.
644 *
645 * \param instruction The Vec4 IR instruction to generate code for.
646 * \param dst The destination register.
647 * \param src An array of up to three source registers.
648 */
649 void
650 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
651 struct brw_reg dst,
652 struct brw_reg *src)
653 {
654 vec4_instruction *inst = (vec4_instruction *) instruction;
655
656 switch (inst->opcode) {
657 case BRW_OPCODE_MOV:
658 brw_MOV(p, dst, src[0]);
659 break;
660 case BRW_OPCODE_ADD:
661 brw_ADD(p, dst, src[0], src[1]);
662 break;
663 case BRW_OPCODE_MUL:
664 brw_MUL(p, dst, src[0], src[1]);
665 break;
666 case BRW_OPCODE_MACH:
667 brw_set_acc_write_control(p, 1);
668 brw_MACH(p, dst, src[0], src[1]);
669 brw_set_acc_write_control(p, 0);
670 break;
671
672 case BRW_OPCODE_MAD:
673 brw_MAD(p, dst, src[0], src[1], src[2]);
674 break;
675
676 case BRW_OPCODE_FRC:
677 brw_FRC(p, dst, src[0]);
678 break;
679 case BRW_OPCODE_RNDD:
680 brw_RNDD(p, dst, src[0]);
681 break;
682 case BRW_OPCODE_RNDE:
683 brw_RNDE(p, dst, src[0]);
684 break;
685 case BRW_OPCODE_RNDZ:
686 brw_RNDZ(p, dst, src[0]);
687 break;
688
689 case BRW_OPCODE_AND:
690 brw_AND(p, dst, src[0], src[1]);
691 break;
692 case BRW_OPCODE_OR:
693 brw_OR(p, dst, src[0], src[1]);
694 break;
695 case BRW_OPCODE_XOR:
696 brw_XOR(p, dst, src[0], src[1]);
697 break;
698 case BRW_OPCODE_NOT:
699 brw_NOT(p, dst, src[0]);
700 break;
701 case BRW_OPCODE_ASR:
702 brw_ASR(p, dst, src[0], src[1]);
703 break;
704 case BRW_OPCODE_SHR:
705 brw_SHR(p, dst, src[0], src[1]);
706 break;
707 case BRW_OPCODE_SHL:
708 brw_SHL(p, dst, src[0], src[1]);
709 break;
710
711 case BRW_OPCODE_CMP:
712 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
713 break;
714 case BRW_OPCODE_SEL:
715 brw_SEL(p, dst, src[0], src[1]);
716 break;
717
718 case BRW_OPCODE_DPH:
719 brw_DPH(p, dst, src[0], src[1]);
720 break;
721
722 case BRW_OPCODE_DP4:
723 brw_DP4(p, dst, src[0], src[1]);
724 break;
725
726 case BRW_OPCODE_DP3:
727 brw_DP3(p, dst, src[0], src[1]);
728 break;
729
730 case BRW_OPCODE_DP2:
731 brw_DP2(p, dst, src[0], src[1]);
732 break;
733
734 case BRW_OPCODE_F32TO16:
735 brw_F32TO16(p, dst, src[0]);
736 break;
737
738 case BRW_OPCODE_F16TO32:
739 brw_F16TO32(p, dst, src[0]);
740 break;
741
742 case BRW_OPCODE_LRP:
743 brw_LRP(p, dst, src[0], src[1], src[2]);
744 break;
745
746 case BRW_OPCODE_BFREV:
747 /* BFREV only supports UD type for src and dst. */
748 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
749 retype(src[0], BRW_REGISTER_TYPE_UD));
750 break;
751 case BRW_OPCODE_FBH:
752 /* FBH only supports UD type for dst. */
753 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
754 break;
755 case BRW_OPCODE_FBL:
756 /* FBL only supports UD type for dst. */
757 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
758 break;
759 case BRW_OPCODE_CBIT:
760 /* CBIT only supports UD type for dst. */
761 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
762 break;
763
764 case BRW_OPCODE_BFE:
765 brw_BFE(p, dst, src[0], src[1], src[2]);
766 break;
767
768 case BRW_OPCODE_BFI1:
769 brw_BFI1(p, dst, src[0], src[1]);
770 break;
771 case BRW_OPCODE_BFI2:
772 brw_BFI2(p, dst, src[0], src[1], src[2]);
773 break;
774
775 case BRW_OPCODE_IF:
776 if (inst->src[0].file != BAD_FILE) {
777 /* The instruction has an embedded compare (only allowed on gen6) */
778 assert(brw->gen == 6);
779 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
780 } else {
781 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
782 brw_inst->header.predicate_control = inst->predicate;
783 }
784 break;
785
786 case BRW_OPCODE_ELSE:
787 brw_ELSE(p);
788 break;
789 case BRW_OPCODE_ENDIF:
790 brw_ENDIF(p);
791 break;
792
793 case BRW_OPCODE_DO:
794 brw_DO(p, BRW_EXECUTE_8);
795 break;
796
797 case BRW_OPCODE_BREAK:
798 brw_BREAK(p);
799 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
800 break;
801 case BRW_OPCODE_CONTINUE:
802 /* FINISHME: We need to write the loop instruction support still. */
803 if (brw->gen >= 6)
804 gen6_CONT(p);
805 else
806 brw_CONT(p);
807 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
808 break;
809
810 case BRW_OPCODE_WHILE:
811 brw_WHILE(p);
812 break;
813
814 case SHADER_OPCODE_RCP:
815 case SHADER_OPCODE_RSQ:
816 case SHADER_OPCODE_SQRT:
817 case SHADER_OPCODE_EXP2:
818 case SHADER_OPCODE_LOG2:
819 case SHADER_OPCODE_SIN:
820 case SHADER_OPCODE_COS:
821 if (brw->gen == 6) {
822 generate_math1_gen6(inst, dst, src[0]);
823 } else {
824 /* Also works for Gen7. */
825 generate_math1_gen4(inst, dst, src[0]);
826 }
827 break;
828
829 case SHADER_OPCODE_POW:
830 case SHADER_OPCODE_INT_QUOTIENT:
831 case SHADER_OPCODE_INT_REMAINDER:
832 if (brw->gen >= 7) {
833 generate_math2_gen7(inst, dst, src[0], src[1]);
834 } else if (brw->gen == 6) {
835 generate_math2_gen6(inst, dst, src[0], src[1]);
836 } else {
837 generate_math2_gen4(inst, dst, src[0], src[1]);
838 }
839 break;
840
841 case SHADER_OPCODE_TEX:
842 case SHADER_OPCODE_TXD:
843 case SHADER_OPCODE_TXF:
844 case SHADER_OPCODE_TXF_MS:
845 case SHADER_OPCODE_TXL:
846 case SHADER_OPCODE_TXS:
847 generate_tex(inst, dst, src[0]);
848 break;
849
850 case VS_OPCODE_URB_WRITE:
851 generate_urb_write(inst);
852 break;
853
854 case VS_OPCODE_SCRATCH_READ:
855 generate_scratch_read(inst, dst, src[0]);
856 break;
857
858 case VS_OPCODE_SCRATCH_WRITE:
859 generate_scratch_write(inst, dst, src[0], src[1]);
860 break;
861
862 case VS_OPCODE_PULL_CONSTANT_LOAD:
863 generate_pull_constant_load(inst, dst, src[0], src[1]);
864 break;
865
866 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
867 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
868 break;
869
870 case SHADER_OPCODE_SHADER_TIME_ADD:
871 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
872 break;
873
874 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
875 generate_unpack_flags(inst, dst);
876 break;
877
878 default:
879 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
880 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
881 opcode_descs[inst->opcode].name);
882 } else {
883 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
884 }
885 abort();
886 }
887 }
888
889 void
890 vec4_generator::generate_code(exec_list *instructions)
891 {
892 int last_native_insn_offset = 0;
893 const char *last_annotation_string = NULL;
894 const void *last_annotation_ir = NULL;
895
896 if (unlikely(debug_flag)) {
897 if (shader) {
898 printf("Native code for vertex shader %d:\n", shader_prog->Name);
899 } else {
900 printf("Native code for vertex program %d:\n", prog->Id);
901 }
902 }
903
904 foreach_list(node, instructions) {
905 vec4_instruction *inst = (vec4_instruction *)node;
906 struct brw_reg src[3], dst;
907
908 if (unlikely(debug_flag)) {
909 if (last_annotation_ir != inst->ir) {
910 last_annotation_ir = inst->ir;
911 if (last_annotation_ir) {
912 printf(" ");
913 if (shader) {
914 ((ir_instruction *) last_annotation_ir)->print();
915 } else {
916 const prog_instruction *vpi;
917 vpi = (const prog_instruction *) inst->ir;
918 printf("%d: ", (int)(vpi - prog->Instructions));
919 _mesa_fprint_instruction_opt(stdout, vpi, 0,
920 PROG_PRINT_DEBUG, NULL);
921 }
922 printf("\n");
923 }
924 }
925 if (last_annotation_string != inst->annotation) {
926 last_annotation_string = inst->annotation;
927 if (last_annotation_string)
928 printf(" %s\n", last_annotation_string);
929 }
930 }
931
932 for (unsigned int i = 0; i < 3; i++) {
933 src[i] = inst->get_src(i);
934 }
935 dst = inst->get_dst();
936
937 brw_set_conditionalmod(p, inst->conditional_mod);
938 brw_set_predicate_control(p, inst->predicate);
939 brw_set_predicate_inverse(p, inst->predicate_inverse);
940 brw_set_saturate(p, inst->saturate);
941 brw_set_mask_control(p, inst->force_writemask_all);
942
943 unsigned pre_emit_nr_insn = p->nr_insn;
944
945 generate_vec4_instruction(inst, dst, src);
946
947 if (inst->no_dd_clear || inst->no_dd_check) {
948 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
949 !"no_dd_check or no_dd_clear set for IR emitting more "
950 "than 1 instruction");
951
952 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
953
954 if (inst->no_dd_clear)
955 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
956 if (inst->no_dd_check)
957 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
958 }
959
960 if (unlikely(debug_flag)) {
961 brw_dump_compile(p, stdout,
962 last_native_insn_offset, p->next_insn_offset);
963 }
964
965 last_native_insn_offset = p->next_insn_offset;
966 }
967
968 if (unlikely(debug_flag)) {
969 printf("\n");
970 }
971
972 brw_set_uip_jip(p);
973
974 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
975 * emit issues, it doesn't get the jump distances into the output,
976 * which is often something we want to debug. So this is here in
977 * case you're doing that.
978 */
979 if (0 && unlikely(debug_flag)) {
980 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
981 }
982 }
983
984 const unsigned *
985 vec4_generator::generate_assembly(exec_list *instructions,
986 unsigned *assembly_size)
987 {
988 brw_set_access_mode(p, BRW_ALIGN_16);
989 generate_code(instructions);
990 return brw_get_program(p, assembly_size);
991 }
992
993 } /* namespace brw */