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i965: Remove brw_set_predicate_inverse(p, true) from scratch offset code
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "glsl/ir_print_visitor.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 };
30
31 using namespace brw;
32
33 namespace brw {
34
35 int
36 vec4_visitor::setup_attributes(int payload_reg)
37 {
38 int nr_attributes;
39 int attribute_map[VERT_ATTRIB_MAX + 1];
40
41 nr_attributes = 0;
42 for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
43 if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
44 attribute_map[i] = payload_reg + nr_attributes;
45 nr_attributes++;
46 }
47 }
48
49 /* VertexID is stored by the VF as the last vertex element, but we
50 * don't represent it with a flag in inputs_read, so we call it
51 * VERT_ATTRIB_MAX.
52 */
53 if (prog_data->uses_vertexid) {
54 attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
55 nr_attributes++;
56 }
57
58 foreach_list(node, &this->instructions) {
59 vec4_instruction *inst = (vec4_instruction *)node;
60
61 /* We have to support ATTR as a destination for GL_FIXED fixup. */
62 if (inst->dst.file == ATTR) {
63 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
64
65 struct brw_reg reg = brw_vec8_grf(grf, 0);
66 reg.dw1.bits.writemask = inst->dst.writemask;
67
68 inst->dst.file = HW_REG;
69 inst->dst.fixed_hw_reg = reg;
70 }
71
72 for (int i = 0; i < 3; i++) {
73 if (inst->src[i].file != ATTR)
74 continue;
75
76 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
77
78 struct brw_reg reg = brw_vec8_grf(grf, 0);
79 reg.dw1.bits.swizzle = inst->src[i].swizzle;
80 reg.type = inst->src[i].type;
81 if (inst->src[i].abs)
82 reg = brw_abs(reg);
83 if (inst->src[i].negate)
84 reg = negate(reg);
85
86 inst->src[i].file = HW_REG;
87 inst->src[i].fixed_hw_reg = reg;
88 }
89 }
90
91 /* The BSpec says we always have to read at least one thing from
92 * the VF, and it appears that the hardware wedges otherwise.
93 */
94 if (nr_attributes == 0)
95 nr_attributes = 1;
96
97 prog_data->urb_read_length = (nr_attributes + 1) / 2;
98
99 unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
100
101 if (intel->gen == 6)
102 c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
103 else
104 c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
105
106 return payload_reg + nr_attributes;
107 }
108
109 int
110 vec4_visitor::setup_uniforms(int reg)
111 {
112 /* The pre-gen6 VS requires that some push constants get loaded no
113 * matter what, or the GPU would hang.
114 */
115 if (intel->gen < 6 && this->uniforms == 0) {
116 this->uniform_vector_size[this->uniforms] = 1;
117
118 for (unsigned int i = 0; i < 4; i++) {
119 unsigned int slot = this->uniforms * 4 + i;
120 static float zero = 0.0;
121 c->prog_data.param[slot] = &zero;
122 }
123
124 this->uniforms++;
125 reg++;
126 } else {
127 reg += ALIGN(uniforms, 2) / 2;
128 }
129
130 c->prog_data.nr_params = this->uniforms * 4;
131
132 c->prog_data.curb_read_length = reg - 1;
133 c->prog_data.uses_new_param_layout = true;
134
135 return reg;
136 }
137
138 void
139 vec4_visitor::setup_payload(void)
140 {
141 int reg = 0;
142
143 /* The payload always contains important data in g0, which contains
144 * the URB handles that are passed on to the URB write at the end
145 * of the thread. So, we always start push constants at g1.
146 */
147 reg++;
148
149 reg = setup_uniforms(reg);
150
151 reg = setup_attributes(reg);
152
153 this->first_non_payload_grf = reg;
154 }
155
156 struct brw_reg
157 vec4_instruction::get_dst(void)
158 {
159 struct brw_reg brw_reg;
160
161 switch (dst.file) {
162 case GRF:
163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
164 brw_reg = retype(brw_reg, dst.type);
165 brw_reg.dw1.bits.writemask = dst.writemask;
166 break;
167
168 case MRF:
169 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
170 brw_reg = retype(brw_reg, dst.type);
171 brw_reg.dw1.bits.writemask = dst.writemask;
172 break;
173
174 case HW_REG:
175 brw_reg = dst.fixed_hw_reg;
176 break;
177
178 case BAD_FILE:
179 brw_reg = brw_null_reg();
180 break;
181
182 default:
183 assert(!"not reached");
184 brw_reg = brw_null_reg();
185 break;
186 }
187 return brw_reg;
188 }
189
190 struct brw_reg
191 vec4_instruction::get_src(int i)
192 {
193 struct brw_reg brw_reg;
194
195 switch (src[i].file) {
196 case GRF:
197 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
198 brw_reg = retype(brw_reg, src[i].type);
199 brw_reg.dw1.bits.swizzle = src[i].swizzle;
200 if (src[i].abs)
201 brw_reg = brw_abs(brw_reg);
202 if (src[i].negate)
203 brw_reg = negate(brw_reg);
204 break;
205
206 case IMM:
207 switch (src[i].type) {
208 case BRW_REGISTER_TYPE_F:
209 brw_reg = brw_imm_f(src[i].imm.f);
210 break;
211 case BRW_REGISTER_TYPE_D:
212 brw_reg = brw_imm_d(src[i].imm.i);
213 break;
214 case BRW_REGISTER_TYPE_UD:
215 brw_reg = brw_imm_ud(src[i].imm.u);
216 break;
217 default:
218 assert(!"not reached");
219 brw_reg = brw_null_reg();
220 break;
221 }
222 break;
223
224 case UNIFORM:
225 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
226 ((src[i].reg + src[i].reg_offset) % 2) * 4),
227 0, 4, 1);
228 brw_reg = retype(brw_reg, src[i].type);
229 brw_reg.dw1.bits.swizzle = src[i].swizzle;
230 if (src[i].abs)
231 brw_reg = brw_abs(brw_reg);
232 if (src[i].negate)
233 brw_reg = negate(brw_reg);
234
235 /* This should have been moved to pull constants. */
236 assert(!src[i].reladdr);
237 break;
238
239 case HW_REG:
240 brw_reg = src[i].fixed_hw_reg;
241 break;
242
243 case BAD_FILE:
244 /* Probably unused. */
245 brw_reg = brw_null_reg();
246 break;
247 case ATTR:
248 default:
249 assert(!"not reached");
250 brw_reg = brw_null_reg();
251 break;
252 }
253
254 return brw_reg;
255 }
256
257 void
258 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
259 struct brw_reg dst,
260 struct brw_reg src)
261 {
262 brw_math(p,
263 dst,
264 brw_math_function(inst->opcode),
265 inst->base_mrf,
266 src,
267 BRW_MATH_DATA_VECTOR,
268 BRW_MATH_PRECISION_FULL);
269 }
270
271 static void
272 check_gen6_math_src_arg(struct brw_reg src)
273 {
274 /* Source swizzles are ignored. */
275 assert(!src.abs);
276 assert(!src.negate);
277 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
278 }
279
280 void
281 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
282 struct brw_reg dst,
283 struct brw_reg src)
284 {
285 /* Can't do writemask because math can't be align16. */
286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
287 check_gen6_math_src_arg(src);
288
289 brw_set_access_mode(p, BRW_ALIGN_1);
290 brw_math(p,
291 dst,
292 brw_math_function(inst->opcode),
293 inst->base_mrf,
294 src,
295 BRW_MATH_DATA_SCALAR,
296 BRW_MATH_PRECISION_FULL);
297 brw_set_access_mode(p, BRW_ALIGN_16);
298 }
299
300 void
301 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
302 struct brw_reg dst,
303 struct brw_reg src0,
304 struct brw_reg src1)
305 {
306 brw_math2(p,
307 dst,
308 brw_math_function(inst->opcode),
309 src0, src1);
310 }
311
312 void
313 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
314 struct brw_reg dst,
315 struct brw_reg src0,
316 struct brw_reg src1)
317 {
318 /* Can't do writemask because math can't be align16. */
319 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
320 /* Source swizzles are ignored. */
321 check_gen6_math_src_arg(src0);
322 check_gen6_math_src_arg(src1);
323
324 brw_set_access_mode(p, BRW_ALIGN_1);
325 brw_math2(p,
326 dst,
327 brw_math_function(inst->opcode),
328 src0, src1);
329 brw_set_access_mode(p, BRW_ALIGN_16);
330 }
331
332 void
333 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
334 struct brw_reg dst,
335 struct brw_reg src0,
336 struct brw_reg src1)
337 {
338 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
339 * "Message Payload":
340 *
341 * "Operand0[7]. For the INT DIV functions, this operand is the
342 * denominator."
343 * ...
344 * "Operand1[7]. For the INT DIV functions, this operand is the
345 * numerator."
346 */
347 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
348 struct brw_reg &op0 = is_int_div ? src1 : src0;
349 struct brw_reg &op1 = is_int_div ? src0 : src1;
350
351 brw_push_insn_state(p);
352 brw_set_saturate(p, false);
353 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
354 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
355 brw_pop_insn_state(p);
356
357 brw_math(p,
358 dst,
359 brw_math_function(inst->opcode),
360 inst->base_mrf,
361 op0,
362 BRW_MATH_DATA_VECTOR,
363 BRW_MATH_PRECISION_FULL);
364 }
365
366 void
367 vec4_visitor::generate_tex(vec4_instruction *inst,
368 struct brw_reg dst,
369 struct brw_reg src)
370 {
371 int msg_type = -1;
372
373 if (intel->gen >= 5) {
374 switch (inst->opcode) {
375 case SHADER_OPCODE_TEX:
376 case SHADER_OPCODE_TXL:
377 if (inst->shadow_compare) {
378 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
379 } else {
380 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
381 }
382 break;
383 case SHADER_OPCODE_TXD:
384 /* There is no sample_d_c message; comparisons are done manually. */
385 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
386 break;
387 case SHADER_OPCODE_TXF:
388 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
389 break;
390 case SHADER_OPCODE_TXS:
391 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
392 break;
393 default:
394 assert(!"should not get here: invalid VS texture opcode");
395 break;
396 }
397 } else {
398 switch (inst->opcode) {
399 case SHADER_OPCODE_TEX:
400 case SHADER_OPCODE_TXL:
401 if (inst->shadow_compare) {
402 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
403 assert(inst->mlen == 3);
404 } else {
405 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
406 assert(inst->mlen == 2);
407 }
408 break;
409 case SHADER_OPCODE_TXD:
410 /* There is no sample_d_c message; comparisons are done manually. */
411 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
412 assert(inst->mlen == 4);
413 break;
414 case SHADER_OPCODE_TXF:
415 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
416 assert(inst->mlen == 2);
417 break;
418 case SHADER_OPCODE_TXS:
419 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
420 assert(inst->mlen == 2);
421 break;
422 default:
423 assert(!"should not get here: invalid VS texture opcode");
424 break;
425 }
426 }
427
428 assert(msg_type != -1);
429
430 /* Load the message header if present. If there's a texture offset, we need
431 * to set it up explicitly and load the offset bitfield. Otherwise, we can
432 * use an implied move from g0 to the first message register.
433 */
434 if (inst->texture_offset) {
435 /* Explicitly set up the message header by copying g0 to the MRF. */
436 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
437 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
438
439 /* Then set the offset bits in DWord 2. */
440 brw_set_access_mode(p, BRW_ALIGN_1);
441 brw_MOV(p,
442 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
443 BRW_REGISTER_TYPE_UD),
444 brw_imm_uw(inst->texture_offset));
445 brw_set_access_mode(p, BRW_ALIGN_16);
446 } else if (inst->header_present) {
447 /* Set up an implied move from g0 to the MRF. */
448 src = brw_vec8_grf(0, 0);
449 }
450
451 uint32_t return_format;
452
453 switch (dst.type) {
454 case BRW_REGISTER_TYPE_D:
455 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
456 break;
457 case BRW_REGISTER_TYPE_UD:
458 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
459 break;
460 default:
461 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
462 break;
463 }
464
465 brw_SAMPLE(p,
466 dst,
467 inst->base_mrf,
468 src,
469 SURF_INDEX_VS_TEXTURE(inst->sampler),
470 inst->sampler,
471 WRITEMASK_XYZW,
472 msg_type,
473 1, /* response length */
474 inst->mlen,
475 inst->header_present,
476 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
477 return_format);
478 }
479
480 void
481 vec4_visitor::generate_urb_write(vec4_instruction *inst)
482 {
483 brw_urb_WRITE(p,
484 brw_null_reg(), /* dest */
485 inst->base_mrf, /* starting mrf reg nr */
486 brw_vec8_grf(0, 0), /* src */
487 false, /* allocate */
488 true, /* used */
489 inst->mlen,
490 0, /* response len */
491 inst->eot, /* eot */
492 inst->eot, /* writes complete */
493 inst->offset, /* urb destination offset */
494 BRW_URB_SWIZZLE_INTERLEAVE);
495 }
496
497 void
498 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
499 struct brw_reg index)
500 {
501 int second_vertex_offset;
502
503 if (intel->gen >= 6)
504 second_vertex_offset = 1;
505 else
506 second_vertex_offset = 16;
507
508 m1 = retype(m1, BRW_REGISTER_TYPE_D);
509
510 /* Set up M1 (message payload). Only the block offsets in M1.0 and
511 * M1.4 are used, and the rest are ignored.
512 */
513 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
514 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
515 struct brw_reg index_0 = suboffset(vec1(index), 0);
516 struct brw_reg index_4 = suboffset(vec1(index), 4);
517
518 brw_push_insn_state(p);
519 brw_set_mask_control(p, BRW_MASK_DISABLE);
520 brw_set_access_mode(p, BRW_ALIGN_1);
521
522 brw_MOV(p, m1_0, index_0);
523
524 if (index.file == BRW_IMMEDIATE_VALUE) {
525 index_4.dw1.ud += second_vertex_offset;
526 brw_MOV(p, m1_4, index_4);
527 } else {
528 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
529 }
530
531 brw_pop_insn_state(p);
532 }
533
534 void
535 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
536 struct brw_reg dst,
537 struct brw_reg index)
538 {
539 struct brw_reg header = brw_vec8_grf(0, 0);
540
541 gen6_resolve_implied_move(p, &header, inst->base_mrf);
542
543 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
544 index);
545
546 uint32_t msg_type;
547
548 if (intel->gen >= 6)
549 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
550 else if (intel->gen == 5 || intel->is_g4x)
551 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
552 else
553 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
554
555 /* Each of the 8 channel enables is considered for whether each
556 * dword is written.
557 */
558 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
559 brw_set_dest(p, send, dst);
560 brw_set_src0(p, send, header);
561 if (intel->gen < 6)
562 send->header.destreg__conditionalmod = inst->base_mrf;
563 brw_set_dp_read_message(p, send,
564 255, /* binding table index: stateless access */
565 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
566 msg_type,
567 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
568 2, /* mlen */
569 1 /* rlen */);
570 }
571
572 void
573 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
574 struct brw_reg dst,
575 struct brw_reg src,
576 struct brw_reg index)
577 {
578 struct brw_reg header = brw_vec8_grf(0, 0);
579 bool write_commit;
580
581 /* If the instruction is predicated, we'll predicate the send, not
582 * the header setup.
583 */
584 brw_set_predicate_control(p, false);
585
586 gen6_resolve_implied_move(p, &header, inst->base_mrf);
587
588 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
589 index);
590
591 brw_MOV(p,
592 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
593 retype(src, BRW_REGISTER_TYPE_D));
594
595 uint32_t msg_type;
596
597 if (intel->gen >= 7)
598 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
599 else if (intel->gen == 6)
600 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
601 else
602 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
603
604 brw_set_predicate_control(p, inst->predicate);
605
606 /* Pre-gen6, we have to specify write commits to ensure ordering
607 * between reads and writes within a thread. Afterwards, that's
608 * guaranteed and write commits only matter for inter-thread
609 * synchronization.
610 */
611 if (intel->gen >= 6) {
612 write_commit = false;
613 } else {
614 /* The visitor set up our destination register to be g0. This
615 * means that when the next read comes along, we will end up
616 * reading from g0 and causing a block on the write commit. For
617 * write-after-read, we are relying on the value of the previous
618 * read being used (and thus blocking on completion) before our
619 * write is executed. This means we have to be careful in
620 * instruction scheduling to not violate this assumption.
621 */
622 write_commit = true;
623 }
624
625 /* Each of the 8 channel enables is considered for whether each
626 * dword is written.
627 */
628 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
629 brw_set_dest(p, send, dst);
630 brw_set_src0(p, send, header);
631 if (intel->gen < 6)
632 send->header.destreg__conditionalmod = inst->base_mrf;
633 brw_set_dp_write_message(p, send,
634 255, /* binding table index: stateless access */
635 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
636 msg_type,
637 3, /* mlen */
638 true, /* header present */
639 false, /* not a render target write */
640 write_commit, /* rlen */
641 false, /* eot */
642 write_commit);
643 }
644
645 void
646 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
647 struct brw_reg dst,
648 struct brw_reg index,
649 struct brw_reg offset)
650 {
651 assert(index.file == BRW_IMMEDIATE_VALUE &&
652 index.type == BRW_REGISTER_TYPE_UD);
653 uint32_t surf_index = index.dw1.ud;
654
655 if (intel->gen == 7) {
656 gen6_resolve_implied_move(p, &offset, inst->base_mrf);
657 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
658 brw_set_dest(p, insn, dst);
659 brw_set_src0(p, insn, offset);
660 brw_set_sampler_message(p, insn,
661 surf_index,
662 0, /* LD message ignores sampler unit */
663 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
664 1, /* rlen */
665 1, /* mlen */
666 false, /* no header */
667 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
668 0);
669 return;
670 }
671
672 struct brw_reg header = brw_vec8_grf(0, 0);
673
674 gen6_resolve_implied_move(p, &header, inst->base_mrf);
675
676 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
677 offset);
678
679 uint32_t msg_type;
680
681 if (intel->gen >= 6)
682 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
683 else if (intel->gen == 5 || intel->is_g4x)
684 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
685 else
686 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
687
688 /* Each of the 8 channel enables is considered for whether each
689 * dword is written.
690 */
691 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
692 brw_set_dest(p, send, dst);
693 brw_set_src0(p, send, header);
694 if (intel->gen < 6)
695 send->header.destreg__conditionalmod = inst->base_mrf;
696 brw_set_dp_read_message(p, send,
697 surf_index,
698 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
699 msg_type,
700 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
701 2, /* mlen */
702 1 /* rlen */);
703 }
704
705 void
706 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
707 struct brw_reg dst,
708 struct brw_reg *src)
709 {
710 vec4_instruction *inst = (vec4_instruction *)instruction;
711
712 switch (inst->opcode) {
713 case SHADER_OPCODE_RCP:
714 case SHADER_OPCODE_RSQ:
715 case SHADER_OPCODE_SQRT:
716 case SHADER_OPCODE_EXP2:
717 case SHADER_OPCODE_LOG2:
718 case SHADER_OPCODE_SIN:
719 case SHADER_OPCODE_COS:
720 if (intel->gen == 6) {
721 generate_math1_gen6(inst, dst, src[0]);
722 } else {
723 /* Also works for Gen7. */
724 generate_math1_gen4(inst, dst, src[0]);
725 }
726 break;
727
728 case SHADER_OPCODE_POW:
729 case SHADER_OPCODE_INT_QUOTIENT:
730 case SHADER_OPCODE_INT_REMAINDER:
731 if (intel->gen >= 7) {
732 generate_math2_gen7(inst, dst, src[0], src[1]);
733 } else if (intel->gen == 6) {
734 generate_math2_gen6(inst, dst, src[0], src[1]);
735 } else {
736 generate_math2_gen4(inst, dst, src[0], src[1]);
737 }
738 break;
739
740 case SHADER_OPCODE_TEX:
741 case SHADER_OPCODE_TXD:
742 case SHADER_OPCODE_TXF:
743 case SHADER_OPCODE_TXL:
744 case SHADER_OPCODE_TXS:
745 generate_tex(inst, dst, src[0]);
746 break;
747
748 case VS_OPCODE_URB_WRITE:
749 generate_urb_write(inst);
750 break;
751
752 case VS_OPCODE_SCRATCH_READ:
753 generate_scratch_read(inst, dst, src[0]);
754 break;
755
756 case VS_OPCODE_SCRATCH_WRITE:
757 generate_scratch_write(inst, dst, src[0], src[1]);
758 break;
759
760 case VS_OPCODE_PULL_CONSTANT_LOAD:
761 generate_pull_constant_load(inst, dst, src[0], src[1]);
762 break;
763
764 default:
765 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
766 fail("unsupported opcode in `%s' in VS\n",
767 brw_opcodes[inst->opcode].name);
768 } else {
769 fail("Unsupported opcode %d in VS", inst->opcode);
770 }
771 }
772 }
773
774 bool
775 vec4_visitor::run()
776 {
777 if (c->key.userclip_active && !c->key.uses_clip_distance)
778 setup_uniform_clipplane_values();
779
780 /* Generate VS IR for main(). (the visitor only descends into
781 * functions called "main").
782 */
783 visit_instructions(shader->ir);
784
785 emit_urb_writes();
786
787 /* Before any optimization, push array accesses out to scratch
788 * space where we need them to be. This pass may allocate new
789 * virtual GRFs, so we want to do it early. It also makes sure
790 * that we have reladdr computations available for CSE, since we'll
791 * often do repeated subexpressions for those.
792 */
793 move_grf_array_access_to_scratch();
794 move_uniform_array_access_to_pull_constants();
795 pack_uniform_registers();
796 move_push_constants_to_pull_constants();
797
798 bool progress;
799 do {
800 progress = false;
801 progress = dead_code_eliminate() || progress;
802 progress = opt_copy_propagation() || progress;
803 progress = opt_algebraic() || progress;
804 progress = opt_compute_to_mrf() || progress;
805 } while (progress);
806
807
808 if (failed)
809 return false;
810
811 setup_payload();
812 reg_allocate();
813
814 if (failed)
815 return false;
816
817 brw_set_access_mode(p, BRW_ALIGN_16);
818
819 generate_code();
820
821 return !failed;
822 }
823
824 void
825 vec4_visitor::generate_code()
826 {
827 int last_native_insn_offset = 0;
828 const char *last_annotation_string = NULL;
829 ir_instruction *last_annotation_ir = NULL;
830
831 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
832 printf("Native code for vertex shader %d:\n", prog->Name);
833 }
834
835 foreach_list(node, &this->instructions) {
836 vec4_instruction *inst = (vec4_instruction *)node;
837 struct brw_reg src[3], dst;
838
839 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
840 if (last_annotation_ir != inst->ir) {
841 last_annotation_ir = inst->ir;
842 if (last_annotation_ir) {
843 printf(" ");
844 last_annotation_ir->print();
845 printf("\n");
846 }
847 }
848 if (last_annotation_string != inst->annotation) {
849 last_annotation_string = inst->annotation;
850 if (last_annotation_string)
851 printf(" %s\n", last_annotation_string);
852 }
853 }
854
855 for (unsigned int i = 0; i < 3; i++) {
856 src[i] = inst->get_src(i);
857 }
858 dst = inst->get_dst();
859
860 brw_set_conditionalmod(p, inst->conditional_mod);
861 brw_set_predicate_control(p, inst->predicate);
862 brw_set_predicate_inverse(p, inst->predicate_inverse);
863 brw_set_saturate(p, inst->saturate);
864
865 switch (inst->opcode) {
866 case BRW_OPCODE_MOV:
867 brw_MOV(p, dst, src[0]);
868 break;
869 case BRW_OPCODE_ADD:
870 brw_ADD(p, dst, src[0], src[1]);
871 break;
872 case BRW_OPCODE_MUL:
873 brw_MUL(p, dst, src[0], src[1]);
874 break;
875 case BRW_OPCODE_MACH:
876 brw_set_acc_write_control(p, 1);
877 brw_MACH(p, dst, src[0], src[1]);
878 brw_set_acc_write_control(p, 0);
879 break;
880
881 case BRW_OPCODE_FRC:
882 brw_FRC(p, dst, src[0]);
883 break;
884 case BRW_OPCODE_RNDD:
885 brw_RNDD(p, dst, src[0]);
886 break;
887 case BRW_OPCODE_RNDE:
888 brw_RNDE(p, dst, src[0]);
889 break;
890 case BRW_OPCODE_RNDZ:
891 brw_RNDZ(p, dst, src[0]);
892 break;
893
894 case BRW_OPCODE_AND:
895 brw_AND(p, dst, src[0], src[1]);
896 break;
897 case BRW_OPCODE_OR:
898 brw_OR(p, dst, src[0], src[1]);
899 break;
900 case BRW_OPCODE_XOR:
901 brw_XOR(p, dst, src[0], src[1]);
902 break;
903 case BRW_OPCODE_NOT:
904 brw_NOT(p, dst, src[0]);
905 break;
906 case BRW_OPCODE_ASR:
907 brw_ASR(p, dst, src[0], src[1]);
908 break;
909 case BRW_OPCODE_SHR:
910 brw_SHR(p, dst, src[0], src[1]);
911 break;
912 case BRW_OPCODE_SHL:
913 brw_SHL(p, dst, src[0], src[1]);
914 break;
915
916 case BRW_OPCODE_CMP:
917 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
918 break;
919 case BRW_OPCODE_SEL:
920 brw_SEL(p, dst, src[0], src[1]);
921 break;
922
923 case BRW_OPCODE_DP4:
924 brw_DP4(p, dst, src[0], src[1]);
925 break;
926
927 case BRW_OPCODE_DP3:
928 brw_DP3(p, dst, src[0], src[1]);
929 break;
930
931 case BRW_OPCODE_DP2:
932 brw_DP2(p, dst, src[0], src[1]);
933 break;
934
935 case BRW_OPCODE_IF:
936 if (inst->src[0].file != BAD_FILE) {
937 /* The instruction has an embedded compare (only allowed on gen6) */
938 assert(intel->gen == 6);
939 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
940 } else {
941 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
942 brw_inst->header.predicate_control = inst->predicate;
943 }
944 break;
945
946 case BRW_OPCODE_ELSE:
947 brw_ELSE(p);
948 break;
949 case BRW_OPCODE_ENDIF:
950 brw_ENDIF(p);
951 break;
952
953 case BRW_OPCODE_DO:
954 brw_DO(p, BRW_EXECUTE_8);
955 break;
956
957 case BRW_OPCODE_BREAK:
958 brw_BREAK(p);
959 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
960 break;
961 case BRW_OPCODE_CONTINUE:
962 /* FINISHME: We need to write the loop instruction support still. */
963 if (intel->gen >= 6)
964 gen6_CONT(p);
965 else
966 brw_CONT(p);
967 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
968 break;
969
970 case BRW_OPCODE_WHILE:
971 brw_WHILE(p);
972 break;
973
974 default:
975 generate_vs_instruction(inst, dst, src);
976 break;
977 }
978
979 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
980 brw_dump_compile(p, stdout,
981 last_native_insn_offset, p->next_insn_offset);
982 }
983
984 last_native_insn_offset = p->next_insn_offset;
985 }
986
987 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
988 printf("\n");
989 }
990
991 brw_set_uip_jip(p);
992
993 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
994 * emit issues, it doesn't get the jump distances into the output,
995 * which is often something we want to debug. So this is here in
996 * case you're doing that.
997 */
998 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
999 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1000 }
1001 }
1002
1003 extern "C" {
1004
1005 bool
1006 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
1007 {
1008 struct brw_context *brw = c->func.brw;
1009 struct intel_context *intel = &c->func.brw->intel;
1010 bool start_busy = false;
1011 float start_time = 0;
1012
1013 if (!prog)
1014 return false;
1015
1016 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
1017 start_busy = (intel->batch.last_bo &&
1018 drm_intel_bo_busy(intel->batch.last_bo));
1019 start_time = get_time();
1020 }
1021
1022 struct brw_shader *shader =
1023 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1024 if (!shader)
1025 return false;
1026
1027 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1028 printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1029 _mesa_print_ir(shader->ir, NULL);
1030 printf("\n\n");
1031 }
1032
1033 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
1034 if (shader->compiled_once) {
1035 brw_vs_debug_recompile(brw, prog, &c->key);
1036 }
1037 if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
1038 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1039 (get_time() - start_time) * 1000);
1040 }
1041 }
1042
1043 vec4_visitor v(c, prog, shader);
1044 if (!v.run()) {
1045 prog->LinkStatus = false;
1046 ralloc_strcat(&prog->InfoLog, v.fail_msg);
1047 return false;
1048 }
1049
1050 shader->compiled_once = true;
1051
1052 return true;
1053 }
1054
1055 } /* extern "C" */
1056
1057 } /* namespace brw */