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i965/gs: Add GS_OPCODE_SET_WRITE_OFFSET.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
104 (src[i].reg + src[i].reg_offset) / 2,
105 ((src[i].reg + src[i].reg_offset) % 2) * 4),
106 0, 4, 1);
107 brw_reg = retype(brw_reg, src[i].type);
108 brw_reg.dw1.bits.swizzle = src[i].swizzle;
109 if (src[i].abs)
110 brw_reg = brw_abs(brw_reg);
111 if (src[i].negate)
112 brw_reg = negate(brw_reg);
113
114 /* This should have been moved to pull constants. */
115 assert(!src[i].reladdr);
116 break;
117
118 case HW_REG:
119 brw_reg = src[i].fixed_hw_reg;
120 break;
121
122 case BAD_FILE:
123 /* Probably unused. */
124 brw_reg = brw_null_reg();
125 break;
126 case ATTR:
127 default:
128 assert(!"not reached");
129 brw_reg = brw_null_reg();
130 break;
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
146
147 p = rzalloc(mem_ctx, struct brw_compile);
148 brw_init_compile(brw, p, mem_ctx);
149 }
150
151 vec4_generator::~vec4_generator()
152 {
153 }
154
155 void
156 vec4_generator::mark_surface_used(unsigned surf_index)
157 {
158 assert(surf_index < BRW_MAX_VS_SURFACES);
159
160 prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
161 surf_index + 1);
162 }
163
164 void
165 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
166 struct brw_reg dst,
167 struct brw_reg src)
168 {
169 brw_math(p,
170 dst,
171 brw_math_function(inst->opcode),
172 inst->base_mrf,
173 src,
174 BRW_MATH_DATA_VECTOR,
175 BRW_MATH_PRECISION_FULL);
176 }
177
178 static void
179 check_gen6_math_src_arg(struct brw_reg src)
180 {
181 /* Source swizzles are ignored. */
182 assert(!src.abs);
183 assert(!src.negate);
184 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
185 }
186
187 void
188 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
189 struct brw_reg dst,
190 struct brw_reg src)
191 {
192 /* Can't do writemask because math can't be align16. */
193 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
194 check_gen6_math_src_arg(src);
195
196 brw_set_access_mode(p, BRW_ALIGN_1);
197 brw_math(p,
198 dst,
199 brw_math_function(inst->opcode),
200 inst->base_mrf,
201 src,
202 BRW_MATH_DATA_SCALAR,
203 BRW_MATH_PRECISION_FULL);
204 brw_set_access_mode(p, BRW_ALIGN_16);
205 }
206
207 void
208 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
209 struct brw_reg dst,
210 struct brw_reg src0,
211 struct brw_reg src1)
212 {
213 brw_math2(p,
214 dst,
215 brw_math_function(inst->opcode),
216 src0, src1);
217 }
218
219 void
220 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
221 struct brw_reg dst,
222 struct brw_reg src0,
223 struct brw_reg src1)
224 {
225 /* Can't do writemask because math can't be align16. */
226 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0);
229 check_gen6_math_src_arg(src1);
230
231 brw_set_access_mode(p, BRW_ALIGN_1);
232 brw_math2(p,
233 dst,
234 brw_math_function(inst->opcode),
235 src0, src1);
236 brw_set_access_mode(p, BRW_ALIGN_16);
237 }
238
239 void
240 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
241 struct brw_reg dst,
242 struct brw_reg src0,
243 struct brw_reg src1)
244 {
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
246 * "Message Payload":
247 *
248 * "Operand0[7]. For the INT DIV functions, this operand is the
249 * denominator."
250 * ...
251 * "Operand1[7]. For the INT DIV functions, this operand is the
252 * numerator."
253 */
254 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
255 struct brw_reg &op0 = is_int_div ? src1 : src0;
256 struct brw_reg &op1 = is_int_div ? src0 : src1;
257
258 brw_push_insn_state(p);
259 brw_set_saturate(p, false);
260 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
262 brw_pop_insn_state(p);
263
264 brw_math(p,
265 dst,
266 brw_math_function(inst->opcode),
267 inst->base_mrf,
268 op0,
269 BRW_MATH_DATA_VECTOR,
270 BRW_MATH_PRECISION_FULL);
271 }
272
273 void
274 vec4_generator::generate_tex(vec4_instruction *inst,
275 struct brw_reg dst,
276 struct brw_reg src)
277 {
278 int msg_type = -1;
279
280 if (brw->gen >= 5) {
281 switch (inst->opcode) {
282 case SHADER_OPCODE_TEX:
283 case SHADER_OPCODE_TXL:
284 if (inst->shadow_compare) {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
286 } else {
287 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
288 }
289 break;
290 case SHADER_OPCODE_TXD:
291 if (inst->shadow_compare) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw->is_haswell);
294 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
295 } else {
296 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
297 }
298 break;
299 case SHADER_OPCODE_TXF:
300 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
301 break;
302 case SHADER_OPCODE_TXF_MS:
303 if (brw->gen >= 7)
304 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
305 else
306 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
307 break;
308 case SHADER_OPCODE_TXS:
309 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
310 break;
311 default:
312 assert(!"should not get here: invalid VS texture opcode");
313 break;
314 }
315 } else {
316 switch (inst->opcode) {
317 case SHADER_OPCODE_TEX:
318 case SHADER_OPCODE_TXL:
319 if (inst->shadow_compare) {
320 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
321 assert(inst->mlen == 3);
322 } else {
323 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
324 assert(inst->mlen == 2);
325 }
326 break;
327 case SHADER_OPCODE_TXD:
328 /* There is no sample_d_c message; comparisons are done manually. */
329 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
330 assert(inst->mlen == 4);
331 break;
332 case SHADER_OPCODE_TXF:
333 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
334 assert(inst->mlen == 2);
335 break;
336 case SHADER_OPCODE_TXS:
337 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
338 assert(inst->mlen == 2);
339 break;
340 default:
341 assert(!"should not get here: invalid VS texture opcode");
342 break;
343 }
344 }
345
346 assert(msg_type != -1);
347
348 /* Load the message header if present. If there's a texture offset, we need
349 * to set it up explicitly and load the offset bitfield. Otherwise, we can
350 * use an implied move from g0 to the first message register.
351 */
352 if (inst->texture_offset) {
353 /* Explicitly set up the message header by copying g0 to the MRF. */
354 brw_push_insn_state(p);
355 brw_set_mask_control(p, BRW_MASK_DISABLE);
356 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
358
359 /* Then set the offset bits in DWord 2. */
360 brw_set_access_mode(p, BRW_ALIGN_1);
361 brw_MOV(p,
362 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
363 BRW_REGISTER_TYPE_UD),
364 brw_imm_uw(inst->texture_offset));
365 brw_pop_insn_state(p);
366 } else if (inst->header_present) {
367 /* Set up an implied move from g0 to the MRF. */
368 src = brw_vec8_grf(0, 0);
369 }
370
371 uint32_t return_format;
372
373 switch (dst.type) {
374 case BRW_REGISTER_TYPE_D:
375 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
376 break;
377 case BRW_REGISTER_TYPE_UD:
378 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
379 break;
380 default:
381 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
382 break;
383 }
384
385 brw_SAMPLE(p,
386 dst,
387 inst->base_mrf,
388 src,
389 SURF_INDEX_VS_TEXTURE(inst->sampler),
390 inst->sampler,
391 msg_type,
392 1, /* response length */
393 inst->mlen,
394 inst->header_present,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
396 return_format);
397
398 mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
399 }
400
401 void
402 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
403 {
404 brw_urb_WRITE(p,
405 brw_null_reg(), /* dest */
406 inst->base_mrf, /* starting mrf reg nr */
407 brw_vec8_grf(0, 0), /* src */
408 inst->urb_write_flags,
409 inst->mlen,
410 0, /* response len */
411 inst->offset, /* urb destination offset */
412 BRW_URB_SWIZZLE_INTERLEAVE);
413 }
414
415 void
416 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
417 {
418 struct brw_reg src = brw_message_reg(inst->base_mrf);
419 brw_urb_WRITE(p,
420 brw_null_reg(), /* dest */
421 inst->base_mrf, /* starting mrf reg nr */
422 src,
423 inst->urb_write_flags,
424 inst->mlen,
425 0, /* response len */
426 inst->offset, /* urb destination offset */
427 BRW_URB_SWIZZLE_INTERLEAVE);
428 }
429
430 void
431 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
432 {
433 struct brw_reg src = brw_message_reg(inst->base_mrf);
434 brw_urb_WRITE(p,
435 brw_null_reg(), /* dest */
436 inst->base_mrf, /* starting mrf reg nr */
437 src,
438 BRW_URB_WRITE_EOT,
439 1, /* message len */
440 0, /* response len */
441 0, /* urb destination offset */
442 BRW_URB_SWIZZLE_INTERLEAVE);
443 }
444
445 void
446 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
447 struct brw_reg src0,
448 struct brw_reg src1)
449 {
450 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
451 * Header: M0.3):
452 *
453 * Slot 0 Offset. This field, after adding to the Global Offset field
454 * in the message descriptor, specifies the offset (in 256-bit units)
455 * from the start of the URB entry, as referenced by URB Handle 0, at
456 * which the data will be accessed.
457 *
458 * Similar text describes DWORD M0.4, which is slot 1 offset.
459 *
460 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
461 * of the register for geometry shader invocations 0 and 1) by the
462 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
463 *
464 * We can do this with the following EU instruction:
465 *
466 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
467 */
468 brw_push_insn_state(p);
469 brw_set_access_mode(p, BRW_ALIGN_1);
470 brw_set_mask_control(p, BRW_MASK_DISABLE);
471 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
472 src1);
473 brw_set_access_mode(p, BRW_ALIGN_16);
474 brw_pop_insn_state(p);
475 }
476
477 void
478 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
479 struct brw_reg index)
480 {
481 int second_vertex_offset;
482
483 if (brw->gen >= 6)
484 second_vertex_offset = 1;
485 else
486 second_vertex_offset = 16;
487
488 m1 = retype(m1, BRW_REGISTER_TYPE_D);
489
490 /* Set up M1 (message payload). Only the block offsets in M1.0 and
491 * M1.4 are used, and the rest are ignored.
492 */
493 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
494 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
495 struct brw_reg index_0 = suboffset(vec1(index), 0);
496 struct brw_reg index_4 = suboffset(vec1(index), 4);
497
498 brw_push_insn_state(p);
499 brw_set_mask_control(p, BRW_MASK_DISABLE);
500 brw_set_access_mode(p, BRW_ALIGN_1);
501
502 brw_MOV(p, m1_0, index_0);
503
504 if (index.file == BRW_IMMEDIATE_VALUE) {
505 index_4.dw1.ud += second_vertex_offset;
506 brw_MOV(p, m1_4, index_4);
507 } else {
508 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
509 }
510
511 brw_pop_insn_state(p);
512 }
513
514 void
515 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
516 struct brw_reg dst)
517 {
518 brw_push_insn_state(p);
519 brw_set_mask_control(p, BRW_MASK_DISABLE);
520 brw_set_access_mode(p, BRW_ALIGN_1);
521
522 struct brw_reg flags = brw_flag_reg(0, 0);
523 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
524 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
525
526 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
527 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
528 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
529
530 brw_pop_insn_state(p);
531 }
532
533 void
534 vec4_generator::generate_scratch_read(vec4_instruction *inst,
535 struct brw_reg dst,
536 struct brw_reg index)
537 {
538 struct brw_reg header = brw_vec8_grf(0, 0);
539
540 gen6_resolve_implied_move(p, &header, inst->base_mrf);
541
542 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
543 index);
544
545 uint32_t msg_type;
546
547 if (brw->gen >= 6)
548 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
549 else if (brw->gen == 5 || brw->is_g4x)
550 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
551 else
552 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
553
554 /* Each of the 8 channel enables is considered for whether each
555 * dword is written.
556 */
557 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
558 brw_set_dest(p, send, dst);
559 brw_set_src0(p, send, header);
560 if (brw->gen < 6)
561 send->header.destreg__conditionalmod = inst->base_mrf;
562 brw_set_dp_read_message(p, send,
563 255, /* binding table index: stateless access */
564 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
565 msg_type,
566 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
567 2, /* mlen */
568 true, /* header_present */
569 1 /* rlen */);
570 }
571
572 void
573 vec4_generator::generate_scratch_write(vec4_instruction *inst,
574 struct brw_reg dst,
575 struct brw_reg src,
576 struct brw_reg index)
577 {
578 struct brw_reg header = brw_vec8_grf(0, 0);
579 bool write_commit;
580
581 /* If the instruction is predicated, we'll predicate the send, not
582 * the header setup.
583 */
584 brw_set_predicate_control(p, false);
585
586 gen6_resolve_implied_move(p, &header, inst->base_mrf);
587
588 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
589 index);
590
591 brw_MOV(p,
592 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
593 retype(src, BRW_REGISTER_TYPE_D));
594
595 uint32_t msg_type;
596
597 if (brw->gen >= 7)
598 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
599 else if (brw->gen == 6)
600 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
601 else
602 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
603
604 brw_set_predicate_control(p, inst->predicate);
605
606 /* Pre-gen6, we have to specify write commits to ensure ordering
607 * between reads and writes within a thread. Afterwards, that's
608 * guaranteed and write commits only matter for inter-thread
609 * synchronization.
610 */
611 if (brw->gen >= 6) {
612 write_commit = false;
613 } else {
614 /* The visitor set up our destination register to be g0. This
615 * means that when the next read comes along, we will end up
616 * reading from g0 and causing a block on the write commit. For
617 * write-after-read, we are relying on the value of the previous
618 * read being used (and thus blocking on completion) before our
619 * write is executed. This means we have to be careful in
620 * instruction scheduling to not violate this assumption.
621 */
622 write_commit = true;
623 }
624
625 /* Each of the 8 channel enables is considered for whether each
626 * dword is written.
627 */
628 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
629 brw_set_dest(p, send, dst);
630 brw_set_src0(p, send, header);
631 if (brw->gen < 6)
632 send->header.destreg__conditionalmod = inst->base_mrf;
633 brw_set_dp_write_message(p, send,
634 255, /* binding table index: stateless access */
635 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
636 msg_type,
637 3, /* mlen */
638 true, /* header present */
639 false, /* not a render target write */
640 write_commit, /* rlen */
641 false, /* eot */
642 write_commit);
643 }
644
645 void
646 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
647 struct brw_reg dst,
648 struct brw_reg index,
649 struct brw_reg offset)
650 {
651 assert(brw->gen <= 7);
652 assert(index.file == BRW_IMMEDIATE_VALUE &&
653 index.type == BRW_REGISTER_TYPE_UD);
654 uint32_t surf_index = index.dw1.ud;
655
656 struct brw_reg header = brw_vec8_grf(0, 0);
657
658 gen6_resolve_implied_move(p, &header, inst->base_mrf);
659
660 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
661 offset);
662
663 uint32_t msg_type;
664
665 if (brw->gen >= 6)
666 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
667 else if (brw->gen == 5 || brw->is_g4x)
668 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
669 else
670 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
671
672 /* Each of the 8 channel enables is considered for whether each
673 * dword is written.
674 */
675 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
676 brw_set_dest(p, send, dst);
677 brw_set_src0(p, send, header);
678 if (brw->gen < 6)
679 send->header.destreg__conditionalmod = inst->base_mrf;
680 brw_set_dp_read_message(p, send,
681 surf_index,
682 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
683 msg_type,
684 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
685 2, /* mlen */
686 true, /* header_present */
687 1 /* rlen */);
688
689 mark_surface_used(surf_index);
690 }
691
692 void
693 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
694 struct brw_reg dst,
695 struct brw_reg surf_index,
696 struct brw_reg offset)
697 {
698 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
699 surf_index.type == BRW_REGISTER_TYPE_UD);
700
701 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
702 brw_set_dest(p, insn, dst);
703 brw_set_src0(p, insn, offset);
704 brw_set_sampler_message(p, insn,
705 surf_index.dw1.ud,
706 0, /* LD message ignores sampler unit */
707 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
708 1, /* rlen */
709 1, /* mlen */
710 false, /* no header */
711 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
712 0);
713
714 mark_surface_used(surf_index.dw1.ud);
715 }
716
717 /**
718 * Generate assembly for a Vec4 IR instruction.
719 *
720 * \param instruction The Vec4 IR instruction to generate code for.
721 * \param dst The destination register.
722 * \param src An array of up to three source registers.
723 */
724 void
725 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
726 struct brw_reg dst,
727 struct brw_reg *src)
728 {
729 vec4_instruction *inst = (vec4_instruction *) instruction;
730
731 switch (inst->opcode) {
732 case BRW_OPCODE_MOV:
733 brw_MOV(p, dst, src[0]);
734 break;
735 case BRW_OPCODE_ADD:
736 brw_ADD(p, dst, src[0], src[1]);
737 break;
738 case BRW_OPCODE_MUL:
739 brw_MUL(p, dst, src[0], src[1]);
740 break;
741 case BRW_OPCODE_MACH:
742 brw_set_acc_write_control(p, 1);
743 brw_MACH(p, dst, src[0], src[1]);
744 brw_set_acc_write_control(p, 0);
745 break;
746
747 case BRW_OPCODE_MAD:
748 brw_MAD(p, dst, src[0], src[1], src[2]);
749 break;
750
751 case BRW_OPCODE_FRC:
752 brw_FRC(p, dst, src[0]);
753 break;
754 case BRW_OPCODE_RNDD:
755 brw_RNDD(p, dst, src[0]);
756 break;
757 case BRW_OPCODE_RNDE:
758 brw_RNDE(p, dst, src[0]);
759 break;
760 case BRW_OPCODE_RNDZ:
761 brw_RNDZ(p, dst, src[0]);
762 break;
763
764 case BRW_OPCODE_AND:
765 brw_AND(p, dst, src[0], src[1]);
766 break;
767 case BRW_OPCODE_OR:
768 brw_OR(p, dst, src[0], src[1]);
769 break;
770 case BRW_OPCODE_XOR:
771 brw_XOR(p, dst, src[0], src[1]);
772 break;
773 case BRW_OPCODE_NOT:
774 brw_NOT(p, dst, src[0]);
775 break;
776 case BRW_OPCODE_ASR:
777 brw_ASR(p, dst, src[0], src[1]);
778 break;
779 case BRW_OPCODE_SHR:
780 brw_SHR(p, dst, src[0], src[1]);
781 break;
782 case BRW_OPCODE_SHL:
783 brw_SHL(p, dst, src[0], src[1]);
784 break;
785
786 case BRW_OPCODE_CMP:
787 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
788 break;
789 case BRW_OPCODE_SEL:
790 brw_SEL(p, dst, src[0], src[1]);
791 break;
792
793 case BRW_OPCODE_DPH:
794 brw_DPH(p, dst, src[0], src[1]);
795 break;
796
797 case BRW_OPCODE_DP4:
798 brw_DP4(p, dst, src[0], src[1]);
799 break;
800
801 case BRW_OPCODE_DP3:
802 brw_DP3(p, dst, src[0], src[1]);
803 break;
804
805 case BRW_OPCODE_DP2:
806 brw_DP2(p, dst, src[0], src[1]);
807 break;
808
809 case BRW_OPCODE_F32TO16:
810 brw_F32TO16(p, dst, src[0]);
811 break;
812
813 case BRW_OPCODE_F16TO32:
814 brw_F16TO32(p, dst, src[0]);
815 break;
816
817 case BRW_OPCODE_LRP:
818 brw_LRP(p, dst, src[0], src[1], src[2]);
819 break;
820
821 case BRW_OPCODE_BFREV:
822 /* BFREV only supports UD type for src and dst. */
823 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
824 retype(src[0], BRW_REGISTER_TYPE_UD));
825 break;
826 case BRW_OPCODE_FBH:
827 /* FBH only supports UD type for dst. */
828 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
829 break;
830 case BRW_OPCODE_FBL:
831 /* FBL only supports UD type for dst. */
832 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
833 break;
834 case BRW_OPCODE_CBIT:
835 /* CBIT only supports UD type for dst. */
836 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
837 break;
838
839 case BRW_OPCODE_BFE:
840 brw_BFE(p, dst, src[0], src[1], src[2]);
841 break;
842
843 case BRW_OPCODE_BFI1:
844 brw_BFI1(p, dst, src[0], src[1]);
845 break;
846 case BRW_OPCODE_BFI2:
847 brw_BFI2(p, dst, src[0], src[1], src[2]);
848 break;
849
850 case BRW_OPCODE_IF:
851 if (inst->src[0].file != BAD_FILE) {
852 /* The instruction has an embedded compare (only allowed on gen6) */
853 assert(brw->gen == 6);
854 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
855 } else {
856 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
857 brw_inst->header.predicate_control = inst->predicate;
858 }
859 break;
860
861 case BRW_OPCODE_ELSE:
862 brw_ELSE(p);
863 break;
864 case BRW_OPCODE_ENDIF:
865 brw_ENDIF(p);
866 break;
867
868 case BRW_OPCODE_DO:
869 brw_DO(p, BRW_EXECUTE_8);
870 break;
871
872 case BRW_OPCODE_BREAK:
873 brw_BREAK(p);
874 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
875 break;
876 case BRW_OPCODE_CONTINUE:
877 /* FINISHME: We need to write the loop instruction support still. */
878 if (brw->gen >= 6)
879 gen6_CONT(p);
880 else
881 brw_CONT(p);
882 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
883 break;
884
885 case BRW_OPCODE_WHILE:
886 brw_WHILE(p);
887 break;
888
889 case SHADER_OPCODE_RCP:
890 case SHADER_OPCODE_RSQ:
891 case SHADER_OPCODE_SQRT:
892 case SHADER_OPCODE_EXP2:
893 case SHADER_OPCODE_LOG2:
894 case SHADER_OPCODE_SIN:
895 case SHADER_OPCODE_COS:
896 if (brw->gen == 6) {
897 generate_math1_gen6(inst, dst, src[0]);
898 } else {
899 /* Also works for Gen7. */
900 generate_math1_gen4(inst, dst, src[0]);
901 }
902 break;
903
904 case SHADER_OPCODE_POW:
905 case SHADER_OPCODE_INT_QUOTIENT:
906 case SHADER_OPCODE_INT_REMAINDER:
907 if (brw->gen >= 7) {
908 generate_math2_gen7(inst, dst, src[0], src[1]);
909 } else if (brw->gen == 6) {
910 generate_math2_gen6(inst, dst, src[0], src[1]);
911 } else {
912 generate_math2_gen4(inst, dst, src[0], src[1]);
913 }
914 break;
915
916 case SHADER_OPCODE_TEX:
917 case SHADER_OPCODE_TXD:
918 case SHADER_OPCODE_TXF:
919 case SHADER_OPCODE_TXF_MS:
920 case SHADER_OPCODE_TXL:
921 case SHADER_OPCODE_TXS:
922 generate_tex(inst, dst, src[0]);
923 break;
924
925 case VS_OPCODE_URB_WRITE:
926 generate_vs_urb_write(inst);
927 break;
928
929 case VS_OPCODE_SCRATCH_READ:
930 generate_scratch_read(inst, dst, src[0]);
931 break;
932
933 case VS_OPCODE_SCRATCH_WRITE:
934 generate_scratch_write(inst, dst, src[0], src[1]);
935 break;
936
937 case VS_OPCODE_PULL_CONSTANT_LOAD:
938 generate_pull_constant_load(inst, dst, src[0], src[1]);
939 break;
940
941 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
942 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
943 break;
944
945 case GS_OPCODE_URB_WRITE:
946 generate_gs_urb_write(inst);
947 break;
948
949 case GS_OPCODE_THREAD_END:
950 generate_gs_thread_end(inst);
951 break;
952
953 case GS_OPCODE_SET_WRITE_OFFSET:
954 generate_gs_set_write_offset(dst, src[0], src[1]);
955 break;
956
957 case SHADER_OPCODE_SHADER_TIME_ADD:
958 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
959 mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
960 break;
961
962 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
963 generate_unpack_flags(inst, dst);
964 break;
965
966 default:
967 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
968 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
969 opcode_descs[inst->opcode].name);
970 } else {
971 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
972 }
973 abort();
974 }
975 }
976
977 void
978 vec4_generator::generate_code(exec_list *instructions)
979 {
980 int last_native_insn_offset = 0;
981 const char *last_annotation_string = NULL;
982 const void *last_annotation_ir = NULL;
983
984 if (unlikely(debug_flag)) {
985 if (shader) {
986 printf("Native code for vertex shader %d:\n", shader_prog->Name);
987 } else {
988 printf("Native code for vertex program %d:\n", prog->Id);
989 }
990 }
991
992 foreach_list(node, instructions) {
993 vec4_instruction *inst = (vec4_instruction *)node;
994 struct brw_reg src[3], dst;
995
996 if (unlikely(debug_flag)) {
997 if (last_annotation_ir != inst->ir) {
998 last_annotation_ir = inst->ir;
999 if (last_annotation_ir) {
1000 printf(" ");
1001 if (shader) {
1002 ((ir_instruction *) last_annotation_ir)->print();
1003 } else {
1004 const prog_instruction *vpi;
1005 vpi = (const prog_instruction *) inst->ir;
1006 printf("%d: ", (int)(vpi - prog->Instructions));
1007 _mesa_fprint_instruction_opt(stdout, vpi, 0,
1008 PROG_PRINT_DEBUG, NULL);
1009 }
1010 printf("\n");
1011 }
1012 }
1013 if (last_annotation_string != inst->annotation) {
1014 last_annotation_string = inst->annotation;
1015 if (last_annotation_string)
1016 printf(" %s\n", last_annotation_string);
1017 }
1018 }
1019
1020 for (unsigned int i = 0; i < 3; i++) {
1021 src[i] = inst->get_src(this->prog_data, i);
1022 }
1023 dst = inst->get_dst();
1024
1025 brw_set_conditionalmod(p, inst->conditional_mod);
1026 brw_set_predicate_control(p, inst->predicate);
1027 brw_set_predicate_inverse(p, inst->predicate_inverse);
1028 brw_set_saturate(p, inst->saturate);
1029 brw_set_mask_control(p, inst->force_writemask_all);
1030
1031 unsigned pre_emit_nr_insn = p->nr_insn;
1032
1033 generate_vec4_instruction(inst, dst, src);
1034
1035 if (inst->no_dd_clear || inst->no_dd_check) {
1036 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1037 !"no_dd_check or no_dd_clear set for IR emitting more "
1038 "than 1 instruction");
1039
1040 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
1041
1042 if (inst->no_dd_clear)
1043 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
1044 if (inst->no_dd_check)
1045 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
1046 }
1047
1048 if (unlikely(debug_flag)) {
1049 brw_dump_compile(p, stdout,
1050 last_native_insn_offset, p->next_insn_offset);
1051 }
1052
1053 last_native_insn_offset = p->next_insn_offset;
1054 }
1055
1056 if (unlikely(debug_flag)) {
1057 printf("\n");
1058 }
1059
1060 brw_set_uip_jip(p);
1061
1062 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1063 * emit issues, it doesn't get the jump distances into the output,
1064 * which is often something we want to debug. So this is here in
1065 * case you're doing that.
1066 */
1067 if (0 && unlikely(debug_flag)) {
1068 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1069 }
1070 }
1071
1072 const unsigned *
1073 vec4_generator::generate_assembly(exec_list *instructions,
1074 unsigned *assembly_size)
1075 {
1076 brw_set_access_mode(p, BRW_ALIGN_16);
1077 generate_code(instructions);
1078 return brw_get_program(p, assembly_size);
1079 }
1080
1081 } /* namespace brw */