src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45       }
  46    }
  47
  48    foreach_list(node, &this->instructions) {
  49       vec4_instruction *inst = (vec4_instruction *)node;
  50
  51       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  52       if (inst->dst.file == ATTR) {
  53          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  54
  55          struct brw_reg reg = brw_vec8_grf(grf, 0);
  56          reg.dw1.bits.writemask = inst->dst.writemask;
  57
  58          inst->dst.file = HW_REG;
  59          inst->dst.fixed_hw_reg = reg;
  60       }
  61
  62       for (int i = 0; i < 3; i++) {
  63          if (inst->src[i].file != ATTR)
  64             continue;
  65
  66          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  67
  68          struct brw_reg reg = brw_vec8_grf(grf, 0);
  69          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  70          if (inst->src[i].abs)
  71             reg = brw_abs(reg);
  72          if (inst->src[i].negate)
  73             reg = negate(reg);
  74
  75          inst->src[i].file = HW_REG;
  76          inst->src[i].fixed_hw_reg = reg;
  77       }
  78    }
  79
  80    /* The BSpec says we always have to read at least one thing from
  81     * the VF, and it appears that the hardware wedges otherwise.
  82     */
  83    if (nr_attributes == 0)
  84       nr_attributes = 1;
  85
  86    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  87
  88    return payload_reg + nr_attributes;
  89 }
  90
  91 int
  92 vec4_visitor::setup_uniforms(int reg)
  93 {
  94    /* User clip planes from curbe:
  95     */
  96    if (c->key.nr_userclip && !c->key.uses_clip_distance) {
  97       if (intel->gen >= 6) {
  98          for (int i = 0; i < c->key.nr_userclip; i++) {
  99             c->userplane[i] = stride(brw_vec4_grf(reg + i / 2,
 100                                                   (i % 2) * 4), 0, 4, 1);
 101          }
 102          reg += ALIGN(c->key.nr_userclip, 2) / 2;
 103       } else {
 104          for (int i = 0; i < c->key.nr_userclip; i++) {
 105             c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2,
 106                                                   (i % 2) * 4), 0, 4, 1);
 107          }
 108          reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2;
 109       }
 110    }
 111
 112    /* The pre-gen6 VS requires that some push constants get loaded no
 113     * matter what, or the GPU would hang.
 114     */
 115    if (intel->gen < 6 && this->uniforms == 0) {
 116       this->uniform_vector_size[this->uniforms] = 1;
 117
 118       for (unsigned int i = 0; i < 4; i++) {
 119          unsigned int slot = this->uniforms * 4 + i;
 120          static float zero = 0.0;
 121          c->prog_data.param[slot] = &zero;
 122       }
 123
 124       this->uniforms++;
 125       reg++;
 126    } else {
 127       reg += ALIGN(uniforms, 2) / 2;
 128    }
 129
 130    c->prog_data.nr_params = this->uniforms * 4;
 131
 132    c->prog_data.curb_read_length = reg - 1;
 133    c->prog_data.uses_new_param_layout = true;
 134
 135    return reg;
 136 }
 137
 138 void
 139 vec4_visitor::setup_payload(void)
 140 {
 141    int reg = 0;
 142
 143    /* The payload always contains important data in g0, which contains
 144     * the URB handles that are passed on to the URB write at the end
 145     * of the thread.  So, we always start push constants at g1.
 146     */
 147    reg++;
 148
 149    reg = setup_uniforms(reg);
 150
 151    reg = setup_attributes(reg);
 152
 153    this->first_non_payload_grf = reg;
 154 }
 155
 156 struct brw_reg
 157 vec4_instruction::get_dst(void)
 158 {
 159    struct brw_reg brw_reg;
 160
 161    switch (dst.file) {
 162    case GRF:
 163       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 164       brw_reg = retype(brw_reg, dst.type);
 165       brw_reg.dw1.bits.writemask = dst.writemask;
 166       break;
 167
 168    case MRF:
 169       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 170       brw_reg = retype(brw_reg, dst.type);
 171       brw_reg.dw1.bits.writemask = dst.writemask;
 172       break;
 173
 174    case HW_REG:
 175       brw_reg = dst.fixed_hw_reg;
 176       break;
 177
 178    case BAD_FILE:
 179       brw_reg = brw_null_reg();
 180       break;
 181
 182    default:
 183       assert(!"not reached");
 184       brw_reg = brw_null_reg();
 185       break;
 186    }
 187    return brw_reg;
 188 }
 189
 190 struct brw_reg
 191 vec4_instruction::get_src(int i)
 192 {
 193    struct brw_reg brw_reg;
 194
 195    switch (src[i].file) {
 196    case GRF:
 197       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 198       brw_reg = retype(brw_reg, src[i].type);
 199       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 200       if (src[i].abs)
 201          brw_reg = brw_abs(brw_reg);
 202       if (src[i].negate)
 203          brw_reg = negate(brw_reg);
 204       break;
 205
 206    case IMM:
 207       switch (src[i].type) {
 208       case BRW_REGISTER_TYPE_F:
 209          brw_reg = brw_imm_f(src[i].imm.f);
 210          break;
 211       case BRW_REGISTER_TYPE_D:
 212          brw_reg = brw_imm_d(src[i].imm.i);
 213          break;
 214       case BRW_REGISTER_TYPE_UD:
 215          brw_reg = brw_imm_ud(src[i].imm.u);
 216          break;
 217       default:
 218          assert(!"not reached");
 219          brw_reg = brw_null_reg();
 220          break;
 221       }
 222       break;
 223
 224    case UNIFORM:
 225       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 226                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 227                        0, 4, 1);
 228       brw_reg = retype(brw_reg, src[i].type);
 229       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 230       if (src[i].abs)
 231          brw_reg = brw_abs(brw_reg);
 232       if (src[i].negate)
 233          brw_reg = negate(brw_reg);
 234
 235       /* This should have been moved to pull constants. */
 236       assert(!src[i].reladdr);
 237       break;
 238
 239    case HW_REG:
 240       brw_reg = src[i].fixed_hw_reg;
 241       break;
 242
 243    case BAD_FILE:
 244       /* Probably unused. */
 245       brw_reg = brw_null_reg();
 246       break;
 247    case ATTR:
 248    default:
 249       assert(!"not reached");
 250       brw_reg = brw_null_reg();
 251       break;
 252    }
 253
 254    return brw_reg;
 255 }
 256
 257 void
 258 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 259                                   struct brw_reg dst,
 260                                   struct brw_reg src)
 261 {
 262    brw_math(p,
 263             dst,
 264             brw_math_function(inst->opcode),
 265             BRW_MATH_SATURATE_NONE,
 266             inst->base_mrf,
 267             src,
 268             BRW_MATH_DATA_VECTOR,
 269             BRW_MATH_PRECISION_FULL);
 270 }
 271
 272 static void
 273 check_gen6_math_src_arg(struct brw_reg src)
 274 {
 275    /* Source swizzles are ignored. */
 276    assert(!src.abs);
 277    assert(!src.negate);
 278    assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
 279 }
 280
 281 void
 282 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 283                                   struct brw_reg dst,
 284                                   struct brw_reg src)
 285 {
 286    /* Can't do writemask because math can't be align16. */
 287    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 288    check_gen6_math_src_arg(src);
 289
 290    brw_set_access_mode(p, BRW_ALIGN_1);
 291    brw_math(p,
 292             dst,
 293             brw_math_function(inst->opcode),
 294             BRW_MATH_SATURATE_NONE,
 295             inst->base_mrf,
 296             src,
 297             BRW_MATH_DATA_SCALAR,
 298             BRW_MATH_PRECISION_FULL);
 299    brw_set_access_mode(p, BRW_ALIGN_16);
 300 }
 301
 302 void
 303 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 304                                   struct brw_reg dst,
 305                                   struct brw_reg src0,
 306                                   struct brw_reg src1)
 307 {
 308    /* Can't do writemask because math can't be align16. */
 309    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 310    /* Source swizzles are ignored. */
 311    check_gen6_math_src_arg(src0);
 312    check_gen6_math_src_arg(src1);
 313
 314    brw_set_access_mode(p, BRW_ALIGN_1);
 315    brw_math2(p,
 316              dst,
 317              brw_math_function(inst->opcode),
 318              src0, src1);
 319    brw_set_access_mode(p, BRW_ALIGN_16);
 320 }
 321
 322 void
 323 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 324                                   struct brw_reg dst,
 325                                   struct brw_reg src0,
 326                                   struct brw_reg src1)
 327 {
 328    brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
 329
 330    brw_math(p,
 331             dst,
 332             brw_math_function(inst->opcode),
 333             BRW_MATH_SATURATE_NONE,
 334             inst->base_mrf,
 335             src0,
 336             BRW_MATH_DATA_VECTOR,
 337             BRW_MATH_PRECISION_FULL);
 338 }
 339
 340 void
 341 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 342 {
 343    brw_urb_WRITE(p,
 344                  brw_null_reg(), /* dest */
 345                  inst->base_mrf, /* starting mrf reg nr */
 346                  brw_vec8_grf(0, 0), /* src */
 347                  false,         /* allocate */
 348                  true,          /* used */
 349                  inst->mlen,
 350                  0,             /* response len */
 351                  inst->eot,     /* eot */
 352                  inst->eot,     /* writes complete */
 353                  inst->offset,  /* urb destination offset */
 354                  BRW_URB_SWIZZLE_INTERLEAVE);
 355 }
 356
 357 void
 358 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 359                                                 struct brw_reg index)
 360 {
 361    int second_vertex_offset;
 362
 363    if (intel->gen >= 6)
 364       second_vertex_offset = 1;
 365    else
 366       second_vertex_offset = 16;
 367
 368    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 369
 370    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 371     * M1.4 are used, and the rest are ignored.
 372     */
 373    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 374    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 375    struct brw_reg index_0 = suboffset(vec1(index), 0);
 376    struct brw_reg index_4 = suboffset(vec1(index), 4);
 377
 378    brw_push_insn_state(p);
 379    brw_set_mask_control(p, BRW_MASK_DISABLE);
 380    brw_set_access_mode(p, BRW_ALIGN_1);
 381
 382    brw_MOV(p, m1_0, index_0);
 383
 384    brw_set_predicate_inverse(p, true);
 385    if (index.file == BRW_IMMEDIATE_VALUE) {
 386       index_4.dw1.ud += second_vertex_offset;
 387       brw_MOV(p, m1_4, index_4);
 388    } else {
 389       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 390    }
 391
 392    brw_pop_insn_state(p);
 393 }
 394
 395 void
 396 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 397                                     struct brw_reg dst,
 398                                     struct brw_reg index)
 399 {
 400    struct brw_reg header = brw_vec8_grf(0, 0);
 401
 402    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 403
 404    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 405                                      index);
 406
 407    uint32_t msg_type;
 408
 409    if (intel->gen >= 6)
 410       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 411    else if (intel->gen == 5 || intel->is_g4x)
 412       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 413    else
 414       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 415
 416    /* Each of the 8 channel enables is considered for whether each
 417     * dword is written.
 418     */
 419    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 420    brw_set_dest(p, send, dst);
 421    brw_set_src0(p, send, header);
 422    if (intel->gen < 6)
 423       send->header.destreg__conditionalmod = inst->base_mrf;
 424    brw_set_dp_read_message(p, send,
 425                            255, /* binding table index: stateless access */
 426                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 427                            msg_type,
 428                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 429                            2, /* mlen */
 430                            1 /* rlen */);
 431 }
 432
 433 void
 434 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 435                                      struct brw_reg dst,
 436                                      struct brw_reg src,
 437                                      struct brw_reg index)
 438 {
 439    struct brw_reg header = brw_vec8_grf(0, 0);
 440    bool write_commit;
 441
 442    /* If the instruction is predicated, we'll predicate the send, not
 443     * the header setup.
 444     */
 445    brw_set_predicate_control(p, false);
 446
 447    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 448
 449    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 450                                      index);
 451
 452    brw_MOV(p,
 453            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 454            retype(src, BRW_REGISTER_TYPE_D));
 455
 456    uint32_t msg_type;
 457
 458    if (intel->gen >= 6)
 459       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 460    else
 461       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 462
 463    brw_set_predicate_control(p, inst->predicate);
 464
 465    /* Pre-gen6, we have to specify write commits to ensure ordering
 466     * between reads and writes within a thread.  Afterwards, that's
 467     * guaranteed and write commits only matter for inter-thread
 468     * synchronization.
 469     */
 470    if (intel->gen >= 6) {
 471       write_commit = false;
 472    } else {
 473       /* The visitor set up our destination register to be g0.  This
 474        * means that when the next read comes along, we will end up
 475        * reading from g0 and causing a block on the write commit.  For
 476        * write-after-read, we are relying on the value of the previous
 477        * read being used (and thus blocking on completion) before our
 478        * write is executed.  This means we have to be careful in
 479        * instruction scheduling to not violate this assumption.
 480        */
 481       write_commit = true;
 482    }
 483
 484    /* Each of the 8 channel enables is considered for whether each
 485     * dword is written.
 486     */
 487    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 488    brw_set_dest(p, send, dst);
 489    brw_set_src0(p, send, header);
 490    if (intel->gen < 6)
 491       send->header.destreg__conditionalmod = inst->base_mrf;
 492    brw_set_dp_write_message(p, send,
 493                             255, /* binding table index: stateless access */
 494                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 495                             msg_type,
 496                             3, /* mlen */
 497                             true, /* header present */
 498                             false, /* pixel scoreboard */
 499                             write_commit, /* rlen */
 500                             false, /* eot */
 501                             write_commit);
 502 }
 503
 504 void
 505 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 506                                           struct brw_reg dst,
 507                                           struct brw_reg index)
 508 {
 509    struct brw_reg header = brw_vec8_grf(0, 0);
 510
 511    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 512
 513    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 514            index);
 515
 516    uint32_t msg_type;
 517
 518    if (intel->gen >= 6)
 519       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 520    else if (intel->gen == 5 || intel->is_g4x)
 521       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 522    else
 523       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 524
 525    /* Each of the 8 channel enables is considered for whether each
 526     * dword is written.
 527     */
 528    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 529    brw_set_dest(p, send, dst);
 530    brw_set_src0(p, send, header);
 531    if (intel->gen < 6)
 532       send->header.destreg__conditionalmod = inst->base_mrf;
 533    brw_set_dp_read_message(p, send,
 534                            SURF_INDEX_VERT_CONST_BUFFER,
 535                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 536                            msg_type,
 537                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 538                            2, /* mlen */
 539                            1 /* rlen */);
 540 }
 541
 542 void
 543 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 544                                       struct brw_reg dst,
 545                                       struct brw_reg *src)
 546 {
 547    vec4_instruction *inst = (vec4_instruction *)instruction;
 548
 549    switch (inst->opcode) {
 550    case SHADER_OPCODE_RCP:
 551    case SHADER_OPCODE_RSQ:
 552    case SHADER_OPCODE_SQRT:
 553    case SHADER_OPCODE_EXP2:
 554    case SHADER_OPCODE_LOG2:
 555    case SHADER_OPCODE_SIN:
 556    case SHADER_OPCODE_COS:
 557       if (intel->gen >= 6) {
 558          generate_math1_gen6(inst, dst, src[0]);
 559       } else {
 560          generate_math1_gen4(inst, dst, src[0]);
 561       }
 562       break;
 563
 564    case SHADER_OPCODE_POW:
 565       if (intel->gen >= 6) {
 566          generate_math2_gen6(inst, dst, src[0], src[1]);
 567       } else {
 568          generate_math2_gen4(inst, dst, src[0], src[1]);
 569       }
 570       break;
 571
 572    case VS_OPCODE_URB_WRITE:
 573       generate_urb_write(inst);
 574       break;
 575
 576    case VS_OPCODE_SCRATCH_READ:
 577       generate_scratch_read(inst, dst, src[0]);
 578       break;
 579
 580    case VS_OPCODE_SCRATCH_WRITE:
 581       generate_scratch_write(inst, dst, src[0], src[1]);
 582       break;
 583
 584    case VS_OPCODE_PULL_CONSTANT_LOAD:
 585       generate_pull_constant_load(inst, dst, src[0]);
 586       break;
 587
 588    default:
 589       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 590          fail("unsupported opcode in `%s' in VS\n",
 591               brw_opcodes[inst->opcode].name);
 592       } else {
 593          fail("Unsupported opcode %d in VS", inst->opcode);
 594       }
 595    }
 596 }
 597
 598 bool
 599 vec4_visitor::run()
 600 {
 601    /* Generate VS IR for main().  (the visitor only descends into
 602     * functions called "main").
 603     */
 604    visit_instructions(shader->ir);
 605
 606    emit_urb_writes();
 607
 608    /* Before any optimization, push array accesses out to scratch
 609     * space where we need them to be.  This pass may allocate new
 610     * virtual GRFs, so we want to do it early.  It also makes sure
 611     * that we have reladdr computations available for CSE, since we'll
 612     * often do repeated subexpressions for those.
 613     */
 614    move_grf_array_access_to_scratch();
 615    move_uniform_array_access_to_pull_constants();
 616    pack_uniform_registers();
 617    move_push_constants_to_pull_constants();
 618
 619    bool progress;
 620    do {
 621       progress = false;
 622       progress = dead_code_eliminate() || progress;
 623       progress = opt_copy_propagation() || progress;
 624       progress = opt_algebraic() || progress;
 625       progress = opt_compute_to_mrf() || progress;
 626    } while (progress);
 627
 628
 629    if (failed)
 630       return false;
 631
 632    setup_payload();
 633    reg_allocate();
 634
 635    if (failed)
 636       return false;
 637
 638    brw_set_access_mode(p, BRW_ALIGN_16);
 639
 640    generate_code();
 641
 642    return !failed;
 643 }
 644
 645 void
 646 vec4_visitor::generate_code()
 647 {
 648    int last_native_inst = 0;
 649    const char *last_annotation_string = NULL;
 650    ir_instruction *last_annotation_ir = NULL;
 651
 652    int loop_stack_array_size = 16;
 653    int loop_stack_depth = 0;
 654    brw_instruction **loop_stack =
 655       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 656    int *if_depth_in_loop =
 657       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 658
 659
 660    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 661       printf("Native code for vertex shader %d:\n", prog->Name);
 662    }
 663
 664    foreach_list(node, &this->instructions) {
 665       vec4_instruction *inst = (vec4_instruction *)node;
 666       struct brw_reg src[3], dst;
 667
 668       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 669          if (last_annotation_ir != inst->ir) {
 670             last_annotation_ir = inst->ir;
 671             if (last_annotation_ir) {
 672                printf("   ");
 673                last_annotation_ir->print();
 674                printf("\n");
 675             }
 676          }
 677          if (last_annotation_string != inst->annotation) {
 678             last_annotation_string = inst->annotation;
 679             if (last_annotation_string)
 680                printf("   %s\n", last_annotation_string);
 681          }
 682       }
 683
 684       for (unsigned int i = 0; i < 3; i++) {
 685          src[i] = inst->get_src(i);
 686       }
 687       dst = inst->get_dst();
 688
 689       brw_set_conditionalmod(p, inst->conditional_mod);
 690       brw_set_predicate_control(p, inst->predicate);
 691       brw_set_predicate_inverse(p, inst->predicate_inverse);
 692       brw_set_saturate(p, inst->saturate);
 693
 694       switch (inst->opcode) {
 695       case BRW_OPCODE_MOV:
 696          brw_MOV(p, dst, src[0]);
 697          break;
 698       case BRW_OPCODE_ADD:
 699          brw_ADD(p, dst, src[0], src[1]);
 700          break;
 701       case BRW_OPCODE_MUL:
 702          brw_MUL(p, dst, src[0], src[1]);
 703          break;
 704       case BRW_OPCODE_MACH:
 705          brw_set_acc_write_control(p, 1);
 706          brw_MACH(p, dst, src[0], src[1]);
 707          brw_set_acc_write_control(p, 0);
 708          break;
 709
 710       case BRW_OPCODE_FRC:
 711          brw_FRC(p, dst, src[0]);
 712          break;
 713       case BRW_OPCODE_RNDD:
 714          brw_RNDD(p, dst, src[0]);
 715          break;
 716       case BRW_OPCODE_RNDE:
 717          brw_RNDE(p, dst, src[0]);
 718          break;
 719       case BRW_OPCODE_RNDZ:
 720          brw_RNDZ(p, dst, src[0]);
 721          break;
 722
 723       case BRW_OPCODE_AND:
 724          brw_AND(p, dst, src[0], src[1]);
 725          break;
 726       case BRW_OPCODE_OR:
 727          brw_OR(p, dst, src[0], src[1]);
 728          break;
 729       case BRW_OPCODE_XOR:
 730          brw_XOR(p, dst, src[0], src[1]);
 731          break;
 732       case BRW_OPCODE_NOT:
 733          brw_NOT(p, dst, src[0]);
 734          break;
 735       case BRW_OPCODE_ASR:
 736          brw_ASR(p, dst, src[0], src[1]);
 737          break;
 738       case BRW_OPCODE_SHR:
 739          brw_SHR(p, dst, src[0], src[1]);
 740          break;
 741       case BRW_OPCODE_SHL:
 742          brw_SHL(p, dst, src[0], src[1]);
 743          break;
 744
 745       case BRW_OPCODE_CMP:
 746          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 747          break;
 748       case BRW_OPCODE_SEL:
 749          brw_SEL(p, dst, src[0], src[1]);
 750          break;
 751
 752       case BRW_OPCODE_DP4:
 753          brw_DP4(p, dst, src[0], src[1]);
 754          break;
 755
 756       case BRW_OPCODE_DP3:
 757          brw_DP3(p, dst, src[0], src[1]);
 758          break;
 759
 760       case BRW_OPCODE_DP2:
 761          brw_DP2(p, dst, src[0], src[1]);
 762          break;
 763
 764       case BRW_OPCODE_IF:
 765          if (inst->src[0].file != BAD_FILE) {
 766             /* The instruction has an embedded compare (only allowed on gen6) */
 767             assert(intel->gen == 6);
 768             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 769          } else {
 770             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 771             brw_inst->header.predicate_control = inst->predicate;
 772          }
 773          if_depth_in_loop[loop_stack_depth]++;
 774          break;
 775
 776       case BRW_OPCODE_ELSE:
 777          brw_ELSE(p);
 778          break;
 779       case BRW_OPCODE_ENDIF:
 780          brw_ENDIF(p);
 781          if_depth_in_loop[loop_stack_depth]--;
 782          break;
 783
 784       case BRW_OPCODE_DO:
 785          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 786          if (loop_stack_array_size <= loop_stack_depth) {
 787             loop_stack_array_size *= 2;
 788             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 789                                   loop_stack_array_size);
 790             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 791                                         loop_stack_array_size);
 792          }
 793          if_depth_in_loop[loop_stack_depth] = 0;
 794          break;
 795
 796       case BRW_OPCODE_BREAK:
 797          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 798          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 799          break;
 800       case BRW_OPCODE_CONTINUE:
 801          /* FINISHME: We need to write the loop instruction support still. */
 802          if (intel->gen >= 6)
 803             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 804          else
 805             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 806          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 807          break;
 808
 809       case BRW_OPCODE_WHILE: {
 810          struct brw_instruction *inst0, *inst1;
 811          GLuint br = 1;
 812
 813          if (intel->gen >= 5)
 814             br = 2;
 815
 816          assert(loop_stack_depth > 0);
 817          loop_stack_depth--;
 818          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 819          if (intel->gen < 6) {
 820             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 821             while (inst0 > loop_stack[loop_stack_depth]) {
 822                inst0--;
 823                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 824                    inst0->bits3.if_else.jump_count == 0) {
 825                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 826             }
 827                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 828                         inst0->bits3.if_else.jump_count == 0) {
 829                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 830                }
 831             }
 832          }
 833       }
 834          break;
 835
 836       default:
 837          generate_vs_instruction(inst, dst, src);
 838          break;
 839       }
 840
 841       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 842          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 843             if (0) {
 844                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 845                       ((uint32_t *)&p->store[i])[3],
 846                       ((uint32_t *)&p->store[i])[2],
 847                       ((uint32_t *)&p->store[i])[1],
 848                       ((uint32_t *)&p->store[i])[0]);
 849             }
 850             brw_disasm(stdout, &p->store[i], intel->gen);
 851          }
 852       }
 853
 854       last_native_inst = p->nr_insn;
 855    }
 856
 857    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 858       printf("\n");
 859    }
 860
 861    ralloc_free(loop_stack);
 862    ralloc_free(if_depth_in_loop);
 863
 864    brw_set_uip_jip(p);
 865
 866    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 867     * emit issues, it doesn't get the jump distances into the output,
 868     * which is often something we want to debug.  So this is here in
 869     * case you're doing that.
 870     */
 871    if (0) {
 872       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 873          for (unsigned int i = 0; i < p->nr_insn; i++) {
 874             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 875                    ((uint32_t *)&p->store[i])[3],
 876                    ((uint32_t *)&p->store[i])[2],
 877                    ((uint32_t *)&p->store[i])[1],
 878                    ((uint32_t *)&p->store[i])[0]);
 879             brw_disasm(stdout, &p->store[i], intel->gen);
 880          }
 881       }
 882    }
 883 }
 884
 885 extern "C" {
 886
 887 bool
 888 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 889 {
 890    if (!prog)
 891       return false;
 892
 893    struct brw_shader *shader =
 894      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 895    if (!shader)
 896       return false;
 897
 898    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 899       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 900       _mesa_print_ir(shader->ir, NULL);
 901       printf("\n\n");
 902    }
 903
 904    vec4_visitor v(c, prog, shader);
 905    if (!v.run()) {
 906       prog->LinkStatus = GL_FALSE;
 907       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 908       return false;
 909    }
 910
 911    return true;
 912 }
 913
 914 } /* extern "C" */
 915
 916 } /* namespace brw */