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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "glsl/glsl_parser_extras.h"
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26 #include "brw_eu.h"
27 #include "brw_program.h"
28
29 using namespace brw;
30
31 static void
32 generate_math1_gen4(struct brw_codegen *p,
33 vec4_instruction *inst,
34 struct brw_reg dst,
35 struct brw_reg src)
36 {
37 gen4_math(p,
38 dst,
39 brw_math_function(inst->opcode),
40 inst->base_mrf,
41 src,
42 BRW_MATH_PRECISION_FULL);
43 }
44
45 static void
46 check_gen6_math_src_arg(struct brw_reg src)
47 {
48 /* Source swizzles are ignored. */
49 assert(!src.abs);
50 assert(!src.negate);
51 assert(src.swizzle == BRW_SWIZZLE_XYZW);
52 }
53
54 static void
55 generate_math_gen6(struct brw_codegen *p,
56 vec4_instruction *inst,
57 struct brw_reg dst,
58 struct brw_reg src0,
59 struct brw_reg src1)
60 {
61 /* Can't do writemask because math can't be align16. */
62 assert(dst.writemask == WRITEMASK_XYZW);
63 /* Source swizzles are ignored. */
64 check_gen6_math_src_arg(src0);
65 if (src1.file == BRW_GENERAL_REGISTER_FILE)
66 check_gen6_math_src_arg(src1);
67
68 brw_set_default_access_mode(p, BRW_ALIGN_1);
69 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
70 brw_set_default_access_mode(p, BRW_ALIGN_16);
71 }
72
73 static void
74 generate_math2_gen4(struct brw_codegen *p,
75 vec4_instruction *inst,
76 struct brw_reg dst,
77 struct brw_reg src0,
78 struct brw_reg src1)
79 {
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
81 * "Message Payload":
82 *
83 * "Operand0[7]. For the INT DIV functions, this operand is the
84 * denominator."
85 * ...
86 * "Operand1[7]. For the INT DIV functions, this operand is the
87 * numerator."
88 */
89 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
90 struct brw_reg &op0 = is_int_div ? src1 : src0;
91 struct brw_reg &op1 = is_int_div ? src0 : src1;
92
93 brw_push_insn_state(p);
94 brw_set_default_saturate(p, false);
95 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
96 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
97 brw_pop_insn_state(p);
98
99 gen4_math(p,
100 dst,
101 brw_math_function(inst->opcode),
102 inst->base_mrf,
103 op0,
104 BRW_MATH_PRECISION_FULL);
105 }
106
107 static void
108 generate_tex(struct brw_codegen *p,
109 struct brw_vue_prog_data *prog_data,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg surface_index,
114 struct brw_reg sampler_index)
115 {
116 const struct brw_device_info *devinfo = p->devinfo;
117 int msg_type = -1;
118
119 if (devinfo->gen >= 5) {
120 switch (inst->opcode) {
121 case SHADER_OPCODE_TEX:
122 case SHADER_OPCODE_TXL:
123 if (inst->shadow_compare) {
124 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
125 } else {
126 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
127 }
128 break;
129 case SHADER_OPCODE_TXD:
130 if (inst->shadow_compare) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo->gen >= 8 || devinfo->is_haswell);
133 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
134 } else {
135 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
136 }
137 break;
138 case SHADER_OPCODE_TXF:
139 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
140 break;
141 case SHADER_OPCODE_TXF_CMS_W:
142 assert(devinfo->gen >= 9);
143 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
144 break;
145 case SHADER_OPCODE_TXF_CMS:
146 if (devinfo->gen >= 7)
147 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
148 else
149 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
150 break;
151 case SHADER_OPCODE_TXF_MCS:
152 assert(devinfo->gen >= 7);
153 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
154 break;
155 case SHADER_OPCODE_TXS:
156 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
157 break;
158 case SHADER_OPCODE_TG4:
159 if (inst->shadow_compare) {
160 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
161 } else {
162 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
163 }
164 break;
165 case SHADER_OPCODE_TG4_OFFSET:
166 if (inst->shadow_compare) {
167 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
168 } else {
169 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
170 }
171 break;
172 case SHADER_OPCODE_SAMPLEINFO:
173 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
174 break;
175 default:
176 unreachable("should not get here: invalid vec4 texture opcode");
177 }
178 } else {
179 switch (inst->opcode) {
180 case SHADER_OPCODE_TEX:
181 case SHADER_OPCODE_TXL:
182 if (inst->shadow_compare) {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
184 assert(inst->mlen == 3);
185 } else {
186 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
187 assert(inst->mlen == 2);
188 }
189 break;
190 case SHADER_OPCODE_TXD:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
193 assert(inst->mlen == 4);
194 break;
195 case SHADER_OPCODE_TXF:
196 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
197 assert(inst->mlen == 2);
198 break;
199 case SHADER_OPCODE_TXS:
200 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
201 assert(inst->mlen == 2);
202 break;
203 default:
204 unreachable("should not get here: invalid vec4 texture opcode");
205 }
206 }
207
208 assert(msg_type != -1);
209
210 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
211
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
215 */
216 if (inst->header_size != 0) {
217 if (devinfo->gen < 6 && !inst->offset) {
218 /* Set up an implied move from g0 to the MRF. */
219 src = brw_vec8_grf(0, 0);
220 } else {
221 struct brw_reg header =
222 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
223 uint32_t dw2 = 0;
224
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p);
227 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
228 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
229
230 brw_set_default_access_mode(p, BRW_ALIGN_1);
231
232 if (inst->offset)
233 /* Set the texel offset bits in DWord 2. */
234 dw2 = inst->offset;
235
236 if (devinfo->gen >= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
239 */
240 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
241
242 if (dw2)
243 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
244
245 brw_adjust_sampler_state_pointer(p, header, sampler_index);
246 brw_pop_insn_state(p);
247 }
248 }
249
250 uint32_t return_format;
251
252 switch (dst.type) {
253 case BRW_REGISTER_TYPE_D:
254 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
255 break;
256 case BRW_REGISTER_TYPE_UD:
257 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
258 break;
259 default:
260 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
261 break;
262 }
263
264 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
265 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
266 ? prog_data->base.binding_table.gather_texture_start
267 : prog_data->base.binding_table.texture_start;
268
269 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
270 sampler_index.file == BRW_IMMEDIATE_VALUE) {
271 uint32_t surface = surface_index.ud;
272 uint32_t sampler = sampler_index.ud;
273
274 brw_SAMPLE(p,
275 dst,
276 inst->base_mrf,
277 src,
278 surface + base_binding_table_index,
279 sampler % 16,
280 msg_type,
281 1, /* response length */
282 inst->mlen,
283 inst->header_size != 0,
284 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
285 return_format);
286
287 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
288 } else {
289 /* Non-constant sampler index. */
290
291 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
292 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
293 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
294
295 brw_push_insn_state(p);
296 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
297 brw_set_default_access_mode(p, BRW_ALIGN_1);
298
299 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
300 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
301 } else {
302 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
303 brw_OR(p, addr, addr, surface_reg);
304 }
305 if (base_binding_table_index)
306 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
307 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
308
309 brw_pop_insn_state(p);
310
311 if (inst->base_mrf != -1)
312 gen6_resolve_implied_move(p, &src, inst->base_mrf);
313
314 /* dst = send(offset, a0.0 | <descriptor>) */
315 brw_inst *insn = brw_send_indirect_message(
316 p, BRW_SFID_SAMPLER, dst, src, addr);
317 brw_set_sampler_message(p, insn,
318 0 /* surface */,
319 0 /* sampler */,
320 msg_type,
321 1 /* rlen */,
322 inst->mlen /* mlen */,
323 inst->header_size != 0 /* header */,
324 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
325 return_format);
326
327 /* visitor knows more than we do about the surface limit required,
328 * so has already done marking.
329 */
330 }
331 }
332
333 static void
334 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
335 {
336 brw_urb_WRITE(p,
337 brw_null_reg(), /* dest */
338 inst->base_mrf, /* starting mrf reg nr */
339 brw_vec8_grf(0, 0), /* src */
340 inst->urb_write_flags,
341 inst->mlen,
342 0, /* response len */
343 inst->offset, /* urb destination offset */
344 BRW_URB_SWIZZLE_INTERLEAVE);
345 }
346
347 static void
348 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
349 {
350 struct brw_reg src = brw_message_reg(inst->base_mrf);
351 brw_urb_WRITE(p,
352 brw_null_reg(), /* dest */
353 inst->base_mrf, /* starting mrf reg nr */
354 src,
355 inst->urb_write_flags,
356 inst->mlen,
357 0, /* response len */
358 inst->offset, /* urb destination offset */
359 BRW_URB_SWIZZLE_INTERLEAVE);
360 }
361
362 static void
363 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
364 {
365 struct brw_reg src = brw_message_reg(inst->base_mrf);
366
367 /* We pass the temporary passed in src0 as the writeback register */
368 brw_urb_WRITE(p,
369 inst->src[0].as_brw_reg(), /* dest */
370 inst->base_mrf, /* starting mrf reg nr */
371 src,
372 BRW_URB_WRITE_ALLOCATE_COMPLETE,
373 inst->mlen,
374 1, /* response len */
375 inst->offset, /* urb destination offset */
376 BRW_URB_SWIZZLE_INTERLEAVE);
377
378 /* Now put allocated urb handle in dst.0 */
379 brw_push_insn_state(p);
380 brw_set_default_access_mode(p, BRW_ALIGN_1);
381 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
382 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
383 get_element_ud(inst->src[0].as_brw_reg(), 0));
384 brw_pop_insn_state(p);
385 }
386
387 static void
388 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
389 {
390 struct brw_reg src = brw_message_reg(inst->base_mrf);
391 brw_urb_WRITE(p,
392 brw_null_reg(), /* dest */
393 inst->base_mrf, /* starting mrf reg nr */
394 src,
395 BRW_URB_WRITE_EOT | inst->urb_write_flags,
396 inst->mlen,
397 0, /* response len */
398 0, /* urb destination offset */
399 BRW_URB_SWIZZLE_INTERLEAVE);
400 }
401
402 static void
403 generate_gs_set_write_offset(struct brw_codegen *p,
404 struct brw_reg dst,
405 struct brw_reg src0,
406 struct brw_reg src1)
407 {
408 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
409 * Header: M0.3):
410 *
411 * Slot 0 Offset. This field, after adding to the Global Offset field
412 * in the message descriptor, specifies the offset (in 256-bit units)
413 * from the start of the URB entry, as referenced by URB Handle 0, at
414 * which the data will be accessed.
415 *
416 * Similar text describes DWORD M0.4, which is slot 1 offset.
417 *
418 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
419 * of the register for geometry shader invocations 0 and 1) by the
420 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
421 *
422 * We can do this with the following EU instruction:
423 *
424 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
425 */
426 brw_push_insn_state(p);
427 brw_set_default_access_mode(p, BRW_ALIGN_1);
428 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
429 assert(p->devinfo->gen >= 7 &&
430 src1.file == BRW_IMMEDIATE_VALUE &&
431 src1.type == BRW_REGISTER_TYPE_UD &&
432 src1.ud <= USHRT_MAX);
433 if (src0.file == BRW_IMMEDIATE_VALUE) {
434 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
435 brw_imm_ud(src0.ud * src1.ud));
436 } else {
437 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
438 retype(src1, BRW_REGISTER_TYPE_UW));
439 }
440 brw_pop_insn_state(p);
441 }
442
443 static void
444 generate_gs_set_vertex_count(struct brw_codegen *p,
445 struct brw_reg dst,
446 struct brw_reg src)
447 {
448 brw_push_insn_state(p);
449 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
450
451 if (p->devinfo->gen >= 8) {
452 /* Move the vertex count into the second MRF for the EOT write. */
453 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
454 src);
455 } else {
456 /* If we think of the src and dst registers as composed of 8 DWORDs each,
457 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
458 * them to WORDs, and then pack them into DWORD 2 of dst.
459 *
460 * It's easier to get the EU to do this if we think of the src and dst
461 * registers as composed of 16 WORDS each; then, we want to pick up the
462 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
463 * of dst.
464 *
465 * We can do that by the following EU instruction:
466 *
467 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
468 */
469 brw_set_default_access_mode(p, BRW_ALIGN_1);
470 brw_MOV(p,
471 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
472 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
473 }
474 brw_pop_insn_state(p);
475 }
476
477 static void
478 generate_gs_svb_write(struct brw_codegen *p,
479 struct brw_vue_prog_data *prog_data,
480 vec4_instruction *inst,
481 struct brw_reg dst,
482 struct brw_reg src0,
483 struct brw_reg src1)
484 {
485 int binding = inst->sol_binding;
486 bool final_write = inst->sol_final_write;
487
488 brw_push_insn_state(p);
489 /* Copy Vertex data into M0.x */
490 brw_MOV(p, stride(dst, 4, 4, 1),
491 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
492
493 /* Send SVB Write */
494 brw_svb_write(p,
495 final_write ? src1 : brw_null_reg(), /* dest == src1 */
496 1, /* msg_reg_nr */
497 dst, /* src0 == previous dst */
498 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
499 final_write); /* send_commit_msg */
500
501 /* Finally, wait for the write commit to occur so that we can proceed to
502 * other things safely.
503 *
504 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
505 *
506 * The write commit does not modify the destination register, but
507 * merely clears the dependency associated with the destination
508 * register. Thus, a simple “mov” instruction using the register as a
509 * source is sufficient to wait for the write commit to occur.
510 */
511 if (final_write) {
512 brw_MOV(p, src1, src1);
513 }
514 brw_pop_insn_state(p);
515 }
516
517 static void
518 generate_gs_svb_set_destination_index(struct brw_codegen *p,
519 vec4_instruction *inst,
520 struct brw_reg dst,
521 struct brw_reg src)
522 {
523 int vertex = inst->sol_vertex;
524 brw_push_insn_state(p);
525 brw_set_default_access_mode(p, BRW_ALIGN_1);
526 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
527 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
528 brw_pop_insn_state(p);
529 }
530
531 static void
532 generate_gs_set_dword_2(struct brw_codegen *p,
533 struct brw_reg dst,
534 struct brw_reg src)
535 {
536 brw_push_insn_state(p);
537 brw_set_default_access_mode(p, BRW_ALIGN_1);
538 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
539 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
540 brw_pop_insn_state(p);
541 }
542
543 static void
544 generate_gs_prepare_channel_masks(struct brw_codegen *p,
545 struct brw_reg dst)
546 {
547 /* We want to left shift just DWORD 4 (the x component belonging to the
548 * second geometry shader invocation) by 4 bits. So generate the
549 * instruction:
550 *
551 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
552 */
553 dst = suboffset(vec1(dst), 4);
554 brw_push_insn_state(p);
555 brw_set_default_access_mode(p, BRW_ALIGN_1);
556 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
557 brw_SHL(p, dst, dst, brw_imm_ud(4));
558 brw_pop_insn_state(p);
559 }
560
561 static void
562 generate_gs_set_channel_masks(struct brw_codegen *p,
563 struct brw_reg dst,
564 struct brw_reg src)
565 {
566 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
567 * Header: M0.5):
568 *
569 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
570 *
571 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
572 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
573 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
574 * channel enable to determine the final channel enable. For the
575 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
576 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
577 * in the writeback message. For the URB_WRITE_OWORD &
578 * URB_WRITE_HWORD messages, when final channel enable is 1 it
579 * indicates that Vertex 1 DATA [3] will be written to the surface.
580 *
581 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
582 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
583 *
584 * 14 Vertex 1 DATA [2] Channel Mask
585 * 13 Vertex 1 DATA [1] Channel Mask
586 * 12 Vertex 1 DATA [0] Channel Mask
587 * 11 Vertex 0 DATA [3] Channel Mask
588 * 10 Vertex 0 DATA [2] Channel Mask
589 * 9 Vertex 0 DATA [1] Channel Mask
590 * 8 Vertex 0 DATA [0] Channel Mask
591 *
592 * (This is from a section of the PRM that is agnostic to the particular
593 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
594 * geometry shader invocations 0 and 1, respectively). Since we have the
595 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
596 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
597 * DWORD 4, we just need to OR them together and store the result in bits
598 * 15:8 of DWORD 5.
599 *
600 * It's easier to get the EU to do this if we think of the src and dst
601 * registers as composed of 32 bytes each; then, we want to pick up the
602 * contents of bytes 0 and 16 from src, OR them together, and store them in
603 * byte 21.
604 *
605 * We can do that by the following EU instruction:
606 *
607 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
608 *
609 * Note: this relies on the source register having zeros in (a) bits 7:4 of
610 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
611 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
612 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
613 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
614 * contain valid channel mask values (which are in the range 0x0-0xf).
615 */
616 dst = retype(dst, BRW_REGISTER_TYPE_UB);
617 src = retype(src, BRW_REGISTER_TYPE_UB);
618 brw_push_insn_state(p);
619 brw_set_default_access_mode(p, BRW_ALIGN_1);
620 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
621 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
622 brw_pop_insn_state(p);
623 }
624
625 static void
626 generate_gs_get_instance_id(struct brw_codegen *p,
627 struct brw_reg dst)
628 {
629 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
630 * and store into dst.0 & dst.4. So generate the instruction:
631 *
632 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
633 */
634 brw_push_insn_state(p);
635 brw_set_default_access_mode(p, BRW_ALIGN_1);
636 dst = retype(dst, BRW_REGISTER_TYPE_UD);
637 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
638 brw_SHR(p, dst, stride(r0, 1, 4, 0),
639 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
640 brw_pop_insn_state(p);
641 }
642
643 static void
644 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
645 struct brw_reg dst,
646 struct brw_reg src0,
647 struct brw_reg src1,
648 struct brw_reg src2)
649 {
650 brw_push_insn_state(p);
651 brw_set_default_access_mode(p, BRW_ALIGN_1);
652 /* Save src0 data in 16:31 bits of dst.0 */
653 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
654 brw_imm_ud(0xffffu));
655 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
656 /* Save src1 data in 0:15 bits of dst.0 */
657 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
658 brw_imm_ud(0xffffu));
659 brw_OR(p, suboffset(vec1(dst), 0),
660 suboffset(vec1(dst), 0),
661 suboffset(vec1(src2), 0));
662 brw_pop_insn_state(p);
663 }
664
665 static void
666 generate_gs_ff_sync(struct brw_codegen *p,
667 vec4_instruction *inst,
668 struct brw_reg dst,
669 struct brw_reg src0,
670 struct brw_reg src1)
671 {
672 /* This opcode uses an implied MRF register for:
673 * - the header of the ff_sync message. And as such it is expected to be
674 * initialized to r0 before calling here.
675 * - the destination where we will write the allocated URB handle.
676 */
677 struct brw_reg header =
678 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
679
680 /* Overwrite dword 0 of the header (SO vertices to write) and
681 * dword 1 (number of primitives written).
682 */
683 brw_push_insn_state(p);
684 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
685 brw_set_default_access_mode(p, BRW_ALIGN_1);
686 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
687 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
688 brw_pop_insn_state(p);
689
690 /* Allocate URB handle in dst */
691 brw_ff_sync(p,
692 dst,
693 0,
694 header,
695 1, /* allocate */
696 1, /* response length */
697 0 /* eot */);
698
699 /* Now put allocated urb handle in header.0 */
700 brw_push_insn_state(p);
701 brw_set_default_access_mode(p, BRW_ALIGN_1);
702 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
703 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
704
705 /* src1 is not an immediate when we use transform feedback */
706 if (src1.file != BRW_IMMEDIATE_VALUE)
707 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
708
709 brw_pop_insn_state(p);
710 }
711
712 static void
713 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
714 {
715 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
716 struct brw_reg src = brw_vec8_grf(0, 0);
717 brw_push_insn_state(p);
718 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
719 brw_set_default_access_mode(p, BRW_ALIGN_1);
720 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
721 brw_pop_insn_state(p);
722 }
723
724 static void
725 generate_oword_dual_block_offsets(struct brw_codegen *p,
726 struct brw_reg m1,
727 struct brw_reg index)
728 {
729 int second_vertex_offset;
730
731 if (p->devinfo->gen >= 6)
732 second_vertex_offset = 1;
733 else
734 second_vertex_offset = 16;
735
736 m1 = retype(m1, BRW_REGISTER_TYPE_D);
737
738 /* Set up M1 (message payload). Only the block offsets in M1.0 and
739 * M1.4 are used, and the rest are ignored.
740 */
741 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
742 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
743 struct brw_reg index_0 = suboffset(vec1(index), 0);
744 struct brw_reg index_4 = suboffset(vec1(index), 4);
745
746 brw_push_insn_state(p);
747 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
748 brw_set_default_access_mode(p, BRW_ALIGN_1);
749
750 brw_MOV(p, m1_0, index_0);
751
752 if (index.file == BRW_IMMEDIATE_VALUE) {
753 index_4.ud += second_vertex_offset;
754 brw_MOV(p, m1_4, index_4);
755 } else {
756 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
757 }
758
759 brw_pop_insn_state(p);
760 }
761
762 static void
763 generate_unpack_flags(struct brw_codegen *p,
764 struct brw_reg dst)
765 {
766 brw_push_insn_state(p);
767 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
768 brw_set_default_access_mode(p, BRW_ALIGN_1);
769
770 struct brw_reg flags = brw_flag_reg(0, 0);
771 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
772 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
773
774 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
775 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
776 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
777
778 brw_pop_insn_state(p);
779 }
780
781 static void
782 generate_scratch_read(struct brw_codegen *p,
783 vec4_instruction *inst,
784 struct brw_reg dst,
785 struct brw_reg index)
786 {
787 const struct brw_device_info *devinfo = p->devinfo;
788 struct brw_reg header = brw_vec8_grf(0, 0);
789
790 gen6_resolve_implied_move(p, &header, inst->base_mrf);
791
792 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
793 index);
794
795 uint32_t msg_type;
796
797 if (devinfo->gen >= 6)
798 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
799 else if (devinfo->gen == 5 || devinfo->is_g4x)
800 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
801 else
802 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
803
804 /* Each of the 8 channel enables is considered for whether each
805 * dword is written.
806 */
807 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
808 brw_set_dest(p, send, dst);
809 brw_set_src0(p, send, header);
810 if (devinfo->gen < 6)
811 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
812 brw_set_dp_read_message(p, send,
813 brw_scratch_surface_idx(p),
814 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
815 msg_type,
816 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
817 2, /* mlen */
818 true, /* header_present */
819 1 /* rlen */);
820 }
821
822 static void
823 generate_scratch_write(struct brw_codegen *p,
824 vec4_instruction *inst,
825 struct brw_reg dst,
826 struct brw_reg src,
827 struct brw_reg index)
828 {
829 const struct brw_device_info *devinfo = p->devinfo;
830 struct brw_reg header = brw_vec8_grf(0, 0);
831 bool write_commit;
832
833 /* If the instruction is predicated, we'll predicate the send, not
834 * the header setup.
835 */
836 brw_set_default_predicate_control(p, false);
837
838 gen6_resolve_implied_move(p, &header, inst->base_mrf);
839
840 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
841 index);
842
843 brw_MOV(p,
844 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
845 retype(src, BRW_REGISTER_TYPE_D));
846
847 uint32_t msg_type;
848
849 if (devinfo->gen >= 7)
850 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
851 else if (devinfo->gen == 6)
852 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
853 else
854 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
855
856 brw_set_default_predicate_control(p, inst->predicate);
857
858 /* Pre-gen6, we have to specify write commits to ensure ordering
859 * between reads and writes within a thread. Afterwards, that's
860 * guaranteed and write commits only matter for inter-thread
861 * synchronization.
862 */
863 if (devinfo->gen >= 6) {
864 write_commit = false;
865 } else {
866 /* The visitor set up our destination register to be g0. This
867 * means that when the next read comes along, we will end up
868 * reading from g0 and causing a block on the write commit. For
869 * write-after-read, we are relying on the value of the previous
870 * read being used (and thus blocking on completion) before our
871 * write is executed. This means we have to be careful in
872 * instruction scheduling to not violate this assumption.
873 */
874 write_commit = true;
875 }
876
877 /* Each of the 8 channel enables is considered for whether each
878 * dword is written.
879 */
880 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
881 brw_set_dest(p, send, dst);
882 brw_set_src0(p, send, header);
883 if (devinfo->gen < 6)
884 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
885 brw_set_dp_write_message(p, send,
886 brw_scratch_surface_idx(p),
887 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
888 msg_type,
889 3, /* mlen */
890 true, /* header present */
891 false, /* not a render target write */
892 write_commit, /* rlen */
893 false, /* eot */
894 write_commit);
895 }
896
897 static void
898 generate_pull_constant_load(struct brw_codegen *p,
899 struct brw_vue_prog_data *prog_data,
900 vec4_instruction *inst,
901 struct brw_reg dst,
902 struct brw_reg index,
903 struct brw_reg offset)
904 {
905 const struct brw_device_info *devinfo = p->devinfo;
906 assert(index.file == BRW_IMMEDIATE_VALUE &&
907 index.type == BRW_REGISTER_TYPE_UD);
908 uint32_t surf_index = index.ud;
909
910 struct brw_reg header = brw_vec8_grf(0, 0);
911
912 gen6_resolve_implied_move(p, &header, inst->base_mrf);
913
914 if (devinfo->gen >= 6) {
915 if (offset.file == BRW_IMMEDIATE_VALUE) {
916 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
917 BRW_REGISTER_TYPE_D),
918 brw_imm_d(offset.ud >> 4));
919 } else {
920 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
921 BRW_REGISTER_TYPE_D),
922 offset, brw_imm_d(4));
923 }
924 } else {
925 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
926 BRW_REGISTER_TYPE_D),
927 offset);
928 }
929
930 uint32_t msg_type;
931
932 if (devinfo->gen >= 6)
933 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
934 else if (devinfo->gen == 5 || devinfo->is_g4x)
935 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
936 else
937 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
938
939 /* Each of the 8 channel enables is considered for whether each
940 * dword is written.
941 */
942 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
943 brw_set_dest(p, send, dst);
944 brw_set_src0(p, send, header);
945 if (devinfo->gen < 6)
946 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
947 brw_set_dp_read_message(p, send,
948 surf_index,
949 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
950 msg_type,
951 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
952 2, /* mlen */
953 true, /* header_present */
954 1 /* rlen */);
955 }
956
957 static void
958 generate_get_buffer_size(struct brw_codegen *p,
959 struct brw_vue_prog_data *prog_data,
960 vec4_instruction *inst,
961 struct brw_reg dst,
962 struct brw_reg src,
963 struct brw_reg surf_index)
964 {
965 assert(p->devinfo->gen >= 7);
966 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
967 surf_index.file == BRW_IMMEDIATE_VALUE);
968
969 brw_SAMPLE(p,
970 dst,
971 inst->base_mrf,
972 src,
973 surf_index.ud,
974 0,
975 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
976 1, /* response length */
977 inst->mlen,
978 inst->header_size > 0,
979 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
980 BRW_SAMPLER_RETURN_FORMAT_SINT32);
981
982 brw_mark_surface_used(&prog_data->base, surf_index.ud);
983 }
984
985 static void
986 generate_pull_constant_load_gen7(struct brw_codegen *p,
987 struct brw_vue_prog_data *prog_data,
988 vec4_instruction *inst,
989 struct brw_reg dst,
990 struct brw_reg surf_index,
991 struct brw_reg offset)
992 {
993 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
994
995 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
996
997 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
998 brw_set_dest(p, insn, dst);
999 brw_set_src0(p, insn, offset);
1000 brw_set_sampler_message(p, insn,
1001 surf_index.ud,
1002 0, /* LD message ignores sampler unit */
1003 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1004 1, /* rlen */
1005 inst->mlen,
1006 inst->header_size != 0,
1007 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1008 0);
1009
1010 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1011
1012 } else {
1013
1014 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1015
1016 brw_push_insn_state(p);
1017 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1018 brw_set_default_access_mode(p, BRW_ALIGN_1);
1019
1020 /* a0.0 = surf_index & 0xff */
1021 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1022 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1023 brw_set_dest(p, insn_and, addr);
1024 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1025 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1026
1027 brw_pop_insn_state(p);
1028
1029 /* dst = send(offset, a0.0 | <descriptor>) */
1030 brw_inst *insn = brw_send_indirect_message(
1031 p, BRW_SFID_SAMPLER, dst, offset, addr);
1032 brw_set_sampler_message(p, insn,
1033 0 /* surface */,
1034 0 /* sampler */,
1035 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1036 1 /* rlen */,
1037 inst->mlen,
1038 inst->header_size != 0,
1039 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1040 0);
1041 }
1042 }
1043
1044 static void
1045 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1046 vec4_instruction *inst,
1047 struct brw_reg dst)
1048 {
1049 brw_push_insn_state(p);
1050 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1051
1052 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1053 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1054
1055 brw_set_default_access_mode(p, BRW_ALIGN_1);
1056 brw_MOV(p, get_element_ud(dst, 2),
1057 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1058
1059 brw_pop_insn_state(p);
1060 }
1061
1062 static void
1063 generate_code(struct brw_codegen *p,
1064 const struct brw_compiler *compiler,
1065 void *log_data,
1066 const nir_shader *nir,
1067 struct brw_vue_prog_data *prog_data,
1068 const struct cfg_t *cfg)
1069 {
1070 const struct brw_device_info *devinfo = p->devinfo;
1071 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
1072 bool debug_flag = INTEL_DEBUG &
1073 intel_debug_flag_for_shader_stage(nir->stage);
1074 struct annotation_info annotation;
1075 memset(&annotation, 0, sizeof(annotation));
1076 int loop_count = 0;
1077
1078 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1079 struct brw_reg src[3], dst;
1080
1081 if (unlikely(debug_flag))
1082 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1083
1084 for (unsigned int i = 0; i < 3; i++) {
1085 src[i] = inst->src[i].as_brw_reg();
1086 }
1087 dst = inst->dst.as_brw_reg();
1088
1089 brw_set_default_predicate_control(p, inst->predicate);
1090 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1091 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1092 brw_set_default_saturate(p, inst->saturate);
1093 brw_set_default_mask_control(p, inst->force_writemask_all);
1094 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1095
1096 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1097 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1098
1099 unsigned pre_emit_nr_insn = p->nr_insn;
1100
1101 if (dst.width == BRW_WIDTH_4) {
1102 /* This happens in attribute fixups for "dual instanced" geometry
1103 * shaders, since they use attributes that are vec4's. Since the exec
1104 * width is only 4, it's essential that the caller set
1105 * force_writemask_all in order to make sure the instruction is executed
1106 * regardless of which channels are enabled.
1107 */
1108 assert(inst->force_writemask_all);
1109
1110 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1111 * the following register region restrictions (from Graphics BSpec:
1112 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1113 * > Register Region Restrictions)
1114 *
1115 * 1. ExecSize must be greater than or equal to Width.
1116 *
1117 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1118 * to Width * HorzStride."
1119 */
1120 for (int i = 0; i < 3; i++) {
1121 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1122 src[i] = stride(src[i], 4, 4, 1);
1123 }
1124 }
1125
1126 switch (inst->opcode) {
1127 case VEC4_OPCODE_UNPACK_UNIFORM:
1128 case BRW_OPCODE_MOV:
1129 brw_MOV(p, dst, src[0]);
1130 break;
1131 case BRW_OPCODE_ADD:
1132 brw_ADD(p, dst, src[0], src[1]);
1133 break;
1134 case BRW_OPCODE_MUL:
1135 brw_MUL(p, dst, src[0], src[1]);
1136 break;
1137 case BRW_OPCODE_MACH:
1138 brw_MACH(p, dst, src[0], src[1]);
1139 break;
1140
1141 case BRW_OPCODE_MAD:
1142 assert(devinfo->gen >= 6);
1143 brw_MAD(p, dst, src[0], src[1], src[2]);
1144 break;
1145
1146 case BRW_OPCODE_FRC:
1147 brw_FRC(p, dst, src[0]);
1148 break;
1149 case BRW_OPCODE_RNDD:
1150 brw_RNDD(p, dst, src[0]);
1151 break;
1152 case BRW_OPCODE_RNDE:
1153 brw_RNDE(p, dst, src[0]);
1154 break;
1155 case BRW_OPCODE_RNDZ:
1156 brw_RNDZ(p, dst, src[0]);
1157 break;
1158
1159 case BRW_OPCODE_AND:
1160 brw_AND(p, dst, src[0], src[1]);
1161 break;
1162 case BRW_OPCODE_OR:
1163 brw_OR(p, dst, src[0], src[1]);
1164 break;
1165 case BRW_OPCODE_XOR:
1166 brw_XOR(p, dst, src[0], src[1]);
1167 break;
1168 case BRW_OPCODE_NOT:
1169 brw_NOT(p, dst, src[0]);
1170 break;
1171 case BRW_OPCODE_ASR:
1172 brw_ASR(p, dst, src[0], src[1]);
1173 break;
1174 case BRW_OPCODE_SHR:
1175 brw_SHR(p, dst, src[0], src[1]);
1176 break;
1177 case BRW_OPCODE_SHL:
1178 brw_SHL(p, dst, src[0], src[1]);
1179 break;
1180
1181 case BRW_OPCODE_CMP:
1182 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1183 break;
1184 case BRW_OPCODE_SEL:
1185 brw_SEL(p, dst, src[0], src[1]);
1186 break;
1187
1188 case BRW_OPCODE_DPH:
1189 brw_DPH(p, dst, src[0], src[1]);
1190 break;
1191
1192 case BRW_OPCODE_DP4:
1193 brw_DP4(p, dst, src[0], src[1]);
1194 break;
1195
1196 case BRW_OPCODE_DP3:
1197 brw_DP3(p, dst, src[0], src[1]);
1198 break;
1199
1200 case BRW_OPCODE_DP2:
1201 brw_DP2(p, dst, src[0], src[1]);
1202 break;
1203
1204 case BRW_OPCODE_F32TO16:
1205 assert(devinfo->gen >= 7);
1206 brw_F32TO16(p, dst, src[0]);
1207 break;
1208
1209 case BRW_OPCODE_F16TO32:
1210 assert(devinfo->gen >= 7);
1211 brw_F16TO32(p, dst, src[0]);
1212 break;
1213
1214 case BRW_OPCODE_LRP:
1215 assert(devinfo->gen >= 6);
1216 brw_LRP(p, dst, src[0], src[1], src[2]);
1217 break;
1218
1219 case BRW_OPCODE_BFREV:
1220 assert(devinfo->gen >= 7);
1221 /* BFREV only supports UD type for src and dst. */
1222 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1223 retype(src[0], BRW_REGISTER_TYPE_UD));
1224 break;
1225 case BRW_OPCODE_FBH:
1226 assert(devinfo->gen >= 7);
1227 /* FBH only supports UD type for dst. */
1228 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1229 break;
1230 case BRW_OPCODE_FBL:
1231 assert(devinfo->gen >= 7);
1232 /* FBL only supports UD type for dst. */
1233 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1234 break;
1235 case BRW_OPCODE_CBIT:
1236 assert(devinfo->gen >= 7);
1237 /* CBIT only supports UD type for dst. */
1238 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1239 break;
1240 case BRW_OPCODE_ADDC:
1241 assert(devinfo->gen >= 7);
1242 brw_ADDC(p, dst, src[0], src[1]);
1243 break;
1244 case BRW_OPCODE_SUBB:
1245 assert(devinfo->gen >= 7);
1246 brw_SUBB(p, dst, src[0], src[1]);
1247 break;
1248 case BRW_OPCODE_MAC:
1249 brw_MAC(p, dst, src[0], src[1]);
1250 break;
1251
1252 case BRW_OPCODE_BFE:
1253 assert(devinfo->gen >= 7);
1254 brw_BFE(p, dst, src[0], src[1], src[2]);
1255 break;
1256
1257 case BRW_OPCODE_BFI1:
1258 assert(devinfo->gen >= 7);
1259 brw_BFI1(p, dst, src[0], src[1]);
1260 break;
1261 case BRW_OPCODE_BFI2:
1262 assert(devinfo->gen >= 7);
1263 brw_BFI2(p, dst, src[0], src[1], src[2]);
1264 break;
1265
1266 case BRW_OPCODE_IF:
1267 if (!inst->src[0].is_null()) {
1268 /* The instruction has an embedded compare (only allowed on gen6) */
1269 assert(devinfo->gen == 6);
1270 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1271 } else {
1272 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1273 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1274 }
1275 break;
1276
1277 case BRW_OPCODE_ELSE:
1278 brw_ELSE(p);
1279 break;
1280 case BRW_OPCODE_ENDIF:
1281 brw_ENDIF(p);
1282 break;
1283
1284 case BRW_OPCODE_DO:
1285 brw_DO(p, BRW_EXECUTE_8);
1286 break;
1287
1288 case BRW_OPCODE_BREAK:
1289 brw_BREAK(p);
1290 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1291 break;
1292 case BRW_OPCODE_CONTINUE:
1293 brw_CONT(p);
1294 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1295 break;
1296
1297 case BRW_OPCODE_WHILE:
1298 brw_WHILE(p);
1299 loop_count++;
1300 break;
1301
1302 case SHADER_OPCODE_RCP:
1303 case SHADER_OPCODE_RSQ:
1304 case SHADER_OPCODE_SQRT:
1305 case SHADER_OPCODE_EXP2:
1306 case SHADER_OPCODE_LOG2:
1307 case SHADER_OPCODE_SIN:
1308 case SHADER_OPCODE_COS:
1309 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1310 if (devinfo->gen >= 7) {
1311 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1312 brw_null_reg());
1313 } else if (devinfo->gen == 6) {
1314 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1315 } else {
1316 generate_math1_gen4(p, inst, dst, src[0]);
1317 }
1318 break;
1319
1320 case SHADER_OPCODE_POW:
1321 case SHADER_OPCODE_INT_QUOTIENT:
1322 case SHADER_OPCODE_INT_REMAINDER:
1323 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1324 if (devinfo->gen >= 7) {
1325 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1326 } else if (devinfo->gen == 6) {
1327 generate_math_gen6(p, inst, dst, src[0], src[1]);
1328 } else {
1329 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1330 }
1331 break;
1332
1333 case SHADER_OPCODE_TEX:
1334 case SHADER_OPCODE_TXD:
1335 case SHADER_OPCODE_TXF:
1336 case SHADER_OPCODE_TXF_CMS:
1337 case SHADER_OPCODE_TXF_CMS_W:
1338 case SHADER_OPCODE_TXF_MCS:
1339 case SHADER_OPCODE_TXL:
1340 case SHADER_OPCODE_TXS:
1341 case SHADER_OPCODE_TG4:
1342 case SHADER_OPCODE_TG4_OFFSET:
1343 case SHADER_OPCODE_SAMPLEINFO:
1344 generate_tex(p, prog_data, inst, dst, src[0], src[1], src[1]);
1345 break;
1346
1347 case VS_OPCODE_URB_WRITE:
1348 generate_vs_urb_write(p, inst);
1349 break;
1350
1351 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1352 generate_scratch_read(p, inst, dst, src[0]);
1353 break;
1354
1355 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1356 generate_scratch_write(p, inst, dst, src[0], src[1]);
1357 break;
1358
1359 case VS_OPCODE_PULL_CONSTANT_LOAD:
1360 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1361 break;
1362
1363 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1364 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1365 break;
1366
1367 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1368 generate_set_simd4x2_header_gen9(p, inst, dst);
1369 break;
1370
1371
1372 case VS_OPCODE_GET_BUFFER_SIZE:
1373 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1374 break;
1375
1376 case GS_OPCODE_URB_WRITE:
1377 generate_gs_urb_write(p, inst);
1378 break;
1379
1380 case GS_OPCODE_URB_WRITE_ALLOCATE:
1381 generate_gs_urb_write_allocate(p, inst);
1382 break;
1383
1384 case GS_OPCODE_SVB_WRITE:
1385 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1386 break;
1387
1388 case GS_OPCODE_SVB_SET_DST_INDEX:
1389 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1390 break;
1391
1392 case GS_OPCODE_THREAD_END:
1393 generate_gs_thread_end(p, inst);
1394 break;
1395
1396 case GS_OPCODE_SET_WRITE_OFFSET:
1397 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1398 break;
1399
1400 case GS_OPCODE_SET_VERTEX_COUNT:
1401 generate_gs_set_vertex_count(p, dst, src[0]);
1402 break;
1403
1404 case GS_OPCODE_FF_SYNC:
1405 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1406 break;
1407
1408 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1409 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1410 break;
1411
1412 case GS_OPCODE_SET_PRIMITIVE_ID:
1413 generate_gs_set_primitive_id(p, dst);
1414 break;
1415
1416 case GS_OPCODE_SET_DWORD_2:
1417 generate_gs_set_dword_2(p, dst, src[0]);
1418 break;
1419
1420 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1421 generate_gs_prepare_channel_masks(p, dst);
1422 break;
1423
1424 case GS_OPCODE_SET_CHANNEL_MASKS:
1425 generate_gs_set_channel_masks(p, dst, src[0]);
1426 break;
1427
1428 case GS_OPCODE_GET_INSTANCE_ID:
1429 generate_gs_get_instance_id(p, dst);
1430 break;
1431
1432 case SHADER_OPCODE_SHADER_TIME_ADD:
1433 brw_shader_time_add(p, src[0],
1434 prog_data->base.binding_table.shader_time_start);
1435 brw_mark_surface_used(&prog_data->base,
1436 prog_data->base.binding_table.shader_time_start);
1437 break;
1438
1439 case SHADER_OPCODE_UNTYPED_ATOMIC:
1440 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1441 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1442 !inst->dst.is_null());
1443 break;
1444
1445 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1446 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1447 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1448 src[2].ud);
1449 break;
1450
1451 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1452 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1453 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1454 src[2].ud);
1455 break;
1456
1457 case SHADER_OPCODE_TYPED_ATOMIC:
1458 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1459 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1460 !inst->dst.is_null());
1461 break;
1462
1463 case SHADER_OPCODE_TYPED_SURFACE_READ:
1464 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1465 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1466 src[2].ud);
1467 break;
1468
1469 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1470 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1471 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1472 src[2].ud);
1473 break;
1474
1475 case SHADER_OPCODE_MEMORY_FENCE:
1476 brw_memory_fence(p, dst);
1477 break;
1478
1479 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1480 brw_find_live_channel(p, dst);
1481 break;
1482
1483 case SHADER_OPCODE_BROADCAST:
1484 brw_broadcast(p, dst, src[0], src[1]);
1485 break;
1486
1487 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1488 generate_unpack_flags(p, dst);
1489 break;
1490
1491 case VEC4_OPCODE_MOV_BYTES: {
1492 /* Moves the low byte from each channel, using an Align1 access mode
1493 * and a <4,1,0> source region.
1494 */
1495 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1496 src[0].type == BRW_REGISTER_TYPE_B);
1497
1498 brw_set_default_access_mode(p, BRW_ALIGN_1);
1499 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1500 src[0].width = BRW_WIDTH_1;
1501 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1502 brw_MOV(p, dst, src[0]);
1503 brw_set_default_access_mode(p, BRW_ALIGN_16);
1504 break;
1505 }
1506
1507 case VEC4_OPCODE_PACK_BYTES: {
1508 /* Is effectively:
1509 *
1510 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1511 *
1512 * but destinations' only regioning is horizontal stride, so instead we
1513 * have to use two instructions:
1514 *
1515 * mov(4) dst<1>:UB src<4,1,0>:UB
1516 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1517 *
1518 * where they pack the four bytes from the low and high four DW.
1519 */
1520 assert(_mesa_is_pow_two(dst.writemask) &&
1521 dst.writemask != 0);
1522 unsigned offset = __builtin_ctz(dst.writemask);
1523
1524 dst.type = BRW_REGISTER_TYPE_UB;
1525
1526 brw_set_default_access_mode(p, BRW_ALIGN_1);
1527
1528 src[0].type = BRW_REGISTER_TYPE_UB;
1529 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1530 src[0].width = BRW_WIDTH_1;
1531 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1532 dst.subnr = offset * 4;
1533 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1534 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1535 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1536 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1537
1538 src[0].subnr = 16;
1539 dst.subnr = 16 + offset * 4;
1540 insn = brw_MOV(p, dst, src[0]);
1541 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1542 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1543 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1544
1545 brw_set_default_access_mode(p, BRW_ALIGN_16);
1546 break;
1547 }
1548
1549 default:
1550 unreachable("Unsupported opcode");
1551 }
1552
1553 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1554 /* Handled dependency hints in the generator. */
1555
1556 assert(!inst->conditional_mod);
1557 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1558 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1559 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1560 "emitting more than 1 instruction");
1561
1562 brw_inst *last = &p->store[pre_emit_nr_insn];
1563
1564 if (inst->conditional_mod)
1565 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1566 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1567 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1568 }
1569 }
1570
1571 brw_set_uip_jip(p);
1572 annotation_finalize(&annotation, p->next_insn_offset);
1573
1574 #ifndef NDEBUG
1575 bool validated = brw_validate_instructions(p, 0, &annotation);
1576 #else
1577 if (unlikely(debug_flag))
1578 brw_validate_instructions(p, 0, &annotation);
1579 #endif
1580
1581 int before_size = p->next_insn_offset;
1582 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1583 int after_size = p->next_insn_offset;
1584
1585 if (unlikely(debug_flag)) {
1586 fprintf(stderr, "Native code for %s %s shader %s:\n",
1587 nir->info.label ? nir->info.label : "unnamed",
1588 _mesa_shader_stage_to_string(nir->stage), nir->info.name);
1589
1590 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles."
1591 "Compacted %d to %d bytes (%.0f%%)\n",
1592 stage_abbrev,
1593 before_size / 16, loop_count, cfg->cycle_count, before_size, after_size,
1594 100.0f * (before_size - after_size) / before_size);
1595
1596 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1597 p->devinfo);
1598 ralloc_free(annotation.mem_ctx);
1599 }
1600 assert(validated);
1601
1602 compiler->shader_debug_log(log_data,
1603 "%s vec4 shader: %d inst, %d loops, %u cycles, "
1604 "compacted %d to %d bytes.\n",
1605 stage_abbrev, before_size / 16,
1606 loop_count, cfg->cycle_count,
1607 before_size, after_size);
1608 }
1609
1610 extern "C" const unsigned *
1611 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
1612 void *log_data,
1613 void *mem_ctx,
1614 const nir_shader *nir,
1615 struct brw_vue_prog_data *prog_data,
1616 const struct cfg_t *cfg,
1617 unsigned *out_assembly_size)
1618 {
1619 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
1620 brw_init_codegen(compiler->devinfo, p, mem_ctx);
1621 brw_set_default_access_mode(p, BRW_ALIGN_16);
1622
1623 generate_code(p, compiler, log_data, nir, prog_data, cfg);
1624
1625 return brw_get_program(p, out_assembly_size);
1626 }