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[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 default:
96 unreachable("not reached");
97 }
98 break;
99
100 case UNIFORM:
101 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
102 (src[i].reg + src[i].reg_offset) / 2,
103 ((src[i].reg + src[i].reg_offset) % 2) * 4),
104 0, 4, 1);
105 brw_reg = retype(brw_reg, src[i].type);
106 brw_reg.dw1.bits.swizzle = src[i].swizzle;
107 if (src[i].abs)
108 brw_reg = brw_abs(brw_reg);
109 if (src[i].negate)
110 brw_reg = negate(brw_reg);
111
112 /* This should have been moved to pull constants. */
113 assert(!src[i].reladdr);
114 break;
115
116 case HW_REG:
117 assert(src[i].type == src[i].fixed_hw_reg.type);
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 unreachable("not reached");
128 }
129
130 return brw_reg;
131 }
132
133 vec4_generator::vec4_generator(struct brw_context *brw,
134 struct gl_shader_program *shader_prog,
135 struct gl_program *prog,
136 struct brw_vec4_prog_data *prog_data,
137 void *mem_ctx,
138 bool debug_flag)
139 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
140 mem_ctx(mem_ctx), debug_flag(debug_flag)
141 {
142 p = rzalloc(mem_ctx, struct brw_compile);
143 brw_init_compile(brw, p, mem_ctx);
144 }
145
146 vec4_generator::~vec4_generator()
147 {
148 }
149
150 void
151 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
152 struct brw_reg dst,
153 struct brw_reg src)
154 {
155 gen4_math(p,
156 dst,
157 brw_math_function(inst->opcode),
158 inst->base_mrf,
159 src,
160 BRW_MATH_DATA_VECTOR,
161 BRW_MATH_PRECISION_FULL);
162 }
163
164 static void
165 check_gen6_math_src_arg(struct brw_reg src)
166 {
167 /* Source swizzles are ignored. */
168 assert(!src.abs);
169 assert(!src.negate);
170 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
171 }
172
173 void
174 vec4_generator::generate_math_gen6(vec4_instruction *inst,
175 struct brw_reg dst,
176 struct brw_reg src0,
177 struct brw_reg src1)
178 {
179 /* Can't do writemask because math can't be align16. */
180 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0);
183 if (src1.file == BRW_GENERAL_REGISTER_FILE)
184 check_gen6_math_src_arg(src1);
185
186 brw_set_default_access_mode(p, BRW_ALIGN_1);
187 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
188 brw_set_default_access_mode(p, BRW_ALIGN_16);
189 }
190
191 void
192 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
193 struct brw_reg dst,
194 struct brw_reg src0,
195 struct brw_reg src1)
196 {
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
198 * "Message Payload":
199 *
200 * "Operand0[7]. For the INT DIV functions, this operand is the
201 * denominator."
202 * ...
203 * "Operand1[7]. For the INT DIV functions, this operand is the
204 * numerator."
205 */
206 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
207 struct brw_reg &op0 = is_int_div ? src1 : src0;
208 struct brw_reg &op1 = is_int_div ? src0 : src1;
209
210 brw_push_insn_state(p);
211 brw_set_default_saturate(p, false);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
214 brw_pop_insn_state(p);
215
216 gen4_math(p,
217 dst,
218 brw_math_function(inst->opcode),
219 inst->base_mrf,
220 op0,
221 BRW_MATH_DATA_VECTOR,
222 BRW_MATH_PRECISION_FULL);
223 }
224
225 void
226 vec4_generator::generate_tex(vec4_instruction *inst,
227 struct brw_reg dst,
228 struct brw_reg src,
229 struct brw_reg sampler_index)
230 {
231 int msg_type = -1;
232
233 if (brw->gen >= 5) {
234 switch (inst->opcode) {
235 case SHADER_OPCODE_TEX:
236 case SHADER_OPCODE_TXL:
237 if (inst->shadow_compare) {
238 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
239 } else {
240 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
241 }
242 break;
243 case SHADER_OPCODE_TXD:
244 if (inst->shadow_compare) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw->gen >= 8 || brw->is_haswell);
247 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
248 } else {
249 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
250 }
251 break;
252 case SHADER_OPCODE_TXF:
253 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
254 break;
255 case SHADER_OPCODE_TXF_CMS:
256 if (brw->gen >= 7)
257 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
258 else
259 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
260 break;
261 case SHADER_OPCODE_TXF_MCS:
262 assert(brw->gen >= 7);
263 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
264 break;
265 case SHADER_OPCODE_TXS:
266 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
267 break;
268 case SHADER_OPCODE_TG4:
269 if (inst->shadow_compare) {
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
271 } else {
272 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
273 }
274 break;
275 case SHADER_OPCODE_TG4_OFFSET:
276 if (inst->shadow_compare) {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
278 } else {
279 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
280 }
281 break;
282 default:
283 unreachable("should not get here: invalid vec4 texture opcode");
284 }
285 } else {
286 switch (inst->opcode) {
287 case SHADER_OPCODE_TEX:
288 case SHADER_OPCODE_TXL:
289 if (inst->shadow_compare) {
290 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
291 assert(inst->mlen == 3);
292 } else {
293 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
294 assert(inst->mlen == 2);
295 }
296 break;
297 case SHADER_OPCODE_TXD:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
300 assert(inst->mlen == 4);
301 break;
302 case SHADER_OPCODE_TXF:
303 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
304 assert(inst->mlen == 2);
305 break;
306 case SHADER_OPCODE_TXS:
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
308 assert(inst->mlen == 2);
309 break;
310 default:
311 unreachable("should not get here: invalid vec4 texture opcode");
312 }
313 }
314
315 assert(msg_type != -1);
316
317 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
318
319 /* Load the message header if present. If there's a texture offset, we need
320 * to set it up explicitly and load the offset bitfield. Otherwise, we can
321 * use an implied move from g0 to the first message register.
322 */
323 if (inst->header_present) {
324 if (brw->gen < 6 && !inst->texture_offset) {
325 /* Set up an implied move from g0 to the MRF. */
326 src = brw_vec8_grf(0, 0);
327 } else {
328 struct brw_reg header =
329 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
330
331 /* Explicitly set up the message header by copying g0 to the MRF. */
332 brw_push_insn_state(p);
333 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
334 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
335
336 brw_set_default_access_mode(p, BRW_ALIGN_1);
337
338 if (inst->texture_offset) {
339 /* Set the texel offset bits in DWord 2. */
340 brw_MOV(p, get_element_ud(header, 2),
341 brw_imm_ud(inst->texture_offset));
342 }
343
344 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
345 brw_pop_insn_state(p);
346 }
347 }
348
349 uint32_t return_format;
350
351 switch (dst.type) {
352 case BRW_REGISTER_TYPE_D:
353 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
354 break;
355 case BRW_REGISTER_TYPE_UD:
356 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
357 break;
358 default:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
360 break;
361 }
362
363 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
364 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
365 ? prog_data->base.binding_table.gather_texture_start
366 : prog_data->base.binding_table.texture_start;
367
368 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
369 uint32_t sampler = sampler_index.dw1.ud;
370
371 brw_SAMPLE(p,
372 dst,
373 inst->base_mrf,
374 src,
375 sampler + base_binding_table_index,
376 sampler % 16,
377 msg_type,
378 1, /* response length */
379 inst->mlen,
380 inst->header_present,
381 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
382 return_format);
383
384 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
385 } else {
386 /* XXX: Non-constant sampler index. */
387 }
388 }
389
390 void
391 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
392 {
393 brw_urb_WRITE(p,
394 brw_null_reg(), /* dest */
395 inst->base_mrf, /* starting mrf reg nr */
396 brw_vec8_grf(0, 0), /* src */
397 inst->urb_write_flags,
398 inst->mlen,
399 0, /* response len */
400 inst->offset, /* urb destination offset */
401 BRW_URB_SWIZZLE_INTERLEAVE);
402 }
403
404 void
405 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
406 {
407 struct brw_reg src = brw_message_reg(inst->base_mrf);
408 brw_urb_WRITE(p,
409 brw_null_reg(), /* dest */
410 inst->base_mrf, /* starting mrf reg nr */
411 src,
412 inst->urb_write_flags,
413 inst->mlen,
414 0, /* response len */
415 inst->offset, /* urb destination offset */
416 BRW_URB_SWIZZLE_INTERLEAVE);
417 }
418
419 void
420 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
421 {
422 struct brw_reg src = brw_message_reg(inst->base_mrf);
423 brw_urb_WRITE(p,
424 brw_null_reg(), /* dest */
425 inst->base_mrf, /* starting mrf reg nr */
426 src,
427 BRW_URB_WRITE_EOT,
428 brw->gen >= 8 ? 2 : 1,/* message len */
429 0, /* response len */
430 0, /* urb destination offset */
431 BRW_URB_SWIZZLE_INTERLEAVE);
432 }
433
434 void
435 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
436 struct brw_reg src0,
437 struct brw_reg src1)
438 {
439 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
440 * Header: M0.3):
441 *
442 * Slot 0 Offset. This field, after adding to the Global Offset field
443 * in the message descriptor, specifies the offset (in 256-bit units)
444 * from the start of the URB entry, as referenced by URB Handle 0, at
445 * which the data will be accessed.
446 *
447 * Similar text describes DWORD M0.4, which is slot 1 offset.
448 *
449 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
450 * of the register for geometry shader invocations 0 and 1) by the
451 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
452 *
453 * We can do this with the following EU instruction:
454 *
455 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
456 */
457 brw_push_insn_state(p);
458 brw_set_default_access_mode(p, BRW_ALIGN_1);
459 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
460 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
461 src1);
462 brw_set_default_access_mode(p, BRW_ALIGN_16);
463 brw_pop_insn_state(p);
464 }
465
466 void
467 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
468 struct brw_reg src)
469 {
470 brw_push_insn_state(p);
471 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
472
473 if (brw->gen >= 8) {
474 /* Move the vertex count into the second MRF for the EOT write. */
475 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
476 src);
477 } else {
478 /* If we think of the src and dst registers as composed of 8 DWORDs each,
479 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
480 * them to WORDs, and then pack them into DWORD 2 of dst.
481 *
482 * It's easier to get the EU to do this if we think of the src and dst
483 * registers as composed of 16 WORDS each; then, we want to pick up the
484 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
485 * of dst.
486 *
487 * We can do that by the following EU instruction:
488 *
489 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
490 */
491 brw_set_default_access_mode(p, BRW_ALIGN_1);
492 brw_MOV(p,
493 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
494 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
495 brw_set_default_access_mode(p, BRW_ALIGN_16);
496 }
497 brw_pop_insn_state(p);
498 }
499
500 void
501 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
502 struct brw_reg src)
503 {
504 assert(src.file == BRW_IMMEDIATE_VALUE);
505
506 brw_push_insn_state(p);
507 brw_set_default_access_mode(p, BRW_ALIGN_1);
508 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
509 brw_MOV(p, suboffset(vec1(dst), 2), src);
510 brw_set_default_access_mode(p, BRW_ALIGN_16);
511 brw_pop_insn_state(p);
512 }
513
514 void
515 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
516 {
517 /* We want to left shift just DWORD 4 (the x component belonging to the
518 * second geometry shader invocation) by 4 bits. So generate the
519 * instruction:
520 *
521 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
522 */
523 dst = suboffset(vec1(dst), 4);
524 brw_push_insn_state(p);
525 brw_set_default_access_mode(p, BRW_ALIGN_1);
526 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
527 brw_SHL(p, dst, dst, brw_imm_ud(4));
528 brw_pop_insn_state(p);
529 }
530
531 void
532 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
533 struct brw_reg src)
534 {
535 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
536 * Header: M0.5):
537 *
538 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
539 *
540 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
541 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
542 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
543 * channel enable to determine the final channel enable. For the
544 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
545 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
546 * in the writeback message. For the URB_WRITE_OWORD &
547 * URB_WRITE_HWORD messages, when final channel enable is 1 it
548 * indicates that Vertex 1 DATA [3] will be written to the surface.
549 *
550 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
551 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
552 *
553 * 14 Vertex 1 DATA [2] Channel Mask
554 * 13 Vertex 1 DATA [1] Channel Mask
555 * 12 Vertex 1 DATA [0] Channel Mask
556 * 11 Vertex 0 DATA [3] Channel Mask
557 * 10 Vertex 0 DATA [2] Channel Mask
558 * 9 Vertex 0 DATA [1] Channel Mask
559 * 8 Vertex 0 DATA [0] Channel Mask
560 *
561 * (This is from a section of the PRM that is agnostic to the particular
562 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
563 * geometry shader invocations 0 and 1, respectively). Since we have the
564 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
565 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
566 * DWORD 4, we just need to OR them together and store the result in bits
567 * 15:8 of DWORD 5.
568 *
569 * It's easier to get the EU to do this if we think of the src and dst
570 * registers as composed of 32 bytes each; then, we want to pick up the
571 * contents of bytes 0 and 16 from src, OR them together, and store them in
572 * byte 21.
573 *
574 * We can do that by the following EU instruction:
575 *
576 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
577 *
578 * Note: this relies on the source register having zeros in (a) bits 7:4 of
579 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
580 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
581 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
582 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
583 * contain valid channel mask values (which are in the range 0x0-0xf).
584 */
585 dst = retype(dst, BRW_REGISTER_TYPE_UB);
586 src = retype(src, BRW_REGISTER_TYPE_UB);
587 brw_push_insn_state(p);
588 brw_set_default_access_mode(p, BRW_ALIGN_1);
589 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
590 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
591 brw_pop_insn_state(p);
592 }
593
594 void
595 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
596 {
597 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
598 * and store into dst.0 & dst.4. So generate the instruction:
599 *
600 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
601 */
602 brw_push_insn_state(p);
603 brw_set_default_access_mode(p, BRW_ALIGN_1);
604 dst = retype(dst, BRW_REGISTER_TYPE_UD);
605 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
606 brw_SHR(p, dst, stride(r0, 1, 4, 0),
607 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
608 brw_pop_insn_state(p);
609 }
610
611 void
612 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
613 struct brw_reg index)
614 {
615 int second_vertex_offset;
616
617 if (brw->gen >= 6)
618 second_vertex_offset = 1;
619 else
620 second_vertex_offset = 16;
621
622 m1 = retype(m1, BRW_REGISTER_TYPE_D);
623
624 /* Set up M1 (message payload). Only the block offsets in M1.0 and
625 * M1.4 are used, and the rest are ignored.
626 */
627 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
628 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
629 struct brw_reg index_0 = suboffset(vec1(index), 0);
630 struct brw_reg index_4 = suboffset(vec1(index), 4);
631
632 brw_push_insn_state(p);
633 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
634 brw_set_default_access_mode(p, BRW_ALIGN_1);
635
636 brw_MOV(p, m1_0, index_0);
637
638 if (index.file == BRW_IMMEDIATE_VALUE) {
639 index_4.dw1.ud += second_vertex_offset;
640 brw_MOV(p, m1_4, index_4);
641 } else {
642 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
643 }
644
645 brw_pop_insn_state(p);
646 }
647
648 void
649 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
650 struct brw_reg dst)
651 {
652 brw_push_insn_state(p);
653 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
654 brw_set_default_access_mode(p, BRW_ALIGN_1);
655
656 struct brw_reg flags = brw_flag_reg(0, 0);
657 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
658 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
659
660 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
661 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
662 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
663
664 brw_pop_insn_state(p);
665 }
666
667 void
668 vec4_generator::generate_scratch_read(vec4_instruction *inst,
669 struct brw_reg dst,
670 struct brw_reg index)
671 {
672 struct brw_reg header = brw_vec8_grf(0, 0);
673
674 gen6_resolve_implied_move(p, &header, inst->base_mrf);
675
676 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
677 index);
678
679 uint32_t msg_type;
680
681 if (brw->gen >= 6)
682 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
683 else if (brw->gen == 5 || brw->is_g4x)
684 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
685 else
686 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
687
688 /* Each of the 8 channel enables is considered for whether each
689 * dword is written.
690 */
691 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
692 brw_set_dest(p, send, dst);
693 brw_set_src0(p, send, header);
694 if (brw->gen < 6)
695 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
696 brw_set_dp_read_message(p, send,
697 255, /* binding table index: stateless access */
698 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
699 msg_type,
700 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
701 2, /* mlen */
702 true, /* header_present */
703 1 /* rlen */);
704 }
705
706 void
707 vec4_generator::generate_scratch_write(vec4_instruction *inst,
708 struct brw_reg dst,
709 struct brw_reg src,
710 struct brw_reg index)
711 {
712 struct brw_reg header = brw_vec8_grf(0, 0);
713 bool write_commit;
714
715 /* If the instruction is predicated, we'll predicate the send, not
716 * the header setup.
717 */
718 brw_set_default_predicate_control(p, false);
719
720 gen6_resolve_implied_move(p, &header, inst->base_mrf);
721
722 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
723 index);
724
725 brw_MOV(p,
726 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
727 retype(src, BRW_REGISTER_TYPE_D));
728
729 uint32_t msg_type;
730
731 if (brw->gen >= 7)
732 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
733 else if (brw->gen == 6)
734 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
735 else
736 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
737
738 brw_set_default_predicate_control(p, inst->predicate);
739
740 /* Pre-gen6, we have to specify write commits to ensure ordering
741 * between reads and writes within a thread. Afterwards, that's
742 * guaranteed and write commits only matter for inter-thread
743 * synchronization.
744 */
745 if (brw->gen >= 6) {
746 write_commit = false;
747 } else {
748 /* The visitor set up our destination register to be g0. This
749 * means that when the next read comes along, we will end up
750 * reading from g0 and causing a block on the write commit. For
751 * write-after-read, we are relying on the value of the previous
752 * read being used (and thus blocking on completion) before our
753 * write is executed. This means we have to be careful in
754 * instruction scheduling to not violate this assumption.
755 */
756 write_commit = true;
757 }
758
759 /* Each of the 8 channel enables is considered for whether each
760 * dword is written.
761 */
762 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
763 brw_set_dest(p, send, dst);
764 brw_set_src0(p, send, header);
765 if (brw->gen < 6)
766 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
767 brw_set_dp_write_message(p, send,
768 255, /* binding table index: stateless access */
769 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
770 msg_type,
771 3, /* mlen */
772 true, /* header present */
773 false, /* not a render target write */
774 write_commit, /* rlen */
775 false, /* eot */
776 write_commit);
777 }
778
779 void
780 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
781 struct brw_reg dst,
782 struct brw_reg index,
783 struct brw_reg offset)
784 {
785 assert(index.file == BRW_IMMEDIATE_VALUE &&
786 index.type == BRW_REGISTER_TYPE_UD);
787 uint32_t surf_index = index.dw1.ud;
788
789 struct brw_reg header = brw_vec8_grf(0, 0);
790
791 gen6_resolve_implied_move(p, &header, inst->base_mrf);
792
793 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
794 offset);
795
796 uint32_t msg_type;
797
798 if (brw->gen >= 6)
799 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
800 else if (brw->gen == 5 || brw->is_g4x)
801 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
802 else
803 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
804
805 /* Each of the 8 channel enables is considered for whether each
806 * dword is written.
807 */
808 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
809 brw_set_dest(p, send, dst);
810 brw_set_src0(p, send, header);
811 if (brw->gen < 6)
812 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
813 brw_set_dp_read_message(p, send,
814 surf_index,
815 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
816 msg_type,
817 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
818 2, /* mlen */
819 true, /* header_present */
820 1 /* rlen */);
821
822 brw_mark_surface_used(&prog_data->base, surf_index);
823 }
824
825 void
826 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
827 struct brw_reg dst,
828 struct brw_reg surf_index,
829 struct brw_reg offset)
830 {
831 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
832
833 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
834
835 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
836 brw_set_dest(p, insn, dst);
837 brw_set_src0(p, insn, offset);
838 brw_set_sampler_message(p, insn,
839 surf_index.dw1.ud,
840 0, /* LD message ignores sampler unit */
841 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
842 1, /* rlen */
843 1, /* mlen */
844 false, /* no header */
845 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
846 0);
847
848 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
849
850 } else {
851
852 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
853
854 brw_push_insn_state(p);
855 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
856 brw_set_default_access_mode(p, BRW_ALIGN_1);
857
858 /* a0.0 = surf_index & 0xff */
859 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
860 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
861 brw_set_dest(p, insn_and, addr);
862 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
863 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
864
865
866 /* a0.0 |= <descriptor> */
867 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
868 brw_set_sampler_message(p, insn_or,
869 0 /* surface */,
870 0 /* sampler */,
871 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
872 1 /* rlen */,
873 1 /* mlen */,
874 false /* header */,
875 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
876 0);
877 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
878 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
879 brw_set_src0(p, insn_or, addr);
880 brw_set_dest(p, insn_or, addr);
881
882
883 /* dst = send(offset, a0.0) */
884 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
885 brw_set_dest(p, insn_send, dst);
886 brw_set_src0(p, insn_send, offset);
887 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
888
889 brw_pop_insn_state(p);
890
891 /* visitor knows more than we do about the surface limit required,
892 * so has already done marking.
893 */
894 }
895 }
896
897 void
898 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
899 struct brw_reg dst,
900 struct brw_reg atomic_op,
901 struct brw_reg surf_index)
902 {
903 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
904 atomic_op.type == BRW_REGISTER_TYPE_UD &&
905 surf_index.file == BRW_IMMEDIATE_VALUE &&
906 surf_index.type == BRW_REGISTER_TYPE_UD);
907
908 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
909 atomic_op.dw1.ud, surf_index.dw1.ud,
910 inst->mlen, 1);
911
912 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
913 }
914
915 void
916 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
917 struct brw_reg dst,
918 struct brw_reg surf_index)
919 {
920 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
921 surf_index.type == BRW_REGISTER_TYPE_UD);
922
923 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
924 surf_index.dw1.ud,
925 inst->mlen, 1);
926
927 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
928 }
929
930 /**
931 * Generate assembly for a Vec4 IR instruction.
932 *
933 * \param instruction The Vec4 IR instruction to generate code for.
934 * \param dst The destination register.
935 * \param src An array of up to three source registers.
936 */
937 void
938 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
939 struct brw_reg dst,
940 struct brw_reg *src)
941 {
942 vec4_instruction *inst = (vec4_instruction *) instruction;
943
944 if (dst.width == BRW_WIDTH_4) {
945 /* This happens in attribute fixups for "dual instanced" geometry
946 * shaders, since they use attributes that are vec4's. Since the exec
947 * width is only 4, it's essential that the caller set
948 * force_writemask_all in order to make sure the instruction is executed
949 * regardless of which channels are enabled.
950 */
951 assert(inst->force_writemask_all);
952
953 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
954 * the following register region restrictions (from Graphics BSpec:
955 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
956 * > Register Region Restrictions)
957 *
958 * 1. ExecSize must be greater than or equal to Width.
959 *
960 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
961 * to Width * HorzStride."
962 */
963 for (int i = 0; i < 3; i++) {
964 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
965 src[i] = stride(src[i], 4, 4, 1);
966 }
967 }
968
969 switch (inst->opcode) {
970 case BRW_OPCODE_MOV:
971 brw_MOV(p, dst, src[0]);
972 break;
973 case BRW_OPCODE_ADD:
974 brw_ADD(p, dst, src[0], src[1]);
975 break;
976 case BRW_OPCODE_MUL:
977 brw_MUL(p, dst, src[0], src[1]);
978 break;
979 case BRW_OPCODE_MACH:
980 brw_MACH(p, dst, src[0], src[1]);
981 break;
982
983 case BRW_OPCODE_MAD:
984 assert(brw->gen >= 6);
985 brw_MAD(p, dst, src[0], src[1], src[2]);
986 break;
987
988 case BRW_OPCODE_FRC:
989 brw_FRC(p, dst, src[0]);
990 break;
991 case BRW_OPCODE_RNDD:
992 brw_RNDD(p, dst, src[0]);
993 break;
994 case BRW_OPCODE_RNDE:
995 brw_RNDE(p, dst, src[0]);
996 break;
997 case BRW_OPCODE_RNDZ:
998 brw_RNDZ(p, dst, src[0]);
999 break;
1000
1001 case BRW_OPCODE_AND:
1002 brw_AND(p, dst, src[0], src[1]);
1003 break;
1004 case BRW_OPCODE_OR:
1005 brw_OR(p, dst, src[0], src[1]);
1006 break;
1007 case BRW_OPCODE_XOR:
1008 brw_XOR(p, dst, src[0], src[1]);
1009 break;
1010 case BRW_OPCODE_NOT:
1011 brw_NOT(p, dst, src[0]);
1012 break;
1013 case BRW_OPCODE_ASR:
1014 brw_ASR(p, dst, src[0], src[1]);
1015 break;
1016 case BRW_OPCODE_SHR:
1017 brw_SHR(p, dst, src[0], src[1]);
1018 break;
1019 case BRW_OPCODE_SHL:
1020 brw_SHL(p, dst, src[0], src[1]);
1021 break;
1022
1023 case BRW_OPCODE_CMP:
1024 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1025 break;
1026 case BRW_OPCODE_SEL:
1027 brw_SEL(p, dst, src[0], src[1]);
1028 break;
1029
1030 case BRW_OPCODE_DPH:
1031 brw_DPH(p, dst, src[0], src[1]);
1032 break;
1033
1034 case BRW_OPCODE_DP4:
1035 brw_DP4(p, dst, src[0], src[1]);
1036 break;
1037
1038 case BRW_OPCODE_DP3:
1039 brw_DP3(p, dst, src[0], src[1]);
1040 break;
1041
1042 case BRW_OPCODE_DP2:
1043 brw_DP2(p, dst, src[0], src[1]);
1044 break;
1045
1046 case BRW_OPCODE_F32TO16:
1047 assert(brw->gen >= 7);
1048 brw_F32TO16(p, dst, src[0]);
1049 break;
1050
1051 case BRW_OPCODE_F16TO32:
1052 assert(brw->gen >= 7);
1053 brw_F16TO32(p, dst, src[0]);
1054 break;
1055
1056 case BRW_OPCODE_LRP:
1057 assert(brw->gen >= 6);
1058 brw_LRP(p, dst, src[0], src[1], src[2]);
1059 break;
1060
1061 case BRW_OPCODE_BFREV:
1062 assert(brw->gen >= 7);
1063 /* BFREV only supports UD type for src and dst. */
1064 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1065 retype(src[0], BRW_REGISTER_TYPE_UD));
1066 break;
1067 case BRW_OPCODE_FBH:
1068 assert(brw->gen >= 7);
1069 /* FBH only supports UD type for dst. */
1070 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1071 break;
1072 case BRW_OPCODE_FBL:
1073 assert(brw->gen >= 7);
1074 /* FBL only supports UD type for dst. */
1075 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1076 break;
1077 case BRW_OPCODE_CBIT:
1078 assert(brw->gen >= 7);
1079 /* CBIT only supports UD type for dst. */
1080 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1081 break;
1082 case BRW_OPCODE_ADDC:
1083 assert(brw->gen >= 7);
1084 brw_ADDC(p, dst, src[0], src[1]);
1085 break;
1086 case BRW_OPCODE_SUBB:
1087 assert(brw->gen >= 7);
1088 brw_SUBB(p, dst, src[0], src[1]);
1089 break;
1090 case BRW_OPCODE_MAC:
1091 brw_MAC(p, dst, src[0], src[1]);
1092 break;
1093
1094 case BRW_OPCODE_BFE:
1095 assert(brw->gen >= 7);
1096 brw_BFE(p, dst, src[0], src[1], src[2]);
1097 break;
1098
1099 case BRW_OPCODE_BFI1:
1100 assert(brw->gen >= 7);
1101 brw_BFI1(p, dst, src[0], src[1]);
1102 break;
1103 case BRW_OPCODE_BFI2:
1104 assert(brw->gen >= 7);
1105 brw_BFI2(p, dst, src[0], src[1], src[2]);
1106 break;
1107
1108 case BRW_OPCODE_IF:
1109 if (inst->src[0].file != BAD_FILE) {
1110 /* The instruction has an embedded compare (only allowed on gen6) */
1111 assert(brw->gen == 6);
1112 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1113 } else {
1114 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1115 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1116 }
1117 break;
1118
1119 case BRW_OPCODE_ELSE:
1120 brw_ELSE(p);
1121 break;
1122 case BRW_OPCODE_ENDIF:
1123 brw_ENDIF(p);
1124 break;
1125
1126 case BRW_OPCODE_DO:
1127 brw_DO(p, BRW_EXECUTE_8);
1128 break;
1129
1130 case BRW_OPCODE_BREAK:
1131 brw_BREAK(p);
1132 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1133 break;
1134 case BRW_OPCODE_CONTINUE:
1135 brw_CONT(p);
1136 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1137 break;
1138
1139 case BRW_OPCODE_WHILE:
1140 brw_WHILE(p);
1141 break;
1142
1143 case SHADER_OPCODE_RCP:
1144 case SHADER_OPCODE_RSQ:
1145 case SHADER_OPCODE_SQRT:
1146 case SHADER_OPCODE_EXP2:
1147 case SHADER_OPCODE_LOG2:
1148 case SHADER_OPCODE_SIN:
1149 case SHADER_OPCODE_COS:
1150 if (brw->gen >= 7) {
1151 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1152 brw_null_reg());
1153 } else if (brw->gen == 6) {
1154 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1155 } else {
1156 generate_math1_gen4(inst, dst, src[0]);
1157 }
1158 break;
1159
1160 case SHADER_OPCODE_POW:
1161 case SHADER_OPCODE_INT_QUOTIENT:
1162 case SHADER_OPCODE_INT_REMAINDER:
1163 if (brw->gen >= 7) {
1164 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1165 } else if (brw->gen == 6) {
1166 generate_math_gen6(inst, dst, src[0], src[1]);
1167 } else {
1168 generate_math2_gen4(inst, dst, src[0], src[1]);
1169 }
1170 break;
1171
1172 case SHADER_OPCODE_TEX:
1173 case SHADER_OPCODE_TXD:
1174 case SHADER_OPCODE_TXF:
1175 case SHADER_OPCODE_TXF_CMS:
1176 case SHADER_OPCODE_TXF_MCS:
1177 case SHADER_OPCODE_TXL:
1178 case SHADER_OPCODE_TXS:
1179 case SHADER_OPCODE_TG4:
1180 case SHADER_OPCODE_TG4_OFFSET:
1181 generate_tex(inst, dst, src[0], src[1]);
1182 break;
1183
1184 case VS_OPCODE_URB_WRITE:
1185 generate_vs_urb_write(inst);
1186 break;
1187
1188 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1189 generate_scratch_read(inst, dst, src[0]);
1190 break;
1191
1192 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1193 generate_scratch_write(inst, dst, src[0], src[1]);
1194 break;
1195
1196 case VS_OPCODE_PULL_CONSTANT_LOAD:
1197 generate_pull_constant_load(inst, dst, src[0], src[1]);
1198 break;
1199
1200 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1201 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1202 break;
1203
1204 case GS_OPCODE_URB_WRITE:
1205 generate_gs_urb_write(inst);
1206 break;
1207
1208 case GS_OPCODE_THREAD_END:
1209 generate_gs_thread_end(inst);
1210 break;
1211
1212 case GS_OPCODE_SET_WRITE_OFFSET:
1213 generate_gs_set_write_offset(dst, src[0], src[1]);
1214 break;
1215
1216 case GS_OPCODE_SET_VERTEX_COUNT:
1217 generate_gs_set_vertex_count(dst, src[0]);
1218 break;
1219
1220 case GS_OPCODE_SET_DWORD_2_IMMED:
1221 generate_gs_set_dword_2_immed(dst, src[0]);
1222 break;
1223
1224 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1225 generate_gs_prepare_channel_masks(dst);
1226 break;
1227
1228 case GS_OPCODE_SET_CHANNEL_MASKS:
1229 generate_gs_set_channel_masks(dst, src[0]);
1230 break;
1231
1232 case GS_OPCODE_GET_INSTANCE_ID:
1233 generate_gs_get_instance_id(dst);
1234 break;
1235
1236 case SHADER_OPCODE_SHADER_TIME_ADD:
1237 brw_shader_time_add(p, src[0],
1238 prog_data->base.binding_table.shader_time_start);
1239 brw_mark_surface_used(&prog_data->base,
1240 prog_data->base.binding_table.shader_time_start);
1241 break;
1242
1243 case SHADER_OPCODE_UNTYPED_ATOMIC:
1244 generate_untyped_atomic(inst, dst, src[0], src[1]);
1245 break;
1246
1247 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1248 generate_untyped_surface_read(inst, dst, src[0]);
1249 break;
1250
1251 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1252 generate_unpack_flags(inst, dst);
1253 break;
1254
1255 default:
1256 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1257 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1258 opcode_descs[inst->opcode].name);
1259 } else {
1260 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1261 }
1262 abort();
1263 }
1264 }
1265
1266 void
1267 vec4_generator::generate_code(exec_list *instructions)
1268 {
1269 struct annotation_info annotation;
1270 memset(&annotation, 0, sizeof(annotation));
1271
1272 cfg_t *cfg = NULL;
1273 if (unlikely(debug_flag))
1274 cfg = new(mem_ctx) cfg_t(instructions);
1275
1276 foreach_in_list(vec4_instruction, inst, instructions) {
1277 struct brw_reg src[3], dst;
1278
1279 if (unlikely(debug_flag))
1280 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1281
1282 for (unsigned int i = 0; i < 3; i++) {
1283 src[i] = inst->get_src(this->prog_data, i);
1284 }
1285 dst = inst->get_dst();
1286
1287 brw_set_default_predicate_control(p, inst->predicate);
1288 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1289 brw_set_default_saturate(p, inst->saturate);
1290 brw_set_default_mask_control(p, inst->force_writemask_all);
1291 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1292
1293 unsigned pre_emit_nr_insn = p->nr_insn;
1294
1295 generate_vec4_instruction(inst, dst, src);
1296
1297 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1298 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1299 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1300 "emitting more than 1 instruction");
1301
1302 brw_inst *last = &p->store[pre_emit_nr_insn];
1303
1304 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1305 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1306 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1307 }
1308 }
1309
1310 brw_set_uip_jip(p);
1311 annotation_finalize(&annotation, p->next_insn_offset);
1312
1313 int before_size = p->next_insn_offset;
1314 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1315 int after_size = p->next_insn_offset;
1316
1317 if (unlikely(debug_flag)) {
1318 if (shader_prog) {
1319 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1320 shader_prog->Label ? shader_prog->Label : "unnamed",
1321 shader_prog->Name);
1322 } else {
1323 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1324 }
1325 fprintf(stderr, "vec4 shader: %d instructions. Compacted %d to %d"
1326 " bytes (%.0f%%)\n",
1327 before_size / 16, before_size, after_size,
1328 100.0f * (before_size - after_size) / before_size);
1329
1330 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1331 ralloc_free(annotation.ann);
1332 }
1333 }
1334
1335 const unsigned *
1336 vec4_generator::generate_assembly(exec_list *instructions,
1337 unsigned *assembly_size)
1338 {
1339 brw_set_default_access_mode(p, BRW_ALIGN_16);
1340 generate_code(instructions);
1341
1342 return brw_get_program(p, assembly_size);
1343 }
1344
1345 } /* namespace brw */