projects / mesa.git / blob
? search:


5d91e0f526046fffd39b16e5da2b643fdcba5af8
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "glsl/glsl_parser_extras.h"
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26 #include "brw_eu.h"
27 #include "brw_program.h"
28
29 using namespace brw;
30
31 static void
32 generate_math1_gen4(struct brw_codegen *p,
33 vec4_instruction *inst,
34 struct brw_reg dst,
35 struct brw_reg src)
36 {
37 gen4_math(p,
38 dst,
39 brw_math_function(inst->opcode),
40 inst->base_mrf,
41 src,
42 BRW_MATH_PRECISION_FULL);
43 }
44
45 static void
46 check_gen6_math_src_arg(struct brw_reg src)
47 {
48 /* Source swizzles are ignored. */
49 assert(!src.abs);
50 assert(!src.negate);
51 assert(src.swizzle == BRW_SWIZZLE_XYZW);
52 }
53
54 static void
55 generate_math_gen6(struct brw_codegen *p,
56 vec4_instruction *inst,
57 struct brw_reg dst,
58 struct brw_reg src0,
59 struct brw_reg src1)
60 {
61 /* Can't do writemask because math can't be align16. */
62 assert(dst.writemask == WRITEMASK_XYZW);
63 /* Source swizzles are ignored. */
64 check_gen6_math_src_arg(src0);
65 if (src1.file == BRW_GENERAL_REGISTER_FILE)
66 check_gen6_math_src_arg(src1);
67
68 brw_set_default_access_mode(p, BRW_ALIGN_1);
69 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
70 brw_set_default_access_mode(p, BRW_ALIGN_16);
71 }
72
73 static void
74 generate_math2_gen4(struct brw_codegen *p,
75 vec4_instruction *inst,
76 struct brw_reg dst,
77 struct brw_reg src0,
78 struct brw_reg src1)
79 {
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
81 * "Message Payload":
82 *
83 * "Operand0[7]. For the INT DIV functions, this operand is the
84 * denominator."
85 * ...
86 * "Operand1[7]. For the INT DIV functions, this operand is the
87 * numerator."
88 */
89 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
90 struct brw_reg &op0 = is_int_div ? src1 : src0;
91 struct brw_reg &op1 = is_int_div ? src0 : src1;
92
93 brw_push_insn_state(p);
94 brw_set_default_saturate(p, false);
95 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
96 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
97 brw_pop_insn_state(p);
98
99 gen4_math(p,
100 dst,
101 brw_math_function(inst->opcode),
102 inst->base_mrf,
103 op0,
104 BRW_MATH_PRECISION_FULL);
105 }
106
107 static void
108 generate_tex(struct brw_codegen *p,
109 struct brw_vue_prog_data *prog_data,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg sampler_index)
114 {
115 const struct brw_device_info *devinfo = p->devinfo;
116 int msg_type = -1;
117
118 if (devinfo->gen >= 5) {
119 switch (inst->opcode) {
120 case SHADER_OPCODE_TEX:
121 case SHADER_OPCODE_TXL:
122 if (inst->shadow_compare) {
123 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
124 } else {
125 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
126 }
127 break;
128 case SHADER_OPCODE_TXD:
129 if (inst->shadow_compare) {
130 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
131 assert(devinfo->gen >= 8 || devinfo->is_haswell);
132 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
133 } else {
134 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
135 }
136 break;
137 case SHADER_OPCODE_TXF:
138 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
139 break;
140 case SHADER_OPCODE_TXF_CMS_W:
141 assert(devinfo->gen >= 9);
142 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
143 break;
144 case SHADER_OPCODE_TXF_CMS:
145 if (devinfo->gen >= 7)
146 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
147 else
148 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
149 break;
150 case SHADER_OPCODE_TXF_MCS:
151 assert(devinfo->gen >= 7);
152 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
153 break;
154 case SHADER_OPCODE_TXS:
155 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
156 break;
157 case SHADER_OPCODE_TG4:
158 if (inst->shadow_compare) {
159 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
160 } else {
161 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
162 }
163 break;
164 case SHADER_OPCODE_TG4_OFFSET:
165 if (inst->shadow_compare) {
166 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
167 } else {
168 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
169 }
170 break;
171 case SHADER_OPCODE_SAMPLEINFO:
172 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
173 break;
174 default:
175 unreachable("should not get here: invalid vec4 texture opcode");
176 }
177 } else {
178 switch (inst->opcode) {
179 case SHADER_OPCODE_TEX:
180 case SHADER_OPCODE_TXL:
181 if (inst->shadow_compare) {
182 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
183 assert(inst->mlen == 3);
184 } else {
185 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
186 assert(inst->mlen == 2);
187 }
188 break;
189 case SHADER_OPCODE_TXD:
190 /* There is no sample_d_c message; comparisons are done manually. */
191 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
192 assert(inst->mlen == 4);
193 break;
194 case SHADER_OPCODE_TXF:
195 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
196 assert(inst->mlen == 2);
197 break;
198 case SHADER_OPCODE_TXS:
199 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
200 assert(inst->mlen == 2);
201 break;
202 default:
203 unreachable("should not get here: invalid vec4 texture opcode");
204 }
205 }
206
207 assert(msg_type != -1);
208
209 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
210
211 /* Load the message header if present. If there's a texture offset, we need
212 * to set it up explicitly and load the offset bitfield. Otherwise, we can
213 * use an implied move from g0 to the first message register.
214 */
215 if (inst->header_size != 0) {
216 if (devinfo->gen < 6 && !inst->offset) {
217 /* Set up an implied move from g0 to the MRF. */
218 src = brw_vec8_grf(0, 0);
219 } else {
220 struct brw_reg header =
221 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
222 uint32_t dw2 = 0;
223
224 /* Explicitly set up the message header by copying g0 to the MRF. */
225 brw_push_insn_state(p);
226 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
227 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
228
229 brw_set_default_access_mode(p, BRW_ALIGN_1);
230
231 if (inst->offset)
232 /* Set the texel offset bits in DWord 2. */
233 dw2 = inst->offset;
234
235 if (devinfo->gen >= 9)
236 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
237 * based on bit 22 in the header.
238 */
239 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
240
241 if (dw2)
242 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
243
244 brw_adjust_sampler_state_pointer(p, header, sampler_index);
245 brw_pop_insn_state(p);
246 }
247 }
248
249 uint32_t return_format;
250
251 switch (dst.type) {
252 case BRW_REGISTER_TYPE_D:
253 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
254 break;
255 case BRW_REGISTER_TYPE_UD:
256 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
257 break;
258 default:
259 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
260 break;
261 }
262
263 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
264 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
265 ? prog_data->base.binding_table.gather_texture_start
266 : prog_data->base.binding_table.texture_start;
267
268 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
269 uint32_t sampler = sampler_index.ud;
270
271 brw_SAMPLE(p,
272 dst,
273 inst->base_mrf,
274 src,
275 sampler + base_binding_table_index,
276 sampler % 16,
277 msg_type,
278 1, /* response length */
279 inst->mlen,
280 inst->header_size != 0,
281 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
282 return_format);
283
284 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
285 } else {
286 /* Non-constant sampler index. */
287
288 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
289 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
290
291 brw_push_insn_state(p);
292 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
293 brw_set_default_access_mode(p, BRW_ALIGN_1);
294
295 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
296 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
297 if (base_binding_table_index)
298 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
299 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
300
301 brw_pop_insn_state(p);
302
303 if (inst->base_mrf != -1)
304 gen6_resolve_implied_move(p, &src, inst->base_mrf);
305
306 /* dst = send(offset, a0.0 | <descriptor>) */
307 brw_inst *insn = brw_send_indirect_message(
308 p, BRW_SFID_SAMPLER, dst, src, addr);
309 brw_set_sampler_message(p, insn,
310 0 /* surface */,
311 0 /* sampler */,
312 msg_type,
313 1 /* rlen */,
314 inst->mlen /* mlen */,
315 inst->header_size != 0 /* header */,
316 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
317 return_format);
318
319 /* visitor knows more than we do about the surface limit required,
320 * so has already done marking.
321 */
322 }
323 }
324
325 static void
326 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
327 {
328 brw_urb_WRITE(p,
329 brw_null_reg(), /* dest */
330 inst->base_mrf, /* starting mrf reg nr */
331 brw_vec8_grf(0, 0), /* src */
332 inst->urb_write_flags,
333 inst->mlen,
334 0, /* response len */
335 inst->offset, /* urb destination offset */
336 BRW_URB_SWIZZLE_INTERLEAVE);
337 }
338
339 static void
340 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
341 {
342 struct brw_reg src = brw_message_reg(inst->base_mrf);
343 brw_urb_WRITE(p,
344 brw_null_reg(), /* dest */
345 inst->base_mrf, /* starting mrf reg nr */
346 src,
347 inst->urb_write_flags,
348 inst->mlen,
349 0, /* response len */
350 inst->offset, /* urb destination offset */
351 BRW_URB_SWIZZLE_INTERLEAVE);
352 }
353
354 static void
355 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
356 {
357 struct brw_reg src = brw_message_reg(inst->base_mrf);
358
359 /* We pass the temporary passed in src0 as the writeback register */
360 brw_urb_WRITE(p,
361 inst->src[0].as_brw_reg(), /* dest */
362 inst->base_mrf, /* starting mrf reg nr */
363 src,
364 BRW_URB_WRITE_ALLOCATE_COMPLETE,
365 inst->mlen,
366 1, /* response len */
367 inst->offset, /* urb destination offset */
368 BRW_URB_SWIZZLE_INTERLEAVE);
369
370 /* Now put allocated urb handle in dst.0 */
371 brw_push_insn_state(p);
372 brw_set_default_access_mode(p, BRW_ALIGN_1);
373 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
374 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
375 get_element_ud(inst->src[0].as_brw_reg(), 0));
376 brw_pop_insn_state(p);
377 }
378
379 static void
380 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
381 {
382 struct brw_reg src = brw_message_reg(inst->base_mrf);
383 brw_urb_WRITE(p,
384 brw_null_reg(), /* dest */
385 inst->base_mrf, /* starting mrf reg nr */
386 src,
387 BRW_URB_WRITE_EOT | inst->urb_write_flags,
388 inst->mlen,
389 0, /* response len */
390 0, /* urb destination offset */
391 BRW_URB_SWIZZLE_INTERLEAVE);
392 }
393
394 static void
395 generate_gs_set_write_offset(struct brw_codegen *p,
396 struct brw_reg dst,
397 struct brw_reg src0,
398 struct brw_reg src1)
399 {
400 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
401 * Header: M0.3):
402 *
403 * Slot 0 Offset. This field, after adding to the Global Offset field
404 * in the message descriptor, specifies the offset (in 256-bit units)
405 * from the start of the URB entry, as referenced by URB Handle 0, at
406 * which the data will be accessed.
407 *
408 * Similar text describes DWORD M0.4, which is slot 1 offset.
409 *
410 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
411 * of the register for geometry shader invocations 0 and 1) by the
412 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
413 *
414 * We can do this with the following EU instruction:
415 *
416 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
417 */
418 brw_push_insn_state(p);
419 brw_set_default_access_mode(p, BRW_ALIGN_1);
420 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
421 assert(p->devinfo->gen >= 7 &&
422 src1.file == BRW_IMMEDIATE_VALUE &&
423 src1.type == BRW_REGISTER_TYPE_UD &&
424 src1.ud <= USHRT_MAX);
425 if (src0.file == BRW_IMMEDIATE_VALUE) {
426 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
427 brw_imm_ud(src0.ud * src1.ud));
428 } else {
429 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
430 retype(src1, BRW_REGISTER_TYPE_UW));
431 }
432 brw_pop_insn_state(p);
433 }
434
435 static void
436 generate_gs_set_vertex_count(struct brw_codegen *p,
437 struct brw_reg dst,
438 struct brw_reg src)
439 {
440 brw_push_insn_state(p);
441 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
442
443 if (p->devinfo->gen >= 8) {
444 /* Move the vertex count into the second MRF for the EOT write. */
445 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
446 src);
447 } else {
448 /* If we think of the src and dst registers as composed of 8 DWORDs each,
449 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
450 * them to WORDs, and then pack them into DWORD 2 of dst.
451 *
452 * It's easier to get the EU to do this if we think of the src and dst
453 * registers as composed of 16 WORDS each; then, we want to pick up the
454 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
455 * of dst.
456 *
457 * We can do that by the following EU instruction:
458 *
459 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
460 */
461 brw_set_default_access_mode(p, BRW_ALIGN_1);
462 brw_MOV(p,
463 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
464 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
465 }
466 brw_pop_insn_state(p);
467 }
468
469 static void
470 generate_gs_svb_write(struct brw_codegen *p,
471 struct brw_vue_prog_data *prog_data,
472 vec4_instruction *inst,
473 struct brw_reg dst,
474 struct brw_reg src0,
475 struct brw_reg src1)
476 {
477 int binding = inst->sol_binding;
478 bool final_write = inst->sol_final_write;
479
480 brw_push_insn_state(p);
481 /* Copy Vertex data into M0.x */
482 brw_MOV(p, stride(dst, 4, 4, 1),
483 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
484
485 /* Send SVB Write */
486 brw_svb_write(p,
487 final_write ? src1 : brw_null_reg(), /* dest == src1 */
488 1, /* msg_reg_nr */
489 dst, /* src0 == previous dst */
490 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
491 final_write); /* send_commit_msg */
492
493 /* Finally, wait for the write commit to occur so that we can proceed to
494 * other things safely.
495 *
496 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
497 *
498 * The write commit does not modify the destination register, but
499 * merely clears the dependency associated with the destination
500 * register. Thus, a simple “mov” instruction using the register as a
501 * source is sufficient to wait for the write commit to occur.
502 */
503 if (final_write) {
504 brw_MOV(p, src1, src1);
505 }
506 brw_pop_insn_state(p);
507 }
508
509 static void
510 generate_gs_svb_set_destination_index(struct brw_codegen *p,
511 vec4_instruction *inst,
512 struct brw_reg dst,
513 struct brw_reg src)
514 {
515 int vertex = inst->sol_vertex;
516 brw_push_insn_state(p);
517 brw_set_default_access_mode(p, BRW_ALIGN_1);
518 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
519 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
520 brw_pop_insn_state(p);
521 }
522
523 static void
524 generate_gs_set_dword_2(struct brw_codegen *p,
525 struct brw_reg dst,
526 struct brw_reg src)
527 {
528 brw_push_insn_state(p);
529 brw_set_default_access_mode(p, BRW_ALIGN_1);
530 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
531 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
532 brw_pop_insn_state(p);
533 }
534
535 static void
536 generate_gs_prepare_channel_masks(struct brw_codegen *p,
537 struct brw_reg dst)
538 {
539 /* We want to left shift just DWORD 4 (the x component belonging to the
540 * second geometry shader invocation) by 4 bits. So generate the
541 * instruction:
542 *
543 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
544 */
545 dst = suboffset(vec1(dst), 4);
546 brw_push_insn_state(p);
547 brw_set_default_access_mode(p, BRW_ALIGN_1);
548 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
549 brw_SHL(p, dst, dst, brw_imm_ud(4));
550 brw_pop_insn_state(p);
551 }
552
553 static void
554 generate_gs_set_channel_masks(struct brw_codegen *p,
555 struct brw_reg dst,
556 struct brw_reg src)
557 {
558 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
559 * Header: M0.5):
560 *
561 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
562 *
563 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
564 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
565 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
566 * channel enable to determine the final channel enable. For the
567 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
568 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
569 * in the writeback message. For the URB_WRITE_OWORD &
570 * URB_WRITE_HWORD messages, when final channel enable is 1 it
571 * indicates that Vertex 1 DATA [3] will be written to the surface.
572 *
573 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
574 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
575 *
576 * 14 Vertex 1 DATA [2] Channel Mask
577 * 13 Vertex 1 DATA [1] Channel Mask
578 * 12 Vertex 1 DATA [0] Channel Mask
579 * 11 Vertex 0 DATA [3] Channel Mask
580 * 10 Vertex 0 DATA [2] Channel Mask
581 * 9 Vertex 0 DATA [1] Channel Mask
582 * 8 Vertex 0 DATA [0] Channel Mask
583 *
584 * (This is from a section of the PRM that is agnostic to the particular
585 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
586 * geometry shader invocations 0 and 1, respectively). Since we have the
587 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
588 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
589 * DWORD 4, we just need to OR them together and store the result in bits
590 * 15:8 of DWORD 5.
591 *
592 * It's easier to get the EU to do this if we think of the src and dst
593 * registers as composed of 32 bytes each; then, we want to pick up the
594 * contents of bytes 0 and 16 from src, OR them together, and store them in
595 * byte 21.
596 *
597 * We can do that by the following EU instruction:
598 *
599 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
600 *
601 * Note: this relies on the source register having zeros in (a) bits 7:4 of
602 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
603 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
604 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
605 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
606 * contain valid channel mask values (which are in the range 0x0-0xf).
607 */
608 dst = retype(dst, BRW_REGISTER_TYPE_UB);
609 src = retype(src, BRW_REGISTER_TYPE_UB);
610 brw_push_insn_state(p);
611 brw_set_default_access_mode(p, BRW_ALIGN_1);
612 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
613 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
614 brw_pop_insn_state(p);
615 }
616
617 static void
618 generate_gs_get_instance_id(struct brw_codegen *p,
619 struct brw_reg dst)
620 {
621 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
622 * and store into dst.0 & dst.4. So generate the instruction:
623 *
624 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
625 */
626 brw_push_insn_state(p);
627 brw_set_default_access_mode(p, BRW_ALIGN_1);
628 dst = retype(dst, BRW_REGISTER_TYPE_UD);
629 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
630 brw_SHR(p, dst, stride(r0, 1, 4, 0),
631 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
632 brw_pop_insn_state(p);
633 }
634
635 static void
636 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
637 struct brw_reg dst,
638 struct brw_reg src0,
639 struct brw_reg src1,
640 struct brw_reg src2)
641 {
642 brw_push_insn_state(p);
643 brw_set_default_access_mode(p, BRW_ALIGN_1);
644 /* Save src0 data in 16:31 bits of dst.0 */
645 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
646 brw_imm_ud(0xffffu));
647 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
648 /* Save src1 data in 0:15 bits of dst.0 */
649 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
650 brw_imm_ud(0xffffu));
651 brw_OR(p, suboffset(vec1(dst), 0),
652 suboffset(vec1(dst), 0),
653 suboffset(vec1(src2), 0));
654 brw_pop_insn_state(p);
655 }
656
657 static void
658 generate_gs_ff_sync(struct brw_codegen *p,
659 vec4_instruction *inst,
660 struct brw_reg dst,
661 struct brw_reg src0,
662 struct brw_reg src1)
663 {
664 /* This opcode uses an implied MRF register for:
665 * - the header of the ff_sync message. And as such it is expected to be
666 * initialized to r0 before calling here.
667 * - the destination where we will write the allocated URB handle.
668 */
669 struct brw_reg header =
670 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
671
672 /* Overwrite dword 0 of the header (SO vertices to write) and
673 * dword 1 (number of primitives written).
674 */
675 brw_push_insn_state(p);
676 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
677 brw_set_default_access_mode(p, BRW_ALIGN_1);
678 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
679 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
680 brw_pop_insn_state(p);
681
682 /* Allocate URB handle in dst */
683 brw_ff_sync(p,
684 dst,
685 0,
686 header,
687 1, /* allocate */
688 1, /* response length */
689 0 /* eot */);
690
691 /* Now put allocated urb handle in header.0 */
692 brw_push_insn_state(p);
693 brw_set_default_access_mode(p, BRW_ALIGN_1);
694 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
695 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
696
697 /* src1 is not an immediate when we use transform feedback */
698 if (src1.file != BRW_IMMEDIATE_VALUE)
699 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
700
701 brw_pop_insn_state(p);
702 }
703
704 static void
705 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
706 {
707 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
708 struct brw_reg src = brw_vec8_grf(0, 0);
709 brw_push_insn_state(p);
710 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
711 brw_set_default_access_mode(p, BRW_ALIGN_1);
712 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
713 brw_pop_insn_state(p);
714 }
715
716 static void
717 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
718 {
719 const struct brw_device_info *devinfo = p->devinfo;
720 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
721
722 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
723 *
724 * Since we operate in SIMD4x2 mode, we need run half as many threads
725 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
726 * shift right by one less to accomplish the multiplication by two.
727 */
728 dst = retype(dst, BRW_REGISTER_TYPE_UD);
729 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
730
731 brw_push_insn_state(p);
732 brw_set_default_access_mode(p, BRW_ALIGN_1);
733
734 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
735 const int shift = ivb ? 16 : 17;
736
737 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
738 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
739 brw_imm_ud(shift - 1));
740 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
741
742 brw_pop_insn_state(p);
743 }
744
745 static void
746 generate_tcs_urb_write(struct brw_codegen *p,
747 vec4_instruction *inst,
748 struct brw_reg urb_header)
749 {
750 const struct brw_device_info *devinfo = p->devinfo;
751
752 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
753 brw_set_dest(p, send, brw_null_reg());
754 brw_set_src0(p, send, urb_header);
755
756 brw_set_message_descriptor(p, send, BRW_SFID_URB,
757 inst->mlen /* mlen */, 0 /* rlen */,
758 true /* header */, false /* eot */);
759 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
760 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
761 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
762 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
763
764 /* what happens to swizzles? */
765 }
766
767
768 static void
769 generate_tcs_input_urb_offsets(struct brw_codegen *p,
770 struct brw_reg dst,
771 struct brw_reg vertex,
772 struct brw_reg offset)
773 {
774 /* Generates an URB read/write message header for HS/DS operation.
775 * Inputs are a vertex index, and a byte offset from the beginning of
776 * the vertex. */
777
778 /* If `vertex` is not an immediate, we clobber a0.0 */
779
780 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
781 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
782
783 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
784
785 brw_push_insn_state(p);
786 brw_set_default_access_mode(p, BRW_ALIGN_1);
787 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
788 brw_MOV(p, dst, brw_imm_ud(0));
789
790 /* m0.5 bits 8-15 are channel enables */
791 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
792
793 /* m0.0-0.1: URB handles */
794 if (vertex.file == BRW_IMMEDIATE_VALUE) {
795 uint32_t vertex_index = vertex.ud;
796 struct brw_reg index_reg = brw_vec1_grf(
797 1 + (vertex_index >> 3), vertex_index & 7);
798
799 brw_MOV(p, vec2(get_element_ud(dst, 0)),
800 retype(index_reg, BRW_REGISTER_TYPE_UD));
801 } else {
802 /* Use indirect addressing. ICP Handles are DWords (single channels
803 * of a register) and start at g1.0.
804 *
805 * In order to start our region at g1.0, we add 8 to the vertex index,
806 * effectively skipping over the 8 channels in g0.0. This gives us a
807 * DWord offset to the ICP Handle.
808 *
809 * Indirect addressing works in terms of bytes, so we then multiply
810 * the DWord offset by 4 (by shifting left by 2).
811 */
812 struct brw_reg addr = brw_address_reg(0);
813
814 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
815 brw_ADD(p, addr, get_element_ud(vertex, 0), brw_imm_uw(0x8));
816 brw_SHL(p, addr, addr, brw_imm_ud(2));
817 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
818
819 /* top half: m0.1 = g[1.0 + vertex.4]UD */
820 brw_ADD(p, addr, get_element_ud(vertex, 4), brw_imm_uw(0x8));
821 brw_SHL(p, addr, addr, brw_imm_ud(2));
822 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
823 }
824
825 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
826 if (offset.file != ARF)
827 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
828
829 brw_pop_insn_state(p);
830 }
831
832
833 static void
834 generate_tcs_output_urb_offsets(struct brw_codegen *p,
835 struct brw_reg dst,
836 struct brw_reg write_mask,
837 struct brw_reg offset)
838 {
839 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
840 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
841
842 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
843 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
844
845 brw_push_insn_state(p);
846
847 brw_set_default_access_mode(p, BRW_ALIGN_1);
848 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
849 brw_MOV(p, dst, brw_imm_ud(0));
850
851 unsigned mask = write_mask.ud;
852
853 /* m0.5 bits 15:12 and 11:8 are channel enables */
854 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
855
856 /* HS patch URB handle is delivered in r0.0 */
857 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
858
859 /* m0.0-0.1: URB handles */
860 brw_MOV(p, vec2(get_element_ud(dst, 0)),
861 retype(urb_handle, BRW_REGISTER_TYPE_UD));
862
863 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
864 if (offset.file != ARF)
865 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
866
867 brw_pop_insn_state(p);
868 }
869
870 static void
871 generate_tes_create_input_read_header(struct brw_codegen *p,
872 struct brw_reg dst)
873 {
874 brw_push_insn_state(p);
875 brw_set_default_access_mode(p, BRW_ALIGN_1);
876 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
877
878 /* Initialize the register to 0 */
879 brw_MOV(p, dst, brw_imm_ud(0));
880
881 /* Enable all the channels in m0.5 bits 15:8 */
882 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
883
884 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
885 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
886 */
887 brw_AND(p, vec2(get_element_ud(dst, 0)),
888 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
889 brw_imm_ud(0x1fff));
890 brw_pop_insn_state(p);
891 }
892
893 static void
894 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
895 struct brw_reg dst,
896 struct brw_reg header,
897 struct brw_reg offset)
898 {
899 brw_push_insn_state(p);
900 brw_set_default_access_mode(p, BRW_ALIGN_1);
901 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
902
903 brw_MOV(p, dst, header);
904 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
905 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
906
907 brw_pop_insn_state(p);
908 }
909
910 static void
911 generate_vec4_urb_read(struct brw_codegen *p,
912 vec4_instruction *inst,
913 struct brw_reg dst,
914 struct brw_reg header)
915 {
916 const struct brw_device_info *devinfo = p->devinfo;
917
918 assert(header.file == BRW_GENERAL_REGISTER_FILE);
919 assert(header.type == BRW_REGISTER_TYPE_UD);
920
921 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
922 brw_set_dest(p, send, dst);
923 brw_set_src0(p, send, header);
924
925 brw_set_message_descriptor(p, send, BRW_SFID_URB,
926 1 /* mlen */, 1 /* rlen */,
927 true /* header */, false /* eot */);
928 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
929 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
930 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
931
932 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
933 }
934
935 static void
936 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
937 {
938 brw_push_insn_state(p);
939 brw_set_default_access_mode(p, BRW_ALIGN_1);
940 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
941 brw_pop_insn_state(p);
942 }
943
944 static void
945 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
946 {
947 brw_push_insn_state(p);
948 brw_set_default_access_mode(p, BRW_ALIGN_1);
949 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
950 brw_pop_insn_state(p);
951 }
952
953 static void
954 generate_tcs_create_barrier_header(struct brw_codegen *p,
955 struct brw_vue_prog_data *prog_data,
956 struct brw_reg dst)
957 {
958 struct brw_reg m0_2 = get_element_ud(dst, 2);
959 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
960
961 brw_push_insn_state(p);
962 brw_set_default_access_mode(p, BRW_ALIGN_1);
963 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
964
965 /* Zero the message header */
966 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
967
968 /* Copy "Barrier ID" from DW0 bits 16:13 */
969 brw_AND(p, m0_2,
970 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
971 brw_imm_ud(0x1e000));
972
973 /* Shift it into place */
974 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(11));
975
976 /* Set the Barrier Count and the enable bit */
977 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
978
979 brw_pop_insn_state(p);
980 }
981
982 static void
983 generate_oword_dual_block_offsets(struct brw_codegen *p,
984 struct brw_reg m1,
985 struct brw_reg index)
986 {
987 int second_vertex_offset;
988
989 if (p->devinfo->gen >= 6)
990 second_vertex_offset = 1;
991 else
992 second_vertex_offset = 16;
993
994 m1 = retype(m1, BRW_REGISTER_TYPE_D);
995
996 /* Set up M1 (message payload). Only the block offsets in M1.0 and
997 * M1.4 are used, and the rest are ignored.
998 */
999 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1000 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1001 struct brw_reg index_0 = suboffset(vec1(index), 0);
1002 struct brw_reg index_4 = suboffset(vec1(index), 4);
1003
1004 brw_push_insn_state(p);
1005 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1006 brw_set_default_access_mode(p, BRW_ALIGN_1);
1007
1008 brw_MOV(p, m1_0, index_0);
1009
1010 if (index.file == BRW_IMMEDIATE_VALUE) {
1011 index_4.ud += second_vertex_offset;
1012 brw_MOV(p, m1_4, index_4);
1013 } else {
1014 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1015 }
1016
1017 brw_pop_insn_state(p);
1018 }
1019
1020 static void
1021 generate_unpack_flags(struct brw_codegen *p,
1022 struct brw_reg dst)
1023 {
1024 brw_push_insn_state(p);
1025 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1026 brw_set_default_access_mode(p, BRW_ALIGN_1);
1027
1028 struct brw_reg flags = brw_flag_reg(0, 0);
1029 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1030 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1031
1032 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1033 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1034 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1035
1036 brw_pop_insn_state(p);
1037 }
1038
1039 static void
1040 generate_scratch_read(struct brw_codegen *p,
1041 vec4_instruction *inst,
1042 struct brw_reg dst,
1043 struct brw_reg index)
1044 {
1045 const struct brw_device_info *devinfo = p->devinfo;
1046 struct brw_reg header = brw_vec8_grf(0, 0);
1047
1048 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1049
1050 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1051 index);
1052
1053 uint32_t msg_type;
1054
1055 if (devinfo->gen >= 6)
1056 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1057 else if (devinfo->gen == 5 || devinfo->is_g4x)
1058 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1059 else
1060 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1061
1062 /* Each of the 8 channel enables is considered for whether each
1063 * dword is written.
1064 */
1065 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1066 brw_set_dest(p, send, dst);
1067 brw_set_src0(p, send, header);
1068 if (devinfo->gen < 6)
1069 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1070 brw_set_dp_read_message(p, send,
1071 brw_scratch_surface_idx(p),
1072 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1073 msg_type,
1074 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
1075 2, /* mlen */
1076 true, /* header_present */
1077 1 /* rlen */);
1078 }
1079
1080 static void
1081 generate_scratch_write(struct brw_codegen *p,
1082 vec4_instruction *inst,
1083 struct brw_reg dst,
1084 struct brw_reg src,
1085 struct brw_reg index)
1086 {
1087 const struct brw_device_info *devinfo = p->devinfo;
1088 struct brw_reg header = brw_vec8_grf(0, 0);
1089 bool write_commit;
1090
1091 /* If the instruction is predicated, we'll predicate the send, not
1092 * the header setup.
1093 */
1094 brw_set_default_predicate_control(p, false);
1095
1096 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1097
1098 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1099 index);
1100
1101 brw_MOV(p,
1102 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1103 retype(src, BRW_REGISTER_TYPE_D));
1104
1105 uint32_t msg_type;
1106
1107 if (devinfo->gen >= 7)
1108 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1109 else if (devinfo->gen == 6)
1110 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1111 else
1112 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1113
1114 brw_set_default_predicate_control(p, inst->predicate);
1115
1116 /* Pre-gen6, we have to specify write commits to ensure ordering
1117 * between reads and writes within a thread. Afterwards, that's
1118 * guaranteed and write commits only matter for inter-thread
1119 * synchronization.
1120 */
1121 if (devinfo->gen >= 6) {
1122 write_commit = false;
1123 } else {
1124 /* The visitor set up our destination register to be g0. This
1125 * means that when the next read comes along, we will end up
1126 * reading from g0 and causing a block on the write commit. For
1127 * write-after-read, we are relying on the value of the previous
1128 * read being used (and thus blocking on completion) before our
1129 * write is executed. This means we have to be careful in
1130 * instruction scheduling to not violate this assumption.
1131 */
1132 write_commit = true;
1133 }
1134
1135 /* Each of the 8 channel enables is considered for whether each
1136 * dword is written.
1137 */
1138 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1139 brw_set_dest(p, send, dst);
1140 brw_set_src0(p, send, header);
1141 if (devinfo->gen < 6)
1142 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1143 brw_set_dp_write_message(p, send,
1144 brw_scratch_surface_idx(p),
1145 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1146 msg_type,
1147 3, /* mlen */
1148 true, /* header present */
1149 false, /* not a render target write */
1150 write_commit, /* rlen */
1151 false, /* eot */
1152 write_commit);
1153 }
1154
1155 static void
1156 generate_pull_constant_load(struct brw_codegen *p,
1157 struct brw_vue_prog_data *prog_data,
1158 vec4_instruction *inst,
1159 struct brw_reg dst,
1160 struct brw_reg index,
1161 struct brw_reg offset)
1162 {
1163 const struct brw_device_info *devinfo = p->devinfo;
1164 assert(index.file == BRW_IMMEDIATE_VALUE &&
1165 index.type == BRW_REGISTER_TYPE_UD);
1166 uint32_t surf_index = index.ud;
1167
1168 struct brw_reg header = brw_vec8_grf(0, 0);
1169
1170 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1171
1172 if (devinfo->gen >= 6) {
1173 if (offset.file == BRW_IMMEDIATE_VALUE) {
1174 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1175 BRW_REGISTER_TYPE_D),
1176 brw_imm_d(offset.ud >> 4));
1177 } else {
1178 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1179 BRW_REGISTER_TYPE_D),
1180 offset, brw_imm_d(4));
1181 }
1182 } else {
1183 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1184 BRW_REGISTER_TYPE_D),
1185 offset);
1186 }
1187
1188 uint32_t msg_type;
1189
1190 if (devinfo->gen >= 6)
1191 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1192 else if (devinfo->gen == 5 || devinfo->is_g4x)
1193 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1194 else
1195 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1196
1197 /* Each of the 8 channel enables is considered for whether each
1198 * dword is written.
1199 */
1200 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1201 brw_set_dest(p, send, dst);
1202 brw_set_src0(p, send, header);
1203 if (devinfo->gen < 6)
1204 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1205 brw_set_dp_read_message(p, send,
1206 surf_index,
1207 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1208 msg_type,
1209 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1210 2, /* mlen */
1211 true, /* header_present */
1212 1 /* rlen */);
1213 }
1214
1215 static void
1216 generate_get_buffer_size(struct brw_codegen *p,
1217 struct brw_vue_prog_data *prog_data,
1218 vec4_instruction *inst,
1219 struct brw_reg dst,
1220 struct brw_reg src,
1221 struct brw_reg surf_index)
1222 {
1223 assert(p->devinfo->gen >= 7);
1224 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1225 surf_index.file == BRW_IMMEDIATE_VALUE);
1226
1227 brw_SAMPLE(p,
1228 dst,
1229 inst->base_mrf,
1230 src,
1231 surf_index.ud,
1232 0,
1233 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1234 1, /* response length */
1235 inst->mlen,
1236 inst->header_size > 0,
1237 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1238 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1239
1240 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1241 }
1242
1243 static void
1244 generate_pull_constant_load_gen7(struct brw_codegen *p,
1245 struct brw_vue_prog_data *prog_data,
1246 vec4_instruction *inst,
1247 struct brw_reg dst,
1248 struct brw_reg surf_index,
1249 struct brw_reg offset)
1250 {
1251 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1252
1253 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1254
1255 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1256 brw_set_dest(p, insn, dst);
1257 brw_set_src0(p, insn, offset);
1258 brw_set_sampler_message(p, insn,
1259 surf_index.ud,
1260 0, /* LD message ignores sampler unit */
1261 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1262 1, /* rlen */
1263 inst->mlen,
1264 inst->header_size != 0,
1265 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1266 0);
1267
1268 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1269
1270 } else {
1271
1272 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1273
1274 brw_push_insn_state(p);
1275 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1276 brw_set_default_access_mode(p, BRW_ALIGN_1);
1277
1278 /* a0.0 = surf_index & 0xff */
1279 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1280 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1281 brw_set_dest(p, insn_and, addr);
1282 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1283 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1284
1285 brw_pop_insn_state(p);
1286
1287 /* dst = send(offset, a0.0 | <descriptor>) */
1288 brw_inst *insn = brw_send_indirect_message(
1289 p, BRW_SFID_SAMPLER, dst, offset, addr);
1290 brw_set_sampler_message(p, insn,
1291 0 /* surface */,
1292 0 /* sampler */,
1293 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1294 1 /* rlen */,
1295 inst->mlen,
1296 inst->header_size != 0,
1297 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1298 0);
1299 }
1300 }
1301
1302 static void
1303 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1304 vec4_instruction *inst,
1305 struct brw_reg dst)
1306 {
1307 brw_push_insn_state(p);
1308 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1309
1310 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1311 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1312
1313 brw_set_default_access_mode(p, BRW_ALIGN_1);
1314 brw_MOV(p, get_element_ud(dst, 2),
1315 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1316
1317 brw_pop_insn_state(p);
1318 }
1319
1320 static void
1321 generate_code(struct brw_codegen *p,
1322 const struct brw_compiler *compiler,
1323 void *log_data,
1324 const nir_shader *nir,
1325 struct brw_vue_prog_data *prog_data,
1326 const struct cfg_t *cfg)
1327 {
1328 const struct brw_device_info *devinfo = p->devinfo;
1329 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
1330 bool debug_flag = INTEL_DEBUG &
1331 intel_debug_flag_for_shader_stage(nir->stage);
1332 struct annotation_info annotation;
1333 memset(&annotation, 0, sizeof(annotation));
1334 int loop_count = 0;
1335
1336 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1337 struct brw_reg src[3], dst;
1338
1339 if (unlikely(debug_flag))
1340 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1341
1342 for (unsigned int i = 0; i < 3; i++) {
1343 src[i] = inst->src[i].as_brw_reg();
1344 }
1345 dst = inst->dst.as_brw_reg();
1346
1347 brw_set_default_predicate_control(p, inst->predicate);
1348 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1349 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1350 brw_set_default_saturate(p, inst->saturate);
1351 brw_set_default_mask_control(p, inst->force_writemask_all);
1352 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1353
1354 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1355 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1356
1357 unsigned pre_emit_nr_insn = p->nr_insn;
1358
1359 if (dst.width == BRW_WIDTH_4) {
1360 /* This happens in attribute fixups for "dual instanced" geometry
1361 * shaders, since they use attributes that are vec4's. Since the exec
1362 * width is only 4, it's essential that the caller set
1363 * force_writemask_all in order to make sure the instruction is executed
1364 * regardless of which channels are enabled.
1365 */
1366 assert(inst->force_writemask_all);
1367
1368 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1369 * the following register region restrictions (from Graphics BSpec:
1370 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1371 * > Register Region Restrictions)
1372 *
1373 * 1. ExecSize must be greater than or equal to Width.
1374 *
1375 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1376 * to Width * HorzStride."
1377 */
1378 for (int i = 0; i < 3; i++) {
1379 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1380 src[i] = stride(src[i], 4, 4, 1);
1381 }
1382 }
1383
1384 switch (inst->opcode) {
1385 case VEC4_OPCODE_UNPACK_UNIFORM:
1386 case BRW_OPCODE_MOV:
1387 brw_MOV(p, dst, src[0]);
1388 break;
1389 case BRW_OPCODE_ADD:
1390 brw_ADD(p, dst, src[0], src[1]);
1391 break;
1392 case BRW_OPCODE_MUL:
1393 brw_MUL(p, dst, src[0], src[1]);
1394 break;
1395 case BRW_OPCODE_MACH:
1396 brw_MACH(p, dst, src[0], src[1]);
1397 break;
1398
1399 case BRW_OPCODE_MAD:
1400 assert(devinfo->gen >= 6);
1401 brw_MAD(p, dst, src[0], src[1], src[2]);
1402 break;
1403
1404 case BRW_OPCODE_FRC:
1405 brw_FRC(p, dst, src[0]);
1406 break;
1407 case BRW_OPCODE_RNDD:
1408 brw_RNDD(p, dst, src[0]);
1409 break;
1410 case BRW_OPCODE_RNDE:
1411 brw_RNDE(p, dst, src[0]);
1412 break;
1413 case BRW_OPCODE_RNDZ:
1414 brw_RNDZ(p, dst, src[0]);
1415 break;
1416
1417 case BRW_OPCODE_AND:
1418 brw_AND(p, dst, src[0], src[1]);
1419 break;
1420 case BRW_OPCODE_OR:
1421 brw_OR(p, dst, src[0], src[1]);
1422 break;
1423 case BRW_OPCODE_XOR:
1424 brw_XOR(p, dst, src[0], src[1]);
1425 break;
1426 case BRW_OPCODE_NOT:
1427 brw_NOT(p, dst, src[0]);
1428 break;
1429 case BRW_OPCODE_ASR:
1430 brw_ASR(p, dst, src[0], src[1]);
1431 break;
1432 case BRW_OPCODE_SHR:
1433 brw_SHR(p, dst, src[0], src[1]);
1434 break;
1435 case BRW_OPCODE_SHL:
1436 brw_SHL(p, dst, src[0], src[1]);
1437 break;
1438
1439 case BRW_OPCODE_CMP:
1440 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1441 break;
1442 case BRW_OPCODE_SEL:
1443 brw_SEL(p, dst, src[0], src[1]);
1444 break;
1445
1446 case BRW_OPCODE_DPH:
1447 brw_DPH(p, dst, src[0], src[1]);
1448 break;
1449
1450 case BRW_OPCODE_DP4:
1451 brw_DP4(p, dst, src[0], src[1]);
1452 break;
1453
1454 case BRW_OPCODE_DP3:
1455 brw_DP3(p, dst, src[0], src[1]);
1456 break;
1457
1458 case BRW_OPCODE_DP2:
1459 brw_DP2(p, dst, src[0], src[1]);
1460 break;
1461
1462 case BRW_OPCODE_F32TO16:
1463 assert(devinfo->gen >= 7);
1464 brw_F32TO16(p, dst, src[0]);
1465 break;
1466
1467 case BRW_OPCODE_F16TO32:
1468 assert(devinfo->gen >= 7);
1469 brw_F16TO32(p, dst, src[0]);
1470 break;
1471
1472 case BRW_OPCODE_LRP:
1473 assert(devinfo->gen >= 6);
1474 brw_LRP(p, dst, src[0], src[1], src[2]);
1475 break;
1476
1477 case BRW_OPCODE_BFREV:
1478 assert(devinfo->gen >= 7);
1479 /* BFREV only supports UD type for src and dst. */
1480 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1481 retype(src[0], BRW_REGISTER_TYPE_UD));
1482 break;
1483 case BRW_OPCODE_FBH:
1484 assert(devinfo->gen >= 7);
1485 /* FBH only supports UD type for dst. */
1486 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1487 break;
1488 case BRW_OPCODE_FBL:
1489 assert(devinfo->gen >= 7);
1490 /* FBL only supports UD type for dst. */
1491 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1492 break;
1493 case BRW_OPCODE_CBIT:
1494 assert(devinfo->gen >= 7);
1495 /* CBIT only supports UD type for dst. */
1496 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1497 break;
1498 case BRW_OPCODE_ADDC:
1499 assert(devinfo->gen >= 7);
1500 brw_ADDC(p, dst, src[0], src[1]);
1501 break;
1502 case BRW_OPCODE_SUBB:
1503 assert(devinfo->gen >= 7);
1504 brw_SUBB(p, dst, src[0], src[1]);
1505 break;
1506 case BRW_OPCODE_MAC:
1507 brw_MAC(p, dst, src[0], src[1]);
1508 break;
1509
1510 case BRW_OPCODE_BFE:
1511 assert(devinfo->gen >= 7);
1512 brw_BFE(p, dst, src[0], src[1], src[2]);
1513 break;
1514
1515 case BRW_OPCODE_BFI1:
1516 assert(devinfo->gen >= 7);
1517 brw_BFI1(p, dst, src[0], src[1]);
1518 break;
1519 case BRW_OPCODE_BFI2:
1520 assert(devinfo->gen >= 7);
1521 brw_BFI2(p, dst, src[0], src[1], src[2]);
1522 break;
1523
1524 case BRW_OPCODE_IF:
1525 if (!inst->src[0].is_null()) {
1526 /* The instruction has an embedded compare (only allowed on gen6) */
1527 assert(devinfo->gen == 6);
1528 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1529 } else {
1530 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1531 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1532 }
1533 break;
1534
1535 case BRW_OPCODE_ELSE:
1536 brw_ELSE(p);
1537 break;
1538 case BRW_OPCODE_ENDIF:
1539 brw_ENDIF(p);
1540 break;
1541
1542 case BRW_OPCODE_DO:
1543 brw_DO(p, BRW_EXECUTE_8);
1544 break;
1545
1546 case BRW_OPCODE_BREAK:
1547 brw_BREAK(p);
1548 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1549 break;
1550 case BRW_OPCODE_CONTINUE:
1551 brw_CONT(p);
1552 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1553 break;
1554
1555 case BRW_OPCODE_WHILE:
1556 brw_WHILE(p);
1557 loop_count++;
1558 break;
1559
1560 case SHADER_OPCODE_RCP:
1561 case SHADER_OPCODE_RSQ:
1562 case SHADER_OPCODE_SQRT:
1563 case SHADER_OPCODE_EXP2:
1564 case SHADER_OPCODE_LOG2:
1565 case SHADER_OPCODE_SIN:
1566 case SHADER_OPCODE_COS:
1567 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1568 if (devinfo->gen >= 7) {
1569 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1570 brw_null_reg());
1571 } else if (devinfo->gen == 6) {
1572 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1573 } else {
1574 generate_math1_gen4(p, inst, dst, src[0]);
1575 }
1576 break;
1577
1578 case SHADER_OPCODE_POW:
1579 case SHADER_OPCODE_INT_QUOTIENT:
1580 case SHADER_OPCODE_INT_REMAINDER:
1581 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1582 if (devinfo->gen >= 7) {
1583 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1584 } else if (devinfo->gen == 6) {
1585 generate_math_gen6(p, inst, dst, src[0], src[1]);
1586 } else {
1587 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1588 }
1589 break;
1590
1591 case SHADER_OPCODE_TEX:
1592 case SHADER_OPCODE_TXD:
1593 case SHADER_OPCODE_TXF:
1594 case SHADER_OPCODE_TXF_CMS:
1595 case SHADER_OPCODE_TXF_CMS_W:
1596 case SHADER_OPCODE_TXF_MCS:
1597 case SHADER_OPCODE_TXL:
1598 case SHADER_OPCODE_TXS:
1599 case SHADER_OPCODE_TG4:
1600 case SHADER_OPCODE_TG4_OFFSET:
1601 case SHADER_OPCODE_SAMPLEINFO:
1602 generate_tex(p, prog_data, inst, dst, src[0], src[1]);
1603 break;
1604
1605 case VS_OPCODE_URB_WRITE:
1606 generate_vs_urb_write(p, inst);
1607 break;
1608
1609 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1610 generate_scratch_read(p, inst, dst, src[0]);
1611 break;
1612
1613 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1614 generate_scratch_write(p, inst, dst, src[0], src[1]);
1615 break;
1616
1617 case VS_OPCODE_PULL_CONSTANT_LOAD:
1618 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1619 break;
1620
1621 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1622 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1623 break;
1624
1625 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1626 generate_set_simd4x2_header_gen9(p, inst, dst);
1627 break;
1628
1629
1630 case VS_OPCODE_GET_BUFFER_SIZE:
1631 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1632 break;
1633
1634 case GS_OPCODE_URB_WRITE:
1635 generate_gs_urb_write(p, inst);
1636 break;
1637
1638 case GS_OPCODE_URB_WRITE_ALLOCATE:
1639 generate_gs_urb_write_allocate(p, inst);
1640 break;
1641
1642 case GS_OPCODE_SVB_WRITE:
1643 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1644 break;
1645
1646 case GS_OPCODE_SVB_SET_DST_INDEX:
1647 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1648 break;
1649
1650 case GS_OPCODE_THREAD_END:
1651 generate_gs_thread_end(p, inst);
1652 break;
1653
1654 case GS_OPCODE_SET_WRITE_OFFSET:
1655 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1656 break;
1657
1658 case GS_OPCODE_SET_VERTEX_COUNT:
1659 generate_gs_set_vertex_count(p, dst, src[0]);
1660 break;
1661
1662 case GS_OPCODE_FF_SYNC:
1663 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1664 break;
1665
1666 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1667 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1668 break;
1669
1670 case GS_OPCODE_SET_PRIMITIVE_ID:
1671 generate_gs_set_primitive_id(p, dst);
1672 break;
1673
1674 case GS_OPCODE_SET_DWORD_2:
1675 generate_gs_set_dword_2(p, dst, src[0]);
1676 break;
1677
1678 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1679 generate_gs_prepare_channel_masks(p, dst);
1680 break;
1681
1682 case GS_OPCODE_SET_CHANNEL_MASKS:
1683 generate_gs_set_channel_masks(p, dst, src[0]);
1684 break;
1685
1686 case GS_OPCODE_GET_INSTANCE_ID:
1687 generate_gs_get_instance_id(p, dst);
1688 break;
1689
1690 case SHADER_OPCODE_SHADER_TIME_ADD:
1691 brw_shader_time_add(p, src[0],
1692 prog_data->base.binding_table.shader_time_start);
1693 brw_mark_surface_used(&prog_data->base,
1694 prog_data->base.binding_table.shader_time_start);
1695 break;
1696
1697 case SHADER_OPCODE_UNTYPED_ATOMIC:
1698 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1699 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1700 !inst->dst.is_null());
1701 break;
1702
1703 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1704 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1705 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1706 src[2].ud);
1707 break;
1708
1709 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1710 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1711 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1712 src[2].ud);
1713 break;
1714
1715 case SHADER_OPCODE_TYPED_ATOMIC:
1716 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1717 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1718 !inst->dst.is_null());
1719 break;
1720
1721 case SHADER_OPCODE_TYPED_SURFACE_READ:
1722 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1723 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1724 src[2].ud);
1725 break;
1726
1727 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1728 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1729 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1730 src[2].ud);
1731 break;
1732
1733 case SHADER_OPCODE_MEMORY_FENCE:
1734 brw_memory_fence(p, dst);
1735 break;
1736
1737 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1738 brw_find_live_channel(p, dst);
1739 break;
1740
1741 case SHADER_OPCODE_BROADCAST:
1742 brw_broadcast(p, dst, src[0], src[1]);
1743 break;
1744
1745 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1746 generate_unpack_flags(p, dst);
1747 break;
1748
1749 case VEC4_OPCODE_MOV_BYTES: {
1750 /* Moves the low byte from each channel, using an Align1 access mode
1751 * and a <4,1,0> source region.
1752 */
1753 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1754 src[0].type == BRW_REGISTER_TYPE_B);
1755
1756 brw_set_default_access_mode(p, BRW_ALIGN_1);
1757 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1758 src[0].width = BRW_WIDTH_1;
1759 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1760 brw_MOV(p, dst, src[0]);
1761 brw_set_default_access_mode(p, BRW_ALIGN_16);
1762 break;
1763 }
1764
1765 case VEC4_OPCODE_PACK_BYTES: {
1766 /* Is effectively:
1767 *
1768 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1769 *
1770 * but destinations' only regioning is horizontal stride, so instead we
1771 * have to use two instructions:
1772 *
1773 * mov(4) dst<1>:UB src<4,1,0>:UB
1774 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1775 *
1776 * where they pack the four bytes from the low and high four DW.
1777 */
1778 assert(_mesa_is_pow_two(dst.writemask) &&
1779 dst.writemask != 0);
1780 unsigned offset = __builtin_ctz(dst.writemask);
1781
1782 dst.type = BRW_REGISTER_TYPE_UB;
1783
1784 brw_set_default_access_mode(p, BRW_ALIGN_1);
1785
1786 src[0].type = BRW_REGISTER_TYPE_UB;
1787 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1788 src[0].width = BRW_WIDTH_1;
1789 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1790 dst.subnr = offset * 4;
1791 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1792 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1793 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1794 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1795
1796 src[0].subnr = 16;
1797 dst.subnr = 16 + offset * 4;
1798 insn = brw_MOV(p, dst, src[0]);
1799 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1800 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1801 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1802
1803 brw_set_default_access_mode(p, BRW_ALIGN_16);
1804 break;
1805 }
1806
1807 case TCS_OPCODE_URB_WRITE:
1808 generate_tcs_urb_write(p, inst, src[0]);
1809 break;
1810
1811 case VEC4_OPCODE_URB_READ:
1812 generate_vec4_urb_read(p, inst, dst, src[0]);
1813 break;
1814
1815 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
1816 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
1817 break;
1818
1819 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
1820 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
1821 break;
1822
1823 case TCS_OPCODE_GET_INSTANCE_ID:
1824 generate_tcs_get_instance_id(p, dst);
1825 break;
1826
1827 case TCS_OPCODE_GET_PRIMITIVE_ID:
1828 generate_tcs_get_primitive_id(p, dst);
1829 break;
1830
1831 case TCS_OPCODE_CREATE_BARRIER_HEADER:
1832 generate_tcs_create_barrier_header(p, prog_data, dst);
1833 break;
1834
1835 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
1836 generate_tes_create_input_read_header(p, dst);
1837 break;
1838
1839 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
1840 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
1841 break;
1842
1843 case TES_OPCODE_GET_PRIMITIVE_ID:
1844 generate_tes_get_primitive_id(p, dst);
1845 break;
1846
1847 case SHADER_OPCODE_BARRIER:
1848 brw_barrier(p, src[0]);
1849 brw_WAIT(p);
1850 break;
1851
1852 default:
1853 unreachable("Unsupported opcode");
1854 }
1855
1856 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1857 /* Handled dependency hints in the generator. */
1858
1859 assert(!inst->conditional_mod);
1860 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1861 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1862 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1863 "emitting more than 1 instruction");
1864
1865 brw_inst *last = &p->store[pre_emit_nr_insn];
1866
1867 if (inst->conditional_mod)
1868 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1869 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1870 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1871 }
1872 }
1873
1874 brw_set_uip_jip(p);
1875 annotation_finalize(&annotation, p->next_insn_offset);
1876
1877 #ifndef NDEBUG
1878 bool validated = brw_validate_instructions(p, 0, &annotation);
1879 #else
1880 if (unlikely(debug_flag))
1881 brw_validate_instructions(p, 0, &annotation);
1882 #endif
1883
1884 int before_size = p->next_insn_offset;
1885 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1886 int after_size = p->next_insn_offset;
1887
1888 if (unlikely(debug_flag)) {
1889 fprintf(stderr, "Native code for %s %s shader %s:\n",
1890 nir->info.label ? nir->info.label : "unnamed",
1891 _mesa_shader_stage_to_string(nir->stage), nir->info.name);
1892
1893 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles."
1894 "Compacted %d to %d bytes (%.0f%%)\n",
1895 stage_abbrev,
1896 before_size / 16, loop_count, cfg->cycle_count, before_size, after_size,
1897 100.0f * (before_size - after_size) / before_size);
1898
1899 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1900 p->devinfo);
1901 ralloc_free(annotation.mem_ctx);
1902 }
1903 assert(validated);
1904
1905 compiler->shader_debug_log(log_data,
1906 "%s vec4 shader: %d inst, %d loops, %u cycles, "
1907 "compacted %d to %d bytes.\n",
1908 stage_abbrev, before_size / 16,
1909 loop_count, cfg->cycle_count,
1910 before_size, after_size);
1911 }
1912
1913 extern "C" const unsigned *
1914 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
1915 void *log_data,
1916 void *mem_ctx,
1917 const nir_shader *nir,
1918 struct brw_vue_prog_data *prog_data,
1919 const struct cfg_t *cfg,
1920 unsigned *out_assembly_size)
1921 {
1922 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
1923 brw_init_codegen(compiler->devinfo, p, mem_ctx);
1924 brw_set_default_access_mode(p, BRW_ALIGN_16);
1925
1926 generate_code(p, compiler, log_data, nir, prog_data, cfg);
1927
1928 return brw_get_program(p, out_assembly_size);
1929 }