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i965: Resolve GCC sign-compare warning.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include <ctype.h>
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26
27 extern "C" {
28 #include "brw_eu.h"
29 #include "main/macros.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
32 };
33
34 namespace brw {
35
36 struct brw_reg
37 vec4_instruction::get_dst(void)
38 {
39 struct brw_reg brw_reg;
40
41 switch (dst.file) {
42 case GRF:
43 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
44 brw_reg = retype(brw_reg, dst.type);
45 brw_reg.dw1.bits.writemask = dst.writemask;
46 break;
47
48 case MRF:
49 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
50 brw_reg = retype(brw_reg, dst.type);
51 brw_reg.dw1.bits.writemask = dst.writemask;
52 break;
53
54 case HW_REG:
55 assert(dst.type == dst.fixed_hw_reg.type);
56 brw_reg = dst.fixed_hw_reg;
57 break;
58
59 case BAD_FILE:
60 brw_reg = brw_null_reg();
61 break;
62
63 default:
64 unreachable("not reached");
65 }
66 return brw_reg;
67 }
68
69 struct brw_reg
70 vec4_instruction::get_src(const struct brw_vue_prog_data *prog_data, int i)
71 {
72 struct brw_reg brw_reg;
73
74 switch (src[i].file) {
75 case GRF:
76 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
77 brw_reg = retype(brw_reg, src[i].type);
78 brw_reg.dw1.bits.swizzle = src[i].swizzle;
79 if (src[i].abs)
80 brw_reg = brw_abs(brw_reg);
81 if (src[i].negate)
82 brw_reg = negate(brw_reg);
83 break;
84
85 case IMM:
86 switch (src[i].type) {
87 case BRW_REGISTER_TYPE_F:
88 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
89 break;
90 case BRW_REGISTER_TYPE_D:
91 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
92 break;
93 case BRW_REGISTER_TYPE_UD:
94 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
95 break;
96 case BRW_REGISTER_TYPE_VF:
97 brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
98 break;
99 default:
100 unreachable("not reached");
101 }
102 break;
103
104 case UNIFORM:
105 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
106 (src[i].reg + src[i].reg_offset) / 2,
107 ((src[i].reg + src[i].reg_offset) % 2) * 4),
108 0, 4, 1);
109 brw_reg = retype(brw_reg, src[i].type);
110 brw_reg.dw1.bits.swizzle = src[i].swizzle;
111 if (src[i].abs)
112 brw_reg = brw_abs(brw_reg);
113 if (src[i].negate)
114 brw_reg = negate(brw_reg);
115
116 /* This should have been moved to pull constants. */
117 assert(!src[i].reladdr);
118 break;
119
120 case HW_REG:
121 assert(src[i].type == src[i].fixed_hw_reg.type);
122 brw_reg = src[i].fixed_hw_reg;
123 break;
124
125 case BAD_FILE:
126 /* Probably unused. */
127 brw_reg = brw_null_reg();
128 break;
129 case ATTR:
130 default:
131 unreachable("not reached");
132 }
133
134 return brw_reg;
135 }
136
137 vec4_generator::vec4_generator(const struct brw_compiler *compiler,
138 void *log_data,
139 struct gl_shader_program *shader_prog,
140 struct gl_program *prog,
141 struct brw_vue_prog_data *prog_data,
142 void *mem_ctx,
143 bool debug_flag,
144 const char *stage_name,
145 const char *stage_abbrev)
146 : compiler(compiler), log_data(log_data), devinfo(compiler->devinfo),
147 shader_prog(shader_prog), prog(prog), prog_data(prog_data),
148 mem_ctx(mem_ctx), stage_name(stage_name), stage_abbrev(stage_abbrev),
149 debug_flag(debug_flag)
150 {
151 p = rzalloc(mem_ctx, struct brw_codegen);
152 brw_init_codegen(devinfo, p, mem_ctx);
153 }
154
155 vec4_generator::~vec4_generator()
156 {
157 }
158
159 void
160 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
161 struct brw_reg dst,
162 struct brw_reg src)
163 {
164 gen4_math(p,
165 dst,
166 brw_math_function(inst->opcode),
167 inst->base_mrf,
168 src,
169 BRW_MATH_PRECISION_FULL);
170 }
171
172 static void
173 check_gen6_math_src_arg(struct brw_reg src)
174 {
175 /* Source swizzles are ignored. */
176 assert(!src.abs);
177 assert(!src.negate);
178 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
179 }
180
181 void
182 vec4_generator::generate_math_gen6(vec4_instruction *inst,
183 struct brw_reg dst,
184 struct brw_reg src0,
185 struct brw_reg src1)
186 {
187 /* Can't do writemask because math can't be align16. */
188 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
189 /* Source swizzles are ignored. */
190 check_gen6_math_src_arg(src0);
191 if (src1.file == BRW_GENERAL_REGISTER_FILE)
192 check_gen6_math_src_arg(src1);
193
194 brw_set_default_access_mode(p, BRW_ALIGN_1);
195 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
196 brw_set_default_access_mode(p, BRW_ALIGN_16);
197 }
198
199 void
200 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
201 struct brw_reg dst,
202 struct brw_reg src0,
203 struct brw_reg src1)
204 {
205 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
206 * "Message Payload":
207 *
208 * "Operand0[7]. For the INT DIV functions, this operand is the
209 * denominator."
210 * ...
211 * "Operand1[7]. For the INT DIV functions, this operand is the
212 * numerator."
213 */
214 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
215 struct brw_reg &op0 = is_int_div ? src1 : src0;
216 struct brw_reg &op1 = is_int_div ? src0 : src1;
217
218 brw_push_insn_state(p);
219 brw_set_default_saturate(p, false);
220 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
221 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
222 brw_pop_insn_state(p);
223
224 gen4_math(p,
225 dst,
226 brw_math_function(inst->opcode),
227 inst->base_mrf,
228 op0,
229 BRW_MATH_PRECISION_FULL);
230 }
231
232 void
233 vec4_generator::generate_tex(vec4_instruction *inst,
234 struct brw_reg dst,
235 struct brw_reg src,
236 struct brw_reg sampler_index)
237 {
238 int msg_type = -1;
239
240 if (devinfo->gen >= 5) {
241 switch (inst->opcode) {
242 case SHADER_OPCODE_TEX:
243 case SHADER_OPCODE_TXL:
244 if (inst->shadow_compare) {
245 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
246 } else {
247 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
248 }
249 break;
250 case SHADER_OPCODE_TXD:
251 if (inst->shadow_compare) {
252 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
253 assert(devinfo->gen >= 8 || devinfo->is_haswell);
254 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
255 } else {
256 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
257 }
258 break;
259 case SHADER_OPCODE_TXF:
260 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
261 break;
262 case SHADER_OPCODE_TXF_CMS:
263 if (devinfo->gen >= 7)
264 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
265 else
266 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
267 break;
268 case SHADER_OPCODE_TXF_MCS:
269 assert(devinfo->gen >= 7);
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
271 break;
272 case SHADER_OPCODE_TXS:
273 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
274 break;
275 case SHADER_OPCODE_TG4:
276 if (inst->shadow_compare) {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
278 } else {
279 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
280 }
281 break;
282 case SHADER_OPCODE_TG4_OFFSET:
283 if (inst->shadow_compare) {
284 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
285 } else {
286 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
287 }
288 break;
289 default:
290 unreachable("should not get here: invalid vec4 texture opcode");
291 }
292 } else {
293 switch (inst->opcode) {
294 case SHADER_OPCODE_TEX:
295 case SHADER_OPCODE_TXL:
296 if (inst->shadow_compare) {
297 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
298 assert(inst->mlen == 3);
299 } else {
300 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
301 assert(inst->mlen == 2);
302 }
303 break;
304 case SHADER_OPCODE_TXD:
305 /* There is no sample_d_c message; comparisons are done manually. */
306 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
307 assert(inst->mlen == 4);
308 break;
309 case SHADER_OPCODE_TXF:
310 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
311 assert(inst->mlen == 2);
312 break;
313 case SHADER_OPCODE_TXS:
314 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
315 assert(inst->mlen == 2);
316 break;
317 default:
318 unreachable("should not get here: invalid vec4 texture opcode");
319 }
320 }
321
322 assert(msg_type != -1);
323
324 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
325
326 /* Load the message header if present. If there's a texture offset, we need
327 * to set it up explicitly and load the offset bitfield. Otherwise, we can
328 * use an implied move from g0 to the first message register.
329 */
330 if (inst->header_size != 0) {
331 if (devinfo->gen < 6 && !inst->offset) {
332 /* Set up an implied move from g0 to the MRF. */
333 src = brw_vec8_grf(0, 0);
334 } else {
335 struct brw_reg header =
336 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
337 uint32_t dw2 = 0;
338
339 /* Explicitly set up the message header by copying g0 to the MRF. */
340 brw_push_insn_state(p);
341 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
342 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
343
344 brw_set_default_access_mode(p, BRW_ALIGN_1);
345
346 if (inst->offset)
347 /* Set the texel offset bits in DWord 2. */
348 dw2 = inst->offset;
349
350 if (devinfo->gen >= 9)
351 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
352 * based on bit 22 in the header.
353 */
354 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
355
356 if (dw2)
357 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
358
359 brw_adjust_sampler_state_pointer(p, header, sampler_index);
360 brw_pop_insn_state(p);
361 }
362 }
363
364 uint32_t return_format;
365
366 switch (dst.type) {
367 case BRW_REGISTER_TYPE_D:
368 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
369 break;
370 case BRW_REGISTER_TYPE_UD:
371 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
372 break;
373 default:
374 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
375 break;
376 }
377
378 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
379 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
380 ? prog_data->base.binding_table.gather_texture_start
381 : prog_data->base.binding_table.texture_start;
382
383 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
384 uint32_t sampler = sampler_index.dw1.ud;
385
386 brw_SAMPLE(p,
387 dst,
388 inst->base_mrf,
389 src,
390 sampler + base_binding_table_index,
391 sampler % 16,
392 msg_type,
393 1, /* response length */
394 inst->mlen,
395 inst->header_size != 0,
396 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
397 return_format);
398
399 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
400 } else {
401 /* Non-constant sampler index. */
402
403 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
404 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
405
406 brw_push_insn_state(p);
407 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
408 brw_set_default_access_mode(p, BRW_ALIGN_1);
409
410 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
411 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
412 if (base_binding_table_index)
413 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
414 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
415
416 brw_pop_insn_state(p);
417
418 if (inst->base_mrf != -1)
419 gen6_resolve_implied_move(p, &src, inst->base_mrf);
420
421 /* dst = send(offset, a0.0 | <descriptor>) */
422 brw_inst *insn = brw_send_indirect_message(
423 p, BRW_SFID_SAMPLER, dst, src, addr);
424 brw_set_sampler_message(p, insn,
425 0 /* surface */,
426 0 /* sampler */,
427 msg_type,
428 1 /* rlen */,
429 inst->mlen /* mlen */,
430 inst->header_size != 0 /* header */,
431 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
432 return_format);
433
434 /* visitor knows more than we do about the surface limit required,
435 * so has already done marking.
436 */
437 }
438 }
439
440 void
441 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
442 {
443 brw_urb_WRITE(p,
444 brw_null_reg(), /* dest */
445 inst->base_mrf, /* starting mrf reg nr */
446 brw_vec8_grf(0, 0), /* src */
447 inst->urb_write_flags,
448 inst->mlen,
449 0, /* response len */
450 inst->offset, /* urb destination offset */
451 BRW_URB_SWIZZLE_INTERLEAVE);
452 }
453
454 void
455 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
456 {
457 struct brw_reg src = brw_message_reg(inst->base_mrf);
458 brw_urb_WRITE(p,
459 brw_null_reg(), /* dest */
460 inst->base_mrf, /* starting mrf reg nr */
461 src,
462 inst->urb_write_flags,
463 inst->mlen,
464 0, /* response len */
465 inst->offset, /* urb destination offset */
466 BRW_URB_SWIZZLE_INTERLEAVE);
467 }
468
469 void
470 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
471 {
472 struct brw_reg src = brw_message_reg(inst->base_mrf);
473
474 /* We pass the temporary passed in src0 as the writeback register */
475 brw_urb_WRITE(p,
476 inst->get_src(this->prog_data, 0), /* dest */
477 inst->base_mrf, /* starting mrf reg nr */
478 src,
479 BRW_URB_WRITE_ALLOCATE_COMPLETE,
480 inst->mlen,
481 1, /* response len */
482 inst->offset, /* urb destination offset */
483 BRW_URB_SWIZZLE_INTERLEAVE);
484
485 /* Now put allocated urb handle in dst.0 */
486 brw_push_insn_state(p);
487 brw_set_default_access_mode(p, BRW_ALIGN_1);
488 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
489 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
490 get_element_ud(inst->get_src(this->prog_data, 0), 0));
491 brw_set_default_access_mode(p, BRW_ALIGN_16);
492 brw_pop_insn_state(p);
493 }
494
495 void
496 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
497 {
498 struct brw_reg src = brw_message_reg(inst->base_mrf);
499 brw_urb_WRITE(p,
500 brw_null_reg(), /* dest */
501 inst->base_mrf, /* starting mrf reg nr */
502 src,
503 BRW_URB_WRITE_EOT | inst->urb_write_flags,
504 devinfo->gen >= 8 ? 2 : 1,/* message len */
505 0, /* response len */
506 0, /* urb destination offset */
507 BRW_URB_SWIZZLE_INTERLEAVE);
508 }
509
510 void
511 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
512 struct brw_reg src0,
513 struct brw_reg src1)
514 {
515 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
516 * Header: M0.3):
517 *
518 * Slot 0 Offset. This field, after adding to the Global Offset field
519 * in the message descriptor, specifies the offset (in 256-bit units)
520 * from the start of the URB entry, as referenced by URB Handle 0, at
521 * which the data will be accessed.
522 *
523 * Similar text describes DWORD M0.4, which is slot 1 offset.
524 *
525 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
526 * of the register for geometry shader invocations 0 and 1) by the
527 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
528 *
529 * We can do this with the following EU instruction:
530 *
531 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
532 */
533 brw_push_insn_state(p);
534 brw_set_default_access_mode(p, BRW_ALIGN_1);
535 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
536 assert(devinfo->gen >= 7 &&
537 src1.file == BRW_IMMEDIATE_VALUE &&
538 src1.type == BRW_REGISTER_TYPE_UD &&
539 src1.dw1.ud <= USHRT_MAX);
540 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
541 retype(src1, BRW_REGISTER_TYPE_UW));
542 brw_set_default_access_mode(p, BRW_ALIGN_16);
543 brw_pop_insn_state(p);
544 }
545
546 void
547 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
548 struct brw_reg src)
549 {
550 brw_push_insn_state(p);
551 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
552
553 if (devinfo->gen >= 8) {
554 /* Move the vertex count into the second MRF for the EOT write. */
555 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
556 src);
557 } else {
558 /* If we think of the src and dst registers as composed of 8 DWORDs each,
559 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
560 * them to WORDs, and then pack them into DWORD 2 of dst.
561 *
562 * It's easier to get the EU to do this if we think of the src and dst
563 * registers as composed of 16 WORDS each; then, we want to pick up the
564 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
565 * of dst.
566 *
567 * We can do that by the following EU instruction:
568 *
569 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
570 */
571 brw_set_default_access_mode(p, BRW_ALIGN_1);
572 brw_MOV(p,
573 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
574 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
575 brw_set_default_access_mode(p, BRW_ALIGN_16);
576 }
577 brw_pop_insn_state(p);
578 }
579
580 void
581 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
582 struct brw_reg dst,
583 struct brw_reg src0,
584 struct brw_reg src1)
585 {
586 int binding = inst->sol_binding;
587 bool final_write = inst->sol_final_write;
588
589 brw_push_insn_state(p);
590 /* Copy Vertex data into M0.x */
591 brw_MOV(p, stride(dst, 4, 4, 1),
592 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
593
594 /* Send SVB Write */
595 brw_svb_write(p,
596 final_write ? src1 : brw_null_reg(), /* dest == src1 */
597 1, /* msg_reg_nr */
598 dst, /* src0 == previous dst */
599 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
600 final_write); /* send_commit_msg */
601
602 /* Finally, wait for the write commit to occur so that we can proceed to
603 * other things safely.
604 *
605 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
606 *
607 * The write commit does not modify the destination register, but
608 * merely clears the dependency associated with the destination
609 * register. Thus, a simple “mov” instruction using the register as a
610 * source is sufficient to wait for the write commit to occur.
611 */
612 if (final_write) {
613 brw_MOV(p, src1, src1);
614 }
615 brw_pop_insn_state(p);
616 }
617
618 void
619 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
620 struct brw_reg dst,
621 struct brw_reg src)
622 {
623
624 int vertex = inst->sol_vertex;
625 brw_push_insn_state(p);
626 brw_set_default_access_mode(p, BRW_ALIGN_1);
627 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
628 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
629 brw_pop_insn_state(p);
630 }
631
632 void
633 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
634 {
635 brw_push_insn_state(p);
636 brw_set_default_access_mode(p, BRW_ALIGN_1);
637 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
638 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
639 brw_pop_insn_state(p);
640 }
641
642 void
643 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
644 {
645 /* We want to left shift just DWORD 4 (the x component belonging to the
646 * second geometry shader invocation) by 4 bits. So generate the
647 * instruction:
648 *
649 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
650 */
651 dst = suboffset(vec1(dst), 4);
652 brw_push_insn_state(p);
653 brw_set_default_access_mode(p, BRW_ALIGN_1);
654 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
655 brw_SHL(p, dst, dst, brw_imm_ud(4));
656 brw_pop_insn_state(p);
657 }
658
659 void
660 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
661 struct brw_reg src)
662 {
663 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
664 * Header: M0.5):
665 *
666 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
667 *
668 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
669 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
670 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
671 * channel enable to determine the final channel enable. For the
672 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
673 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
674 * in the writeback message. For the URB_WRITE_OWORD &
675 * URB_WRITE_HWORD messages, when final channel enable is 1 it
676 * indicates that Vertex 1 DATA [3] will be written to the surface.
677 *
678 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
679 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
680 *
681 * 14 Vertex 1 DATA [2] Channel Mask
682 * 13 Vertex 1 DATA [1] Channel Mask
683 * 12 Vertex 1 DATA [0] Channel Mask
684 * 11 Vertex 0 DATA [3] Channel Mask
685 * 10 Vertex 0 DATA [2] Channel Mask
686 * 9 Vertex 0 DATA [1] Channel Mask
687 * 8 Vertex 0 DATA [0] Channel Mask
688 *
689 * (This is from a section of the PRM that is agnostic to the particular
690 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
691 * geometry shader invocations 0 and 1, respectively). Since we have the
692 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
693 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
694 * DWORD 4, we just need to OR them together and store the result in bits
695 * 15:8 of DWORD 5.
696 *
697 * It's easier to get the EU to do this if we think of the src and dst
698 * registers as composed of 32 bytes each; then, we want to pick up the
699 * contents of bytes 0 and 16 from src, OR them together, and store them in
700 * byte 21.
701 *
702 * We can do that by the following EU instruction:
703 *
704 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
705 *
706 * Note: this relies on the source register having zeros in (a) bits 7:4 of
707 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
708 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
709 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
710 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
711 * contain valid channel mask values (which are in the range 0x0-0xf).
712 */
713 dst = retype(dst, BRW_REGISTER_TYPE_UB);
714 src = retype(src, BRW_REGISTER_TYPE_UB);
715 brw_push_insn_state(p);
716 brw_set_default_access_mode(p, BRW_ALIGN_1);
717 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
718 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
719 brw_pop_insn_state(p);
720 }
721
722 void
723 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
724 {
725 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
726 * and store into dst.0 & dst.4. So generate the instruction:
727 *
728 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
729 */
730 brw_push_insn_state(p);
731 brw_set_default_access_mode(p, BRW_ALIGN_1);
732 dst = retype(dst, BRW_REGISTER_TYPE_UD);
733 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
734 brw_SHR(p, dst, stride(r0, 1, 4, 0),
735 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
736 brw_pop_insn_state(p);
737 }
738
739 void
740 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
741 struct brw_reg src0,
742 struct brw_reg src1,
743 struct brw_reg src2)
744 {
745 brw_push_insn_state(p);
746 brw_set_default_access_mode(p, BRW_ALIGN_1);
747 /* Save src0 data in 16:31 bits of dst.0 */
748 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
749 brw_imm_ud(0xffffu));
750 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
751 /* Save src1 data in 0:15 bits of dst.0 */
752 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
753 brw_imm_ud(0xffffu));
754 brw_OR(p, suboffset(vec1(dst), 0),
755 suboffset(vec1(dst), 0),
756 suboffset(vec1(src2), 0));
757 brw_pop_insn_state(p);
758 }
759
760 void
761 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
762 struct brw_reg dst,
763 struct brw_reg src0,
764 struct brw_reg src1)
765 {
766 /* This opcode uses an implied MRF register for:
767 * - the header of the ff_sync message. And as such it is expected to be
768 * initialized to r0 before calling here.
769 * - the destination where we will write the allocated URB handle.
770 */
771 struct brw_reg header =
772 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
773
774 /* Overwrite dword 0 of the header (SO vertices to write) and
775 * dword 1 (number of primitives written).
776 */
777 brw_push_insn_state(p);
778 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
779 brw_set_default_access_mode(p, BRW_ALIGN_1);
780 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
781 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
782 brw_pop_insn_state(p);
783
784 /* Allocate URB handle in dst */
785 brw_ff_sync(p,
786 dst,
787 0,
788 header,
789 1, /* allocate */
790 1, /* response length */
791 0 /* eot */);
792
793 /* Now put allocated urb handle in header.0 */
794 brw_push_insn_state(p);
795 brw_set_default_access_mode(p, BRW_ALIGN_1);
796 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
797 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
798
799 /* src1 is not an immediate when we use transform feedback */
800 if (src1.file != BRW_IMMEDIATE_VALUE)
801 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
802
803 brw_pop_insn_state(p);
804 }
805
806 void
807 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
808 {
809 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
810 struct brw_reg src = brw_vec8_grf(0, 0);
811 brw_push_insn_state(p);
812 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
813 brw_set_default_access_mode(p, BRW_ALIGN_1);
814 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
815 brw_pop_insn_state(p);
816 }
817
818 void
819 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
820 struct brw_reg index)
821 {
822 int second_vertex_offset;
823
824 if (devinfo->gen >= 6)
825 second_vertex_offset = 1;
826 else
827 second_vertex_offset = 16;
828
829 m1 = retype(m1, BRW_REGISTER_TYPE_D);
830
831 /* Set up M1 (message payload). Only the block offsets in M1.0 and
832 * M1.4 are used, and the rest are ignored.
833 */
834 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
835 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
836 struct brw_reg index_0 = suboffset(vec1(index), 0);
837 struct brw_reg index_4 = suboffset(vec1(index), 4);
838
839 brw_push_insn_state(p);
840 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
841 brw_set_default_access_mode(p, BRW_ALIGN_1);
842
843 brw_MOV(p, m1_0, index_0);
844
845 if (index.file == BRW_IMMEDIATE_VALUE) {
846 index_4.dw1.ud += second_vertex_offset;
847 brw_MOV(p, m1_4, index_4);
848 } else {
849 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
850 }
851
852 brw_pop_insn_state(p);
853 }
854
855 void
856 vec4_generator::generate_unpack_flags(struct brw_reg dst)
857 {
858 brw_push_insn_state(p);
859 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
860 brw_set_default_access_mode(p, BRW_ALIGN_1);
861
862 struct brw_reg flags = brw_flag_reg(0, 0);
863 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
864 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
865
866 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
867 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
868 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
869
870 brw_pop_insn_state(p);
871 }
872
873 void
874 vec4_generator::generate_scratch_read(vec4_instruction *inst,
875 struct brw_reg dst,
876 struct brw_reg index)
877 {
878 struct brw_reg header = brw_vec8_grf(0, 0);
879
880 gen6_resolve_implied_move(p, &header, inst->base_mrf);
881
882 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
883 index);
884
885 uint32_t msg_type;
886
887 if (devinfo->gen >= 6)
888 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
889 else if (devinfo->gen == 5 || devinfo->is_g4x)
890 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
891 else
892 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
893
894 /* Each of the 8 channel enables is considered for whether each
895 * dword is written.
896 */
897 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
898 brw_set_dest(p, send, dst);
899 brw_set_src0(p, send, header);
900 if (devinfo->gen < 6)
901 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
902 brw_set_dp_read_message(p, send,
903 255, /* binding table index: stateless access */
904 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
905 msg_type,
906 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
907 2, /* mlen */
908 true, /* header_present */
909 1 /* rlen */);
910 }
911
912 void
913 vec4_generator::generate_scratch_write(vec4_instruction *inst,
914 struct brw_reg dst,
915 struct brw_reg src,
916 struct brw_reg index)
917 {
918 struct brw_reg header = brw_vec8_grf(0, 0);
919 bool write_commit;
920
921 /* If the instruction is predicated, we'll predicate the send, not
922 * the header setup.
923 */
924 brw_set_default_predicate_control(p, false);
925
926 gen6_resolve_implied_move(p, &header, inst->base_mrf);
927
928 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
929 index);
930
931 brw_MOV(p,
932 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
933 retype(src, BRW_REGISTER_TYPE_D));
934
935 uint32_t msg_type;
936
937 if (devinfo->gen >= 7)
938 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
939 else if (devinfo->gen == 6)
940 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
941 else
942 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
943
944 brw_set_default_predicate_control(p, inst->predicate);
945
946 /* Pre-gen6, we have to specify write commits to ensure ordering
947 * between reads and writes within a thread. Afterwards, that's
948 * guaranteed and write commits only matter for inter-thread
949 * synchronization.
950 */
951 if (devinfo->gen >= 6) {
952 write_commit = false;
953 } else {
954 /* The visitor set up our destination register to be g0. This
955 * means that when the next read comes along, we will end up
956 * reading from g0 and causing a block on the write commit. For
957 * write-after-read, we are relying on the value of the previous
958 * read being used (and thus blocking on completion) before our
959 * write is executed. This means we have to be careful in
960 * instruction scheduling to not violate this assumption.
961 */
962 write_commit = true;
963 }
964
965 /* Each of the 8 channel enables is considered for whether each
966 * dword is written.
967 */
968 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
969 brw_set_dest(p, send, dst);
970 brw_set_src0(p, send, header);
971 if (devinfo->gen < 6)
972 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
973 brw_set_dp_write_message(p, send,
974 255, /* binding table index: stateless access */
975 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
976 msg_type,
977 3, /* mlen */
978 true, /* header present */
979 false, /* not a render target write */
980 write_commit, /* rlen */
981 false, /* eot */
982 write_commit);
983 }
984
985 void
986 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
987 struct brw_reg dst,
988 struct brw_reg index,
989 struct brw_reg offset)
990 {
991 assert(index.file == BRW_IMMEDIATE_VALUE &&
992 index.type == BRW_REGISTER_TYPE_UD);
993 uint32_t surf_index = index.dw1.ud;
994
995 struct brw_reg header = brw_vec8_grf(0, 0);
996
997 gen6_resolve_implied_move(p, &header, inst->base_mrf);
998
999 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
1000 offset);
1001
1002 uint32_t msg_type;
1003
1004 if (devinfo->gen >= 6)
1005 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1006 else if (devinfo->gen == 5 || devinfo->is_g4x)
1007 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1008 else
1009 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1010
1011 /* Each of the 8 channel enables is considered for whether each
1012 * dword is written.
1013 */
1014 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1015 brw_set_dest(p, send, dst);
1016 brw_set_src0(p, send, header);
1017 if (devinfo->gen < 6)
1018 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1019 brw_set_dp_read_message(p, send,
1020 surf_index,
1021 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1022 msg_type,
1023 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1024 2, /* mlen */
1025 true, /* header_present */
1026 1 /* rlen */);
1027
1028 brw_mark_surface_used(&prog_data->base, surf_index);
1029 }
1030
1031 void
1032 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1033 struct brw_reg dst,
1034 struct brw_reg surf_index,
1035 struct brw_reg offset)
1036 {
1037 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1038
1039 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1040
1041 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1042 brw_set_dest(p, insn, dst);
1043 brw_set_src0(p, insn, offset);
1044 brw_set_sampler_message(p, insn,
1045 surf_index.dw1.ud,
1046 0, /* LD message ignores sampler unit */
1047 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1048 1, /* rlen */
1049 inst->mlen,
1050 inst->header_size != 0,
1051 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1052 0);
1053
1054 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1055
1056 } else {
1057
1058 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1059
1060 brw_push_insn_state(p);
1061 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1062 brw_set_default_access_mode(p, BRW_ALIGN_1);
1063
1064 /* a0.0 = surf_index & 0xff */
1065 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1066 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1067 brw_set_dest(p, insn_and, addr);
1068 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1069 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1070
1071 brw_pop_insn_state(p);
1072
1073 /* dst = send(offset, a0.0 | <descriptor>) */
1074 brw_inst *insn = brw_send_indirect_message(
1075 p, BRW_SFID_SAMPLER, dst, offset, addr);
1076 brw_set_sampler_message(p, insn,
1077 0 /* surface */,
1078 0 /* sampler */,
1079 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1080 1 /* rlen */,
1081 inst->mlen,
1082 inst->header_size != 0,
1083 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1084 0);
1085
1086 /* visitor knows more than we do about the surface limit required,
1087 * so has already done marking.
1088 */
1089 }
1090 }
1091
1092 void
1093 vec4_generator::generate_set_simd4x2_header_gen9(vec4_instruction *inst,
1094 struct brw_reg dst)
1095 {
1096 brw_push_insn_state(p);
1097 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1098
1099 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1100 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1101
1102 brw_set_default_access_mode(p, BRW_ALIGN_1);
1103 brw_MOV(p, get_element_ud(dst, 2),
1104 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1105
1106 brw_pop_insn_state(p);
1107 }
1108
1109 void
1110 vec4_generator::generate_code(const cfg_t *cfg)
1111 {
1112 struct annotation_info annotation;
1113 memset(&annotation, 0, sizeof(annotation));
1114 int loop_count = 0;
1115
1116 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1117 struct brw_reg src[3], dst;
1118
1119 if (unlikely(debug_flag))
1120 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1121
1122 for (unsigned int i = 0; i < 3; i++) {
1123 src[i] = inst->get_src(this->prog_data, i);
1124 }
1125 dst = inst->get_dst();
1126
1127 brw_set_default_predicate_control(p, inst->predicate);
1128 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1129 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1130 brw_set_default_saturate(p, inst->saturate);
1131 brw_set_default_mask_control(p, inst->force_writemask_all);
1132 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1133
1134 unsigned pre_emit_nr_insn = p->nr_insn;
1135
1136 if (dst.width == BRW_WIDTH_4) {
1137 /* This happens in attribute fixups for "dual instanced" geometry
1138 * shaders, since they use attributes that are vec4's. Since the exec
1139 * width is only 4, it's essential that the caller set
1140 * force_writemask_all in order to make sure the instruction is executed
1141 * regardless of which channels are enabled.
1142 */
1143 assert(inst->force_writemask_all);
1144
1145 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1146 * the following register region restrictions (from Graphics BSpec:
1147 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1148 * > Register Region Restrictions)
1149 *
1150 * 1. ExecSize must be greater than or equal to Width.
1151 *
1152 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1153 * to Width * HorzStride."
1154 */
1155 for (int i = 0; i < 3; i++) {
1156 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1157 src[i] = stride(src[i], 4, 4, 1);
1158 }
1159 }
1160
1161 switch (inst->opcode) {
1162 case VEC4_OPCODE_UNPACK_UNIFORM:
1163 case BRW_OPCODE_MOV:
1164 brw_MOV(p, dst, src[0]);
1165 break;
1166 case BRW_OPCODE_ADD:
1167 brw_ADD(p, dst, src[0], src[1]);
1168 break;
1169 case BRW_OPCODE_MUL:
1170 brw_MUL(p, dst, src[0], src[1]);
1171 break;
1172 case BRW_OPCODE_MACH:
1173 brw_MACH(p, dst, src[0], src[1]);
1174 break;
1175
1176 case BRW_OPCODE_MAD:
1177 assert(devinfo->gen >= 6);
1178 brw_MAD(p, dst, src[0], src[1], src[2]);
1179 break;
1180
1181 case BRW_OPCODE_FRC:
1182 brw_FRC(p, dst, src[0]);
1183 break;
1184 case BRW_OPCODE_RNDD:
1185 brw_RNDD(p, dst, src[0]);
1186 break;
1187 case BRW_OPCODE_RNDE:
1188 brw_RNDE(p, dst, src[0]);
1189 break;
1190 case BRW_OPCODE_RNDZ:
1191 brw_RNDZ(p, dst, src[0]);
1192 break;
1193
1194 case BRW_OPCODE_AND:
1195 brw_AND(p, dst, src[0], src[1]);
1196 break;
1197 case BRW_OPCODE_OR:
1198 brw_OR(p, dst, src[0], src[1]);
1199 break;
1200 case BRW_OPCODE_XOR:
1201 brw_XOR(p, dst, src[0], src[1]);
1202 break;
1203 case BRW_OPCODE_NOT:
1204 brw_NOT(p, dst, src[0]);
1205 break;
1206 case BRW_OPCODE_ASR:
1207 brw_ASR(p, dst, src[0], src[1]);
1208 break;
1209 case BRW_OPCODE_SHR:
1210 brw_SHR(p, dst, src[0], src[1]);
1211 break;
1212 case BRW_OPCODE_SHL:
1213 brw_SHL(p, dst, src[0], src[1]);
1214 break;
1215
1216 case BRW_OPCODE_CMP:
1217 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1218 break;
1219 case BRW_OPCODE_SEL:
1220 brw_SEL(p, dst, src[0], src[1]);
1221 break;
1222
1223 case BRW_OPCODE_DPH:
1224 brw_DPH(p, dst, src[0], src[1]);
1225 break;
1226
1227 case BRW_OPCODE_DP4:
1228 brw_DP4(p, dst, src[0], src[1]);
1229 break;
1230
1231 case BRW_OPCODE_DP3:
1232 brw_DP3(p, dst, src[0], src[1]);
1233 break;
1234
1235 case BRW_OPCODE_DP2:
1236 brw_DP2(p, dst, src[0], src[1]);
1237 break;
1238
1239 case BRW_OPCODE_F32TO16:
1240 assert(devinfo->gen >= 7);
1241 brw_F32TO16(p, dst, src[0]);
1242 break;
1243
1244 case BRW_OPCODE_F16TO32:
1245 assert(devinfo->gen >= 7);
1246 brw_F16TO32(p, dst, src[0]);
1247 break;
1248
1249 case BRW_OPCODE_LRP:
1250 assert(devinfo->gen >= 6);
1251 brw_LRP(p, dst, src[0], src[1], src[2]);
1252 break;
1253
1254 case BRW_OPCODE_BFREV:
1255 assert(devinfo->gen >= 7);
1256 /* BFREV only supports UD type for src and dst. */
1257 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1258 retype(src[0], BRW_REGISTER_TYPE_UD));
1259 break;
1260 case BRW_OPCODE_FBH:
1261 assert(devinfo->gen >= 7);
1262 /* FBH only supports UD type for dst. */
1263 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1264 break;
1265 case BRW_OPCODE_FBL:
1266 assert(devinfo->gen >= 7);
1267 /* FBL only supports UD type for dst. */
1268 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1269 break;
1270 case BRW_OPCODE_CBIT:
1271 assert(devinfo->gen >= 7);
1272 /* CBIT only supports UD type for dst. */
1273 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1274 break;
1275 case BRW_OPCODE_ADDC:
1276 assert(devinfo->gen >= 7);
1277 brw_ADDC(p, dst, src[0], src[1]);
1278 break;
1279 case BRW_OPCODE_SUBB:
1280 assert(devinfo->gen >= 7);
1281 brw_SUBB(p, dst, src[0], src[1]);
1282 break;
1283 case BRW_OPCODE_MAC:
1284 brw_MAC(p, dst, src[0], src[1]);
1285 break;
1286
1287 case BRW_OPCODE_BFE:
1288 assert(devinfo->gen >= 7);
1289 brw_BFE(p, dst, src[0], src[1], src[2]);
1290 break;
1291
1292 case BRW_OPCODE_BFI1:
1293 assert(devinfo->gen >= 7);
1294 brw_BFI1(p, dst, src[0], src[1]);
1295 break;
1296 case BRW_OPCODE_BFI2:
1297 assert(devinfo->gen >= 7);
1298 brw_BFI2(p, dst, src[0], src[1], src[2]);
1299 break;
1300
1301 case BRW_OPCODE_IF:
1302 if (inst->src[0].file != BAD_FILE) {
1303 /* The instruction has an embedded compare (only allowed on gen6) */
1304 assert(devinfo->gen == 6);
1305 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1306 } else {
1307 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1308 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1309 }
1310 break;
1311
1312 case BRW_OPCODE_ELSE:
1313 brw_ELSE(p);
1314 break;
1315 case BRW_OPCODE_ENDIF:
1316 brw_ENDIF(p);
1317 break;
1318
1319 case BRW_OPCODE_DO:
1320 brw_DO(p, BRW_EXECUTE_8);
1321 break;
1322
1323 case BRW_OPCODE_BREAK:
1324 brw_BREAK(p);
1325 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1326 break;
1327 case BRW_OPCODE_CONTINUE:
1328 brw_CONT(p);
1329 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1330 break;
1331
1332 case BRW_OPCODE_WHILE:
1333 brw_WHILE(p);
1334 loop_count++;
1335 break;
1336
1337 case SHADER_OPCODE_RCP:
1338 case SHADER_OPCODE_RSQ:
1339 case SHADER_OPCODE_SQRT:
1340 case SHADER_OPCODE_EXP2:
1341 case SHADER_OPCODE_LOG2:
1342 case SHADER_OPCODE_SIN:
1343 case SHADER_OPCODE_COS:
1344 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1345 if (devinfo->gen >= 7) {
1346 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1347 brw_null_reg());
1348 } else if (devinfo->gen == 6) {
1349 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1350 } else {
1351 generate_math1_gen4(inst, dst, src[0]);
1352 }
1353 break;
1354
1355 case SHADER_OPCODE_POW:
1356 case SHADER_OPCODE_INT_QUOTIENT:
1357 case SHADER_OPCODE_INT_REMAINDER:
1358 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1359 if (devinfo->gen >= 7) {
1360 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1361 } else if (devinfo->gen == 6) {
1362 generate_math_gen6(inst, dst, src[0], src[1]);
1363 } else {
1364 generate_math2_gen4(inst, dst, src[0], src[1]);
1365 }
1366 break;
1367
1368 case SHADER_OPCODE_TEX:
1369 case SHADER_OPCODE_TXD:
1370 case SHADER_OPCODE_TXF:
1371 case SHADER_OPCODE_TXF_CMS:
1372 case SHADER_OPCODE_TXF_MCS:
1373 case SHADER_OPCODE_TXL:
1374 case SHADER_OPCODE_TXS:
1375 case SHADER_OPCODE_TG4:
1376 case SHADER_OPCODE_TG4_OFFSET:
1377 generate_tex(inst, dst, src[0], src[1]);
1378 break;
1379
1380 case VS_OPCODE_URB_WRITE:
1381 generate_vs_urb_write(inst);
1382 break;
1383
1384 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1385 generate_scratch_read(inst, dst, src[0]);
1386 break;
1387
1388 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1389 generate_scratch_write(inst, dst, src[0], src[1]);
1390 break;
1391
1392 case VS_OPCODE_PULL_CONSTANT_LOAD:
1393 generate_pull_constant_load(inst, dst, src[0], src[1]);
1394 break;
1395
1396 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1397 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1398 break;
1399
1400 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1401 generate_set_simd4x2_header_gen9(inst, dst);
1402 break;
1403
1404 case GS_OPCODE_URB_WRITE:
1405 generate_gs_urb_write(inst);
1406 break;
1407
1408 case GS_OPCODE_URB_WRITE_ALLOCATE:
1409 generate_gs_urb_write_allocate(inst);
1410 break;
1411
1412 case GS_OPCODE_SVB_WRITE:
1413 generate_gs_svb_write(inst, dst, src[0], src[1]);
1414 break;
1415
1416 case GS_OPCODE_SVB_SET_DST_INDEX:
1417 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1418 break;
1419
1420 case GS_OPCODE_THREAD_END:
1421 generate_gs_thread_end(inst);
1422 break;
1423
1424 case GS_OPCODE_SET_WRITE_OFFSET:
1425 generate_gs_set_write_offset(dst, src[0], src[1]);
1426 break;
1427
1428 case GS_OPCODE_SET_VERTEX_COUNT:
1429 generate_gs_set_vertex_count(dst, src[0]);
1430 break;
1431
1432 case GS_OPCODE_FF_SYNC:
1433 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1434 break;
1435
1436 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1437 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1438 break;
1439
1440 case GS_OPCODE_SET_PRIMITIVE_ID:
1441 generate_gs_set_primitive_id(dst);
1442 break;
1443
1444 case GS_OPCODE_SET_DWORD_2:
1445 generate_gs_set_dword_2(dst, src[0]);
1446 break;
1447
1448 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1449 generate_gs_prepare_channel_masks(dst);
1450 break;
1451
1452 case GS_OPCODE_SET_CHANNEL_MASKS:
1453 generate_gs_set_channel_masks(dst, src[0]);
1454 break;
1455
1456 case GS_OPCODE_GET_INSTANCE_ID:
1457 generate_gs_get_instance_id(dst);
1458 break;
1459
1460 case SHADER_OPCODE_SHADER_TIME_ADD:
1461 brw_shader_time_add(p, src[0],
1462 prog_data->base.binding_table.shader_time_start);
1463 brw_mark_surface_used(&prog_data->base,
1464 prog_data->base.binding_table.shader_time_start);
1465 break;
1466
1467 case SHADER_OPCODE_UNTYPED_ATOMIC:
1468 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1469 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
1470 !inst->dst.is_null());
1471 break;
1472
1473 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1474 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1475 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1476 src[2].dw1.ud);
1477 break;
1478
1479 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1480 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1481 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1482 src[2].dw1.ud);
1483 break;
1484
1485 case SHADER_OPCODE_TYPED_ATOMIC:
1486 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1487 brw_typed_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
1488 !inst->dst.is_null());
1489 break;
1490
1491 case SHADER_OPCODE_TYPED_SURFACE_READ:
1492 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1493 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1494 src[2].dw1.ud);
1495 break;
1496
1497 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1498 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1499 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1500 src[2].dw1.ud);
1501 break;
1502
1503 case SHADER_OPCODE_MEMORY_FENCE:
1504 brw_memory_fence(p, dst);
1505 break;
1506
1507 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1508 brw_find_live_channel(p, dst);
1509 break;
1510
1511 case SHADER_OPCODE_BROADCAST:
1512 brw_broadcast(p, dst, src[0], src[1]);
1513 break;
1514
1515 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1516 generate_unpack_flags(dst);
1517 break;
1518
1519 case VEC4_OPCODE_MOV_BYTES: {
1520 /* Moves the low byte from each channel, using an Align1 access mode
1521 * and a <4,1,0> source region.
1522 */
1523 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1524 src[0].type == BRW_REGISTER_TYPE_B);
1525
1526 brw_set_default_access_mode(p, BRW_ALIGN_1);
1527 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1528 src[0].width = BRW_WIDTH_1;
1529 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1530 brw_MOV(p, dst, src[0]);
1531 brw_set_default_access_mode(p, BRW_ALIGN_16);
1532 break;
1533 }
1534
1535 case VEC4_OPCODE_PACK_BYTES: {
1536 /* Is effectively:
1537 *
1538 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1539 *
1540 * but destinations' only regioning is horizontal stride, so instead we
1541 * have to use two instructions:
1542 *
1543 * mov(4) dst<1>:UB src<4,1,0>:UB
1544 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1545 *
1546 * where they pack the four bytes from the low and high four DW.
1547 */
1548 assert(_mesa_is_pow_two(dst.dw1.bits.writemask) &&
1549 dst.dw1.bits.writemask != 0);
1550 unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
1551
1552 dst.type = BRW_REGISTER_TYPE_UB;
1553
1554 brw_set_default_access_mode(p, BRW_ALIGN_1);
1555
1556 src[0].type = BRW_REGISTER_TYPE_UB;
1557 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1558 src[0].width = BRW_WIDTH_1;
1559 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1560 dst.subnr = offset * 4;
1561 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1562 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1563 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1564 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1565
1566 src[0].subnr = 16;
1567 dst.subnr = 16 + offset * 4;
1568 insn = brw_MOV(p, dst, src[0]);
1569 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1570 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1571 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1572
1573 brw_set_default_access_mode(p, BRW_ALIGN_16);
1574 break;
1575 }
1576
1577 default:
1578 unreachable("Unsupported opcode");
1579 }
1580
1581 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1582 /* Handled dependency hints in the generator. */
1583
1584 assert(!inst->conditional_mod);
1585 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1586 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1587 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1588 "emitting more than 1 instruction");
1589
1590 brw_inst *last = &p->store[pre_emit_nr_insn];
1591
1592 if (inst->conditional_mod)
1593 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1594 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1595 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1596 }
1597 }
1598
1599 brw_set_uip_jip(p);
1600 annotation_finalize(&annotation, p->next_insn_offset);
1601
1602 int before_size = p->next_insn_offset;
1603 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1604 int after_size = p->next_insn_offset;
1605
1606 if (unlikely(debug_flag)) {
1607 if (shader_prog) {
1608 fprintf(stderr, "Native code for %s %s shader %d:\n",
1609 shader_prog->Label ? shader_prog->Label : "unnamed",
1610 stage_name, shader_prog->Name);
1611 } else {
1612 fprintf(stderr, "Native code for %s program %d:\n", stage_name,
1613 prog->Id);
1614 }
1615 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1616 " bytes (%.0f%%)\n",
1617 stage_abbrev,
1618 before_size / 16, loop_count, before_size, after_size,
1619 100.0f * (before_size - after_size) / before_size);
1620
1621 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1622 p->devinfo, prog);
1623 ralloc_free(annotation.ann);
1624 }
1625
1626 compiler->shader_debug_log(log_data,
1627 "%s vec4 shader: %d inst, %d loops, "
1628 "compacted %d to %d bytes.\n",
1629 stage_abbrev, before_size / 16, loop_count,
1630 before_size, after_size);
1631 }
1632
1633 const unsigned *
1634 vec4_generator::generate_assembly(const cfg_t *cfg,
1635 unsigned *assembly_size)
1636 {
1637 brw_set_default_access_mode(p, BRW_ALIGN_16);
1638 generate_code(cfg);
1639
1640 return brw_get_program(p, assembly_size);
1641 }
1642
1643 } /* namespace brw */