1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
54 brw_reg
= dst
.fixed_hw_reg
;
58 brw_reg
= brw_null_reg();
62 assert(!"not reached");
63 brw_reg
= brw_null_reg();
70 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
72 struct brw_reg brw_reg
;
74 switch (src
[i
].file
) {
76 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
77 brw_reg
= retype(brw_reg
, src
[i
].type
);
78 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
80 brw_reg
= brw_abs(brw_reg
);
82 brw_reg
= negate(brw_reg
);
86 switch (src
[i
].type
) {
87 case BRW_REGISTER_TYPE_F
:
88 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
90 case BRW_REGISTER_TYPE_D
:
91 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
93 case BRW_REGISTER_TYPE_UD
:
94 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
97 assert(!"not reached");
98 brw_reg
= brw_null_reg();
104 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
105 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
106 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
108 brw_reg
= retype(brw_reg
, src
[i
].type
);
109 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
111 brw_reg
= brw_abs(brw_reg
);
113 brw_reg
= negate(brw_reg
);
115 /* This should have been moved to pull constants. */
116 assert(!src
[i
].reladdr
);
120 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
121 brw_reg
= src
[i
].fixed_hw_reg
;
125 /* Probably unused. */
126 brw_reg
= brw_null_reg();
130 assert(!"not reached");
131 brw_reg
= brw_null_reg();
138 vec4_generator::vec4_generator(struct brw_context
*brw
,
139 struct gl_shader_program
*shader_prog
,
140 struct gl_program
*prog
,
141 struct brw_vec4_prog_data
*prog_data
,
144 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
145 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
147 p
= rzalloc(mem_ctx
, struct brw_compile
);
148 brw_init_compile(brw
, p
, mem_ctx
);
151 vec4_generator::~vec4_generator()
156 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
162 brw_math_function(inst
->opcode
),
165 BRW_MATH_DATA_VECTOR
,
166 BRW_MATH_PRECISION_FULL
);
170 check_gen6_math_src_arg(struct brw_reg src
)
172 /* Source swizzles are ignored. */
175 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
179 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
183 /* Can't do writemask because math can't be align16. */
184 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
185 check_gen6_math_src_arg(src
);
187 brw_set_access_mode(p
, BRW_ALIGN_1
);
190 brw_math_function(inst
->opcode
),
193 BRW_MATH_DATA_SCALAR
,
194 BRW_MATH_PRECISION_FULL
);
195 brw_set_access_mode(p
, BRW_ALIGN_16
);
199 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
206 brw_math_function(inst
->opcode
),
211 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
216 /* Can't do writemask because math can't be align16. */
217 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
218 /* Source swizzles are ignored. */
219 check_gen6_math_src_arg(src0
);
220 check_gen6_math_src_arg(src1
);
222 brw_set_access_mode(p
, BRW_ALIGN_1
);
225 brw_math_function(inst
->opcode
),
227 brw_set_access_mode(p
, BRW_ALIGN_16
);
231 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
236 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
239 * "Operand0[7]. For the INT DIV functions, this operand is the
242 * "Operand1[7]. For the INT DIV functions, this operand is the
245 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
246 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
247 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
249 brw_push_insn_state(p
);
250 brw_set_saturate(p
, false);
251 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
252 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
253 brw_pop_insn_state(p
);
257 brw_math_function(inst
->opcode
),
260 BRW_MATH_DATA_VECTOR
,
261 BRW_MATH_PRECISION_FULL
);
265 vec4_generator::generate_tex(vec4_instruction
*inst
,
272 switch (inst
->opcode
) {
273 case SHADER_OPCODE_TEX
:
274 case SHADER_OPCODE_TXL
:
275 if (inst
->shadow_compare
) {
276 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
278 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
281 case SHADER_OPCODE_TXD
:
282 if (inst
->shadow_compare
) {
283 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
284 assert(brw
->is_haswell
);
285 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
287 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
290 case SHADER_OPCODE_TXF
:
291 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
293 case SHADER_OPCODE_TXF_CMS
:
295 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
297 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
299 case SHADER_OPCODE_TXF_MCS
:
300 assert(brw
->gen
>= 7);
301 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
303 case SHADER_OPCODE_TXS
:
304 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
306 case SHADER_OPCODE_TG4
:
307 if (inst
->shadow_compare
) {
308 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
310 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
313 case SHADER_OPCODE_TG4_OFFSET
:
314 if (inst
->shadow_compare
) {
315 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
317 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
321 assert(!"should not get here: invalid vec4 texture opcode");
325 switch (inst
->opcode
) {
326 case SHADER_OPCODE_TEX
:
327 case SHADER_OPCODE_TXL
:
328 if (inst
->shadow_compare
) {
329 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
330 assert(inst
->mlen
== 3);
332 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
333 assert(inst
->mlen
== 2);
336 case SHADER_OPCODE_TXD
:
337 /* There is no sample_d_c message; comparisons are done manually. */
338 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
339 assert(inst
->mlen
== 4);
341 case SHADER_OPCODE_TXF
:
342 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
343 assert(inst
->mlen
== 2);
345 case SHADER_OPCODE_TXS
:
346 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
347 assert(inst
->mlen
== 2);
350 assert(!"should not get here: invalid vec4 texture opcode");
355 assert(msg_type
!= -1);
357 /* Load the message header if present. If there's a texture offset, we need
358 * to set it up explicitly and load the offset bitfield. Otherwise, we can
359 * use an implied move from g0 to the first message register.
361 if (inst
->header_present
) {
362 if (brw
->gen
< 6 && !inst
->texture_offset
) {
363 /* Set up an implied move from g0 to the MRF. */
364 src
= brw_vec8_grf(0, 0);
366 struct brw_reg header
=
367 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
369 /* Explicitly set up the message header by copying g0 to the MRF. */
370 brw_push_insn_state(p
);
371 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
372 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
374 brw_set_access_mode(p
, BRW_ALIGN_1
);
376 if (inst
->texture_offset
) {
377 /* Set the texel offset bits in DWord 2. */
378 brw_MOV(p
, get_element_ud(header
, 2),
379 brw_imm_ud(inst
->texture_offset
));
382 if (inst
->sampler
>= 16) {
383 /* The "Sampler Index" field can only store values between 0 and 15.
384 * However, we can add an offset to the "Sampler State Pointer"
385 * field, effectively selecting a different set of 16 samplers.
387 * The "Sampler State Pointer" needs to be aligned to a 32-byte
388 * offset, and each sampler state is only 16-bytes, so we can't
389 * exclusively use the offset - we have to use both.
391 assert(brw
->is_haswell
); /* field only exists on Haswell */
393 get_element_ud(header
, 3),
394 get_element_ud(brw_vec8_grf(0, 0), 3),
395 brw_imm_ud(16 * (inst
->sampler
/ 16) *
396 sizeof(gen7_sampler_state
)));
398 brw_pop_insn_state(p
);
402 uint32_t return_format
;
405 case BRW_REGISTER_TYPE_D
:
406 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
408 case BRW_REGISTER_TYPE_UD
:
409 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
412 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
416 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
417 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
418 ? prog_data
->base
.binding_table
.gather_texture_start
419 : prog_data
->base
.binding_table
.texture_start
) + inst
->sampler
;
428 1, /* response length */
430 inst
->header_present
,
431 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
434 brw_mark_surface_used(&prog_data
->base
, surface_index
);
438 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
441 brw_null_reg(), /* dest */
442 inst
->base_mrf
, /* starting mrf reg nr */
443 brw_vec8_grf(0, 0), /* src */
444 inst
->urb_write_flags
,
446 0, /* response len */
447 inst
->offset
, /* urb destination offset */
448 BRW_URB_SWIZZLE_INTERLEAVE
);
452 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
454 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
456 brw_null_reg(), /* dest */
457 inst
->base_mrf
, /* starting mrf reg nr */
459 inst
->urb_write_flags
,
461 0, /* response len */
462 inst
->offset
, /* urb destination offset */
463 BRW_URB_SWIZZLE_INTERLEAVE
);
467 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
469 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
471 brw_null_reg(), /* dest */
472 inst
->base_mrf
, /* starting mrf reg nr */
476 0, /* response len */
477 0, /* urb destination offset */
478 BRW_URB_SWIZZLE_INTERLEAVE
);
482 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
486 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
489 * Slot 0 Offset. This field, after adding to the Global Offset field
490 * in the message descriptor, specifies the offset (in 256-bit units)
491 * from the start of the URB entry, as referenced by URB Handle 0, at
492 * which the data will be accessed.
494 * Similar text describes DWORD M0.4, which is slot 1 offset.
496 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
497 * of the register for geometry shader invocations 0 and 1) by the
498 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
500 * We can do this with the following EU instruction:
502 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
504 brw_push_insn_state(p
);
505 brw_set_access_mode(p
, BRW_ALIGN_1
);
506 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
507 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
509 brw_set_access_mode(p
, BRW_ALIGN_16
);
510 brw_pop_insn_state(p
);
514 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
517 brw_push_insn_state(p
);
518 brw_set_access_mode(p
, BRW_ALIGN_1
);
519 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
521 /* If we think of the src and dst registers as composed of 8 DWORDs each,
522 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
523 * them to WORDs, and then pack them into DWORD 2 of dst.
525 * It's easier to get the EU to do this if we think of the src and dst
526 * registers as composed of 16 WORDS each; then, we want to pick up the
527 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
530 * We can do that by the following EU instruction:
532 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
534 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
535 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
536 brw_set_access_mode(p
, BRW_ALIGN_16
);
537 brw_pop_insn_state(p
);
541 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
544 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
546 brw_push_insn_state(p
);
547 brw_set_access_mode(p
, BRW_ALIGN_1
);
548 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
549 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
550 brw_set_access_mode(p
, BRW_ALIGN_16
);
551 brw_pop_insn_state(p
);
555 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
557 /* We want to left shift just DWORD 4 (the x component belonging to the
558 * second geometry shader invocation) by 4 bits. So generate the
561 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
563 dst
= suboffset(vec1(dst
), 4);
564 brw_push_insn_state(p
);
565 brw_set_access_mode(p
, BRW_ALIGN_1
);
566 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
567 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
568 brw_pop_insn_state(p
);
572 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
575 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
578 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
580 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
581 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
582 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
583 * channel enable to determine the final channel enable. For the
584 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
585 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
586 * in the writeback message. For the URB_WRITE_OWORD &
587 * URB_WRITE_HWORD messages, when final channel enable is 1 it
588 * indicates that Vertex 1 DATA [3] will be written to the surface.
590 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
591 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
593 * 14 Vertex 1 DATA [2] Channel Mask
594 * 13 Vertex 1 DATA [1] Channel Mask
595 * 12 Vertex 1 DATA [0] Channel Mask
596 * 11 Vertex 0 DATA [3] Channel Mask
597 * 10 Vertex 0 DATA [2] Channel Mask
598 * 9 Vertex 0 DATA [1] Channel Mask
599 * 8 Vertex 0 DATA [0] Channel Mask
601 * (This is from a section of the PRM that is agnostic to the particular
602 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
603 * geometry shader invocations 0 and 1, respectively). Since we have the
604 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
605 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
606 * DWORD 4, we just need to OR them together and store the result in bits
609 * It's easier to get the EU to do this if we think of the src and dst
610 * registers as composed of 32 bytes each; then, we want to pick up the
611 * contents of bytes 0 and 16 from src, OR them together, and store them in
614 * We can do that by the following EU instruction:
616 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
618 * Note: this relies on the source register having zeros in (a) bits 7:4 of
619 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
620 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
621 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
622 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
623 * contain valid channel mask values (which are in the range 0x0-0xf).
625 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
626 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
627 brw_push_insn_state(p
);
628 brw_set_access_mode(p
, BRW_ALIGN_1
);
629 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
630 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
631 brw_pop_insn_state(p
);
635 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
637 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
638 * and store into dst.0 & dst.4. So generate the instruction:
640 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
642 brw_push_insn_state(p
);
643 brw_set_access_mode(p
, BRW_ALIGN_1
);
644 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
645 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
646 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
647 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
648 brw_pop_insn_state(p
);
652 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
653 struct brw_reg index
)
655 int second_vertex_offset
;
658 second_vertex_offset
= 1;
660 second_vertex_offset
= 16;
662 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
664 /* Set up M1 (message payload). Only the block offsets in M1.0 and
665 * M1.4 are used, and the rest are ignored.
667 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
668 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
669 struct brw_reg index_0
= suboffset(vec1(index
), 0);
670 struct brw_reg index_4
= suboffset(vec1(index
), 4);
672 brw_push_insn_state(p
);
673 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
674 brw_set_access_mode(p
, BRW_ALIGN_1
);
676 brw_MOV(p
, m1_0
, index_0
);
678 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
679 index_4
.dw1
.ud
+= second_vertex_offset
;
680 brw_MOV(p
, m1_4
, index_4
);
682 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
685 brw_pop_insn_state(p
);
689 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
692 brw_push_insn_state(p
);
693 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
694 brw_set_access_mode(p
, BRW_ALIGN_1
);
696 struct brw_reg flags
= brw_flag_reg(0, 0);
697 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
698 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
700 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
701 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
702 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
704 brw_pop_insn_state(p
);
708 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
710 struct brw_reg index
)
712 struct brw_reg header
= brw_vec8_grf(0, 0);
714 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
716 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
722 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
723 else if (brw
->gen
== 5 || brw
->is_g4x
)
724 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
726 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
728 /* Each of the 8 channel enables is considered for whether each
731 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
732 brw_set_dest(p
, send
, dst
);
733 brw_set_src0(p
, send
, header
);
735 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
736 brw_set_dp_read_message(p
, send
,
737 255, /* binding table index: stateless access */
738 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
740 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
742 true, /* header_present */
747 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
750 struct brw_reg index
)
752 struct brw_reg header
= brw_vec8_grf(0, 0);
755 /* If the instruction is predicated, we'll predicate the send, not
758 brw_set_predicate_control(p
, false);
760 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
762 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
766 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
767 retype(src
, BRW_REGISTER_TYPE_D
));
772 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
773 else if (brw
->gen
== 6)
774 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
776 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
778 brw_set_predicate_control(p
, inst
->predicate
);
780 /* Pre-gen6, we have to specify write commits to ensure ordering
781 * between reads and writes within a thread. Afterwards, that's
782 * guaranteed and write commits only matter for inter-thread
786 write_commit
= false;
788 /* The visitor set up our destination register to be g0. This
789 * means that when the next read comes along, we will end up
790 * reading from g0 and causing a block on the write commit. For
791 * write-after-read, we are relying on the value of the previous
792 * read being used (and thus blocking on completion) before our
793 * write is executed. This means we have to be careful in
794 * instruction scheduling to not violate this assumption.
799 /* Each of the 8 channel enables is considered for whether each
802 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
803 brw_set_dest(p
, send
, dst
);
804 brw_set_src0(p
, send
, header
);
806 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
807 brw_set_dp_write_message(p
, send
,
808 255, /* binding table index: stateless access */
809 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
812 true, /* header present */
813 false, /* not a render target write */
814 write_commit
, /* rlen */
820 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
822 struct brw_reg index
,
823 struct brw_reg offset
)
825 assert(brw
->gen
<= 7);
826 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
827 index
.type
== BRW_REGISTER_TYPE_UD
);
828 uint32_t surf_index
= index
.dw1
.ud
;
830 struct brw_reg header
= brw_vec8_grf(0, 0);
832 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
834 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
840 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
841 else if (brw
->gen
== 5 || brw
->is_g4x
)
842 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
844 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
846 /* Each of the 8 channel enables is considered for whether each
849 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
850 brw_set_dest(p
, send
, dst
);
851 brw_set_src0(p
, send
, header
);
853 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
854 brw_set_dp_read_message(p
, send
,
856 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
858 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
860 true, /* header_present */
863 brw_mark_surface_used(&prog_data
->base
, surf_index
);
867 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
869 struct brw_reg surf_index
,
870 struct brw_reg offset
)
872 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
873 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
875 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
876 brw_set_dest(p
, insn
, dst
);
877 brw_set_src0(p
, insn
, offset
);
878 brw_set_sampler_message(p
, insn
,
880 0, /* LD message ignores sampler unit */
881 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
884 false, /* no header */
885 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
888 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
892 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
894 struct brw_reg atomic_op
,
895 struct brw_reg surf_index
)
897 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
898 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
899 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
900 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
902 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
903 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
906 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
910 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
912 struct brw_reg surf_index
)
914 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
915 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
917 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
921 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
925 * Generate assembly for a Vec4 IR instruction.
927 * \param instruction The Vec4 IR instruction to generate code for.
928 * \param dst The destination register.
929 * \param src An array of up to three source registers.
932 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
936 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
938 if (dst
.width
== BRW_WIDTH_4
) {
939 /* This happens in attribute fixups for "dual instanced" geometry
940 * shaders, since they use attributes that are vec4's. Since the exec
941 * width is only 4, it's essential that the caller set
942 * force_writemask_all in order to make sure the instruction is executed
943 * regardless of which channels are enabled.
945 assert(inst
->force_writemask_all
);
947 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
948 * the following register region restrictions (from Graphics BSpec:
949 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
950 * > Register Region Restrictions)
952 * 1. ExecSize must be greater than or equal to Width.
954 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
955 * to Width * HorzStride."
957 for (int i
= 0; i
< 3; i
++) {
958 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
959 src
[i
] = stride(src
[i
], 4, 4, 1);
963 switch (inst
->opcode
) {
965 brw_MOV(p
, dst
, src
[0]);
968 brw_ADD(p
, dst
, src
[0], src
[1]);
971 brw_MUL(p
, dst
, src
[0], src
[1]);
973 case BRW_OPCODE_MACH
:
974 brw_set_acc_write_control(p
, 1);
975 brw_MACH(p
, dst
, src
[0], src
[1]);
976 brw_set_acc_write_control(p
, 0);
980 assert(brw
->gen
>= 6);
981 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
985 brw_FRC(p
, dst
, src
[0]);
987 case BRW_OPCODE_RNDD
:
988 brw_RNDD(p
, dst
, src
[0]);
990 case BRW_OPCODE_RNDE
:
991 brw_RNDE(p
, dst
, src
[0]);
993 case BRW_OPCODE_RNDZ
:
994 brw_RNDZ(p
, dst
, src
[0]);
998 brw_AND(p
, dst
, src
[0], src
[1]);
1001 brw_OR(p
, dst
, src
[0], src
[1]);
1003 case BRW_OPCODE_XOR
:
1004 brw_XOR(p
, dst
, src
[0], src
[1]);
1006 case BRW_OPCODE_NOT
:
1007 brw_NOT(p
, dst
, src
[0]);
1009 case BRW_OPCODE_ASR
:
1010 brw_ASR(p
, dst
, src
[0], src
[1]);
1012 case BRW_OPCODE_SHR
:
1013 brw_SHR(p
, dst
, src
[0], src
[1]);
1015 case BRW_OPCODE_SHL
:
1016 brw_SHL(p
, dst
, src
[0], src
[1]);
1019 case BRW_OPCODE_CMP
:
1020 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1022 case BRW_OPCODE_SEL
:
1023 brw_SEL(p
, dst
, src
[0], src
[1]);
1026 case BRW_OPCODE_DPH
:
1027 brw_DPH(p
, dst
, src
[0], src
[1]);
1030 case BRW_OPCODE_DP4
:
1031 brw_DP4(p
, dst
, src
[0], src
[1]);
1034 case BRW_OPCODE_DP3
:
1035 brw_DP3(p
, dst
, src
[0], src
[1]);
1038 case BRW_OPCODE_DP2
:
1039 brw_DP2(p
, dst
, src
[0], src
[1]);
1042 case BRW_OPCODE_F32TO16
:
1043 assert(brw
->gen
>= 7);
1044 brw_F32TO16(p
, dst
, src
[0]);
1047 case BRW_OPCODE_F16TO32
:
1048 assert(brw
->gen
>= 7);
1049 brw_F16TO32(p
, dst
, src
[0]);
1052 case BRW_OPCODE_LRP
:
1053 assert(brw
->gen
>= 6);
1054 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1057 case BRW_OPCODE_BFREV
:
1058 assert(brw
->gen
>= 7);
1059 /* BFREV only supports UD type for src and dst. */
1060 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1061 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1063 case BRW_OPCODE_FBH
:
1064 assert(brw
->gen
>= 7);
1065 /* FBH only supports UD type for dst. */
1066 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1068 case BRW_OPCODE_FBL
:
1069 assert(brw
->gen
>= 7);
1070 /* FBL only supports UD type for dst. */
1071 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1073 case BRW_OPCODE_CBIT
:
1074 assert(brw
->gen
>= 7);
1075 /* CBIT only supports UD type for dst. */
1076 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1078 case BRW_OPCODE_ADDC
:
1079 assert(brw
->gen
>= 7);
1080 brw_set_acc_write_control(p
, 1);
1081 brw_ADDC(p
, dst
, src
[0], src
[1]);
1082 brw_set_acc_write_control(p
, 0);
1084 case BRW_OPCODE_SUBB
:
1085 assert(brw
->gen
>= 7);
1086 brw_set_acc_write_control(p
, 1);
1087 brw_SUBB(p
, dst
, src
[0], src
[1]);
1088 brw_set_acc_write_control(p
, 0);
1091 case BRW_OPCODE_BFE
:
1092 assert(brw
->gen
>= 7);
1093 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1096 case BRW_OPCODE_BFI1
:
1097 assert(brw
->gen
>= 7);
1098 brw_BFI1(p
, dst
, src
[0], src
[1]);
1100 case BRW_OPCODE_BFI2
:
1101 assert(brw
->gen
>= 7);
1102 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1106 if (inst
->src
[0].file
!= BAD_FILE
) {
1107 /* The instruction has an embedded compare (only allowed on gen6) */
1108 assert(brw
->gen
== 6);
1109 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1111 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1112 brw_inst
->header
.predicate_control
= inst
->predicate
;
1116 case BRW_OPCODE_ELSE
:
1119 case BRW_OPCODE_ENDIF
:
1124 brw_DO(p
, BRW_EXECUTE_8
);
1127 case BRW_OPCODE_BREAK
:
1129 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1131 case BRW_OPCODE_CONTINUE
:
1132 /* FINISHME: We need to write the loop instruction support still. */
1137 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1140 case BRW_OPCODE_WHILE
:
1144 case SHADER_OPCODE_RCP
:
1145 case SHADER_OPCODE_RSQ
:
1146 case SHADER_OPCODE_SQRT
:
1147 case SHADER_OPCODE_EXP2
:
1148 case SHADER_OPCODE_LOG2
:
1149 case SHADER_OPCODE_SIN
:
1150 case SHADER_OPCODE_COS
:
1151 if (brw
->gen
== 6) {
1152 generate_math1_gen6(inst
, dst
, src
[0]);
1154 /* Also works for Gen7. */
1155 generate_math1_gen4(inst
, dst
, src
[0]);
1159 case SHADER_OPCODE_POW
:
1160 case SHADER_OPCODE_INT_QUOTIENT
:
1161 case SHADER_OPCODE_INT_REMAINDER
:
1162 if (brw
->gen
>= 7) {
1163 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1164 } else if (brw
->gen
== 6) {
1165 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1167 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1171 case SHADER_OPCODE_TEX
:
1172 case SHADER_OPCODE_TXD
:
1173 case SHADER_OPCODE_TXF
:
1174 case SHADER_OPCODE_TXF_CMS
:
1175 case SHADER_OPCODE_TXF_MCS
:
1176 case SHADER_OPCODE_TXL
:
1177 case SHADER_OPCODE_TXS
:
1178 case SHADER_OPCODE_TG4
:
1179 case SHADER_OPCODE_TG4_OFFSET
:
1180 generate_tex(inst
, dst
, src
[0]);
1183 case VS_OPCODE_URB_WRITE
:
1184 generate_vs_urb_write(inst
);
1187 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1188 generate_scratch_read(inst
, dst
, src
[0]);
1191 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1192 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1195 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1196 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1199 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1200 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1203 case GS_OPCODE_URB_WRITE
:
1204 generate_gs_urb_write(inst
);
1207 case GS_OPCODE_THREAD_END
:
1208 generate_gs_thread_end(inst
);
1211 case GS_OPCODE_SET_WRITE_OFFSET
:
1212 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1215 case GS_OPCODE_SET_VERTEX_COUNT
:
1216 generate_gs_set_vertex_count(dst
, src
[0]);
1219 case GS_OPCODE_SET_DWORD_2_IMMED
:
1220 generate_gs_set_dword_2_immed(dst
, src
[0]);
1223 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1224 generate_gs_prepare_channel_masks(dst
);
1227 case GS_OPCODE_SET_CHANNEL_MASKS
:
1228 generate_gs_set_channel_masks(dst
, src
[0]);
1231 case GS_OPCODE_GET_INSTANCE_ID
:
1232 generate_gs_get_instance_id(dst
);
1235 case SHADER_OPCODE_SHADER_TIME_ADD
:
1236 brw_shader_time_add(p
, src
[0],
1237 prog_data
->base
.binding_table
.shader_time_start
);
1238 brw_mark_surface_used(&prog_data
->base
,
1239 prog_data
->base
.binding_table
.shader_time_start
);
1242 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1243 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1246 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1247 generate_untyped_surface_read(inst
, dst
, src
[0]);
1250 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1251 generate_unpack_flags(inst
, dst
);
1255 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1256 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1257 opcode_descs
[inst
->opcode
].name
);
1259 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1266 vec4_generator::generate_code(exec_list
*instructions
)
1268 int last_native_insn_offset
= 0;
1269 const char *last_annotation_string
= NULL
;
1270 const void *last_annotation_ir
= NULL
;
1272 if (unlikely(debug_flag
)) {
1274 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1275 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1278 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1282 foreach_list(node
, instructions
) {
1283 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1284 struct brw_reg src
[3], dst
;
1286 if (unlikely(debug_flag
)) {
1287 if (last_annotation_ir
!= inst
->ir
) {
1288 last_annotation_ir
= inst
->ir
;
1289 if (last_annotation_ir
) {
1290 fprintf(stderr
, " ");
1292 ((ir_instruction
*) last_annotation_ir
)->fprint(stderr
);
1294 const prog_instruction
*vpi
;
1295 vpi
= (const prog_instruction
*) inst
->ir
;
1296 fprintf(stderr
, "%d: ", (int)(vpi
- prog
->Instructions
));
1297 _mesa_fprint_instruction_opt(stderr
, vpi
, 0,
1298 PROG_PRINT_DEBUG
, NULL
);
1300 fprintf(stderr
, "\n");
1303 if (last_annotation_string
!= inst
->annotation
) {
1304 last_annotation_string
= inst
->annotation
;
1305 if (last_annotation_string
)
1306 fprintf(stderr
, " %s\n", last_annotation_string
);
1310 for (unsigned int i
= 0; i
< 3; i
++) {
1311 src
[i
] = inst
->get_src(this->prog_data
, i
);
1313 dst
= inst
->get_dst();
1315 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1316 brw_set_predicate_control(p
, inst
->predicate
);
1317 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1318 brw_set_saturate(p
, inst
->saturate
);
1319 brw_set_mask_control(p
, inst
->force_writemask_all
);
1321 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1323 generate_vec4_instruction(inst
, dst
, src
);
1325 if (inst
->no_dd_clear
|| inst
->no_dd_check
) {
1326 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1327 !"no_dd_check or no_dd_clear set for IR emitting more "
1328 "than 1 instruction");
1330 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
1332 if (inst
->no_dd_clear
)
1333 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
1334 if (inst
->no_dd_check
)
1335 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
1338 if (unlikely(debug_flag
)) {
1339 brw_dump_compile(p
, stderr
,
1340 last_native_insn_offset
, p
->next_insn_offset
);
1343 last_native_insn_offset
= p
->next_insn_offset
;
1346 if (unlikely(debug_flag
)) {
1347 fprintf(stderr
, "\n");
1352 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1353 * emit issues, it doesn't get the jump distances into the output,
1354 * which is often something we want to debug. So this is here in
1355 * case you're doing that.
1357 if (0 && unlikely(debug_flag
)) {
1358 brw_dump_compile(p
, stderr
, 0, p
->next_insn_offset
);
1363 vec4_generator::generate_assembly(exec_list
*instructions
,
1364 unsigned *assembly_size
)
1366 brw_set_access_mode(p
, BRW_ALIGN_16
);
1367 generate_code(instructions
);
1368 return brw_get_program(p
, assembly_size
);
1371 } /* namespace brw */