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i965/skl: Don't use ALL_SLICES_AT_EACH_LOD
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include <ctype.h>
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26
27 extern "C" {
28 #include "brw_eu.h"
29 #include "main/macros.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
32 };
33
34 namespace brw {
35
36 struct brw_reg
37 vec4_instruction::get_dst(void)
38 {
39 struct brw_reg brw_reg;
40
41 switch (dst.file) {
42 case GRF:
43 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
44 brw_reg = retype(brw_reg, dst.type);
45 brw_reg.dw1.bits.writemask = dst.writemask;
46 break;
47
48 case MRF:
49 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
50 brw_reg = retype(brw_reg, dst.type);
51 brw_reg.dw1.bits.writemask = dst.writemask;
52 break;
53
54 case HW_REG:
55 assert(dst.type == dst.fixed_hw_reg.type);
56 brw_reg = dst.fixed_hw_reg;
57 break;
58
59 case BAD_FILE:
60 brw_reg = brw_null_reg();
61 break;
62
63 default:
64 unreachable("not reached");
65 }
66 return brw_reg;
67 }
68
69 struct brw_reg
70 vec4_instruction::get_src(const struct brw_vue_prog_data *prog_data, int i)
71 {
72 struct brw_reg brw_reg;
73
74 switch (src[i].file) {
75 case GRF:
76 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
77 brw_reg = retype(brw_reg, src[i].type);
78 brw_reg.dw1.bits.swizzle = src[i].swizzle;
79 if (src[i].abs)
80 brw_reg = brw_abs(brw_reg);
81 if (src[i].negate)
82 brw_reg = negate(brw_reg);
83 break;
84
85 case IMM:
86 switch (src[i].type) {
87 case BRW_REGISTER_TYPE_F:
88 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
89 break;
90 case BRW_REGISTER_TYPE_D:
91 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
92 break;
93 case BRW_REGISTER_TYPE_UD:
94 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
95 break;
96 case BRW_REGISTER_TYPE_VF:
97 brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
98 break;
99 default:
100 unreachable("not reached");
101 }
102 break;
103
104 case UNIFORM:
105 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
106 (src[i].reg + src[i].reg_offset) / 2,
107 ((src[i].reg + src[i].reg_offset) % 2) * 4),
108 0, 4, 1);
109 brw_reg = retype(brw_reg, src[i].type);
110 brw_reg.dw1.bits.swizzle = src[i].swizzle;
111 if (src[i].abs)
112 brw_reg = brw_abs(brw_reg);
113 if (src[i].negate)
114 brw_reg = negate(brw_reg);
115
116 /* This should have been moved to pull constants. */
117 assert(!src[i].reladdr);
118 break;
119
120 case HW_REG:
121 assert(src[i].type == src[i].fixed_hw_reg.type);
122 brw_reg = src[i].fixed_hw_reg;
123 break;
124
125 case BAD_FILE:
126 /* Probably unused. */
127 brw_reg = brw_null_reg();
128 break;
129 case ATTR:
130 default:
131 unreachable("not reached");
132 }
133
134 return brw_reg;
135 }
136
137 vec4_generator::vec4_generator(struct brw_context *brw,
138 struct gl_shader_program *shader_prog,
139 struct gl_program *prog,
140 struct brw_vue_prog_data *prog_data,
141 void *mem_ctx,
142 bool debug_flag,
143 const char *stage_name,
144 const char *stage_abbrev)
145 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
146 mem_ctx(mem_ctx), stage_name(stage_name), stage_abbrev(stage_abbrev),
147 debug_flag(debug_flag)
148 {
149 p = rzalloc(mem_ctx, struct brw_compile);
150 brw_init_compile(brw, p, mem_ctx);
151 }
152
153 vec4_generator::~vec4_generator()
154 {
155 }
156
157 void
158 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
159 struct brw_reg dst,
160 struct brw_reg src)
161 {
162 gen4_math(p,
163 dst,
164 brw_math_function(inst->opcode),
165 inst->base_mrf,
166 src,
167 BRW_MATH_PRECISION_FULL);
168 }
169
170 static void
171 check_gen6_math_src_arg(struct brw_reg src)
172 {
173 /* Source swizzles are ignored. */
174 assert(!src.abs);
175 assert(!src.negate);
176 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
177 }
178
179 void
180 vec4_generator::generate_math_gen6(vec4_instruction *inst,
181 struct brw_reg dst,
182 struct brw_reg src0,
183 struct brw_reg src1)
184 {
185 /* Can't do writemask because math can't be align16. */
186 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
187 /* Source swizzles are ignored. */
188 check_gen6_math_src_arg(src0);
189 if (src1.file == BRW_GENERAL_REGISTER_FILE)
190 check_gen6_math_src_arg(src1);
191
192 brw_set_default_access_mode(p, BRW_ALIGN_1);
193 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
194 brw_set_default_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
204 * "Message Payload":
205 *
206 * "Operand0[7]. For the INT DIV functions, this operand is the
207 * denominator."
208 * ...
209 * "Operand1[7]. For the INT DIV functions, this operand is the
210 * numerator."
211 */
212 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
213 struct brw_reg &op0 = is_int_div ? src1 : src0;
214 struct brw_reg &op1 = is_int_div ? src0 : src1;
215
216 brw_push_insn_state(p);
217 brw_set_default_saturate(p, false);
218 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
219 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
220 brw_pop_insn_state(p);
221
222 gen4_math(p,
223 dst,
224 brw_math_function(inst->opcode),
225 inst->base_mrf,
226 op0,
227 BRW_MATH_PRECISION_FULL);
228 }
229
230 void
231 vec4_generator::generate_tex(vec4_instruction *inst,
232 struct brw_reg dst,
233 struct brw_reg src,
234 struct brw_reg sampler_index)
235 {
236 int msg_type = -1;
237
238 if (brw->gen >= 5) {
239 switch (inst->opcode) {
240 case SHADER_OPCODE_TEX:
241 case SHADER_OPCODE_TXL:
242 if (inst->shadow_compare) {
243 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
244 } else {
245 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
246 }
247 break;
248 case SHADER_OPCODE_TXD:
249 if (inst->shadow_compare) {
250 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
251 assert(brw->gen >= 8 || brw->is_haswell);
252 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
253 } else {
254 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
255 }
256 break;
257 case SHADER_OPCODE_TXF:
258 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
259 break;
260 case SHADER_OPCODE_TXF_CMS:
261 if (brw->gen >= 7)
262 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
263 else
264 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
265 break;
266 case SHADER_OPCODE_TXF_MCS:
267 assert(brw->gen >= 7);
268 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
269 break;
270 case SHADER_OPCODE_TXS:
271 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
272 break;
273 case SHADER_OPCODE_TG4:
274 if (inst->shadow_compare) {
275 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
276 } else {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
278 }
279 break;
280 case SHADER_OPCODE_TG4_OFFSET:
281 if (inst->shadow_compare) {
282 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
283 } else {
284 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
285 }
286 break;
287 default:
288 unreachable("should not get here: invalid vec4 texture opcode");
289 }
290 } else {
291 switch (inst->opcode) {
292 case SHADER_OPCODE_TEX:
293 case SHADER_OPCODE_TXL:
294 if (inst->shadow_compare) {
295 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
296 assert(inst->mlen == 3);
297 } else {
298 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
299 assert(inst->mlen == 2);
300 }
301 break;
302 case SHADER_OPCODE_TXD:
303 /* There is no sample_d_c message; comparisons are done manually. */
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
305 assert(inst->mlen == 4);
306 break;
307 case SHADER_OPCODE_TXF:
308 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
309 assert(inst->mlen == 2);
310 break;
311 case SHADER_OPCODE_TXS:
312 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
313 assert(inst->mlen == 2);
314 break;
315 default:
316 unreachable("should not get here: invalid vec4 texture opcode");
317 }
318 }
319
320 assert(msg_type != -1);
321
322 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
323
324 /* Load the message header if present. If there's a texture offset, we need
325 * to set it up explicitly and load the offset bitfield. Otherwise, we can
326 * use an implied move from g0 to the first message register.
327 */
328 if (inst->header_present) {
329 if (brw->gen < 6 && !inst->offset) {
330 /* Set up an implied move from g0 to the MRF. */
331 src = brw_vec8_grf(0, 0);
332 } else {
333 struct brw_reg header =
334 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
335 uint32_t dw2 = 0;
336
337 /* Explicitly set up the message header by copying g0 to the MRF. */
338 brw_push_insn_state(p);
339 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
340 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
341
342 brw_set_default_access_mode(p, BRW_ALIGN_1);
343
344 if (inst->offset)
345 /* Set the texel offset bits in DWord 2. */
346 dw2 = inst->offset;
347
348 if (brw->gen >= 9)
349 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
350 * based on bit 22 in the header.
351 */
352 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
353
354 if (dw2)
355 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
356
357 brw_adjust_sampler_state_pointer(p, header, sampler_index);
358 brw_pop_insn_state(p);
359 }
360 }
361
362 uint32_t return_format;
363
364 switch (dst.type) {
365 case BRW_REGISTER_TYPE_D:
366 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
367 break;
368 case BRW_REGISTER_TYPE_UD:
369 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
370 break;
371 default:
372 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
373 break;
374 }
375
376 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
377 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
378 ? prog_data->base.binding_table.gather_texture_start
379 : prog_data->base.binding_table.texture_start;
380
381 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
382 uint32_t sampler = sampler_index.dw1.ud;
383
384 brw_SAMPLE(p,
385 dst,
386 inst->base_mrf,
387 src,
388 sampler + base_binding_table_index,
389 sampler % 16,
390 msg_type,
391 1, /* response length */
392 inst->mlen,
393 inst->header_present,
394 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
395 return_format);
396
397 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
398 } else {
399 /* Non-constant sampler index. */
400 /* Note: this clobbers `dst` as a temporary before emitting the send */
401
402 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
403 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
404
405 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
406
407 brw_push_insn_state(p);
408 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
409 brw_set_default_access_mode(p, BRW_ALIGN_1);
410
411 /* Some care required: `sampler` and `temp` may alias:
412 * addr = sampler & 0xff
413 * temp = (sampler << 8) & 0xf00
414 * addr = addr | temp
415 */
416 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
417 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
418 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
419 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
420 brw_OR(p, addr, addr, temp);
421
422 brw_pop_insn_state(p);
423
424 /* dst = send(offset, a0.0 | <descriptor>) */
425 brw_inst *insn = brw_send_indirect_message(
426 p, BRW_SFID_SAMPLER, dst, src, addr);
427 brw_set_sampler_message(p, insn,
428 0 /* surface */,
429 0 /* sampler */,
430 msg_type,
431 1 /* rlen */,
432 inst->mlen /* mlen */,
433 inst->header_present /* header */,
434 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
435 return_format);
436
437 /* visitor knows more than we do about the surface limit required,
438 * so has already done marking.
439 */
440 }
441 }
442
443 void
444 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
445 {
446 brw_urb_WRITE(p,
447 brw_null_reg(), /* dest */
448 inst->base_mrf, /* starting mrf reg nr */
449 brw_vec8_grf(0, 0), /* src */
450 inst->urb_write_flags,
451 inst->mlen,
452 0, /* response len */
453 inst->offset, /* urb destination offset */
454 BRW_URB_SWIZZLE_INTERLEAVE);
455 }
456
457 void
458 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
459 {
460 struct brw_reg src = brw_message_reg(inst->base_mrf);
461 brw_urb_WRITE(p,
462 brw_null_reg(), /* dest */
463 inst->base_mrf, /* starting mrf reg nr */
464 src,
465 inst->urb_write_flags,
466 inst->mlen,
467 0, /* response len */
468 inst->offset, /* urb destination offset */
469 BRW_URB_SWIZZLE_INTERLEAVE);
470 }
471
472 void
473 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
474 {
475 struct brw_reg src = brw_message_reg(inst->base_mrf);
476
477 /* We pass the temporary passed in src0 as the writeback register */
478 brw_urb_WRITE(p,
479 inst->get_src(this->prog_data, 0), /* dest */
480 inst->base_mrf, /* starting mrf reg nr */
481 src,
482 BRW_URB_WRITE_ALLOCATE_COMPLETE,
483 inst->mlen,
484 1, /* response len */
485 inst->offset, /* urb destination offset */
486 BRW_URB_SWIZZLE_INTERLEAVE);
487
488 /* Now put allocated urb handle in dst.0 */
489 brw_push_insn_state(p);
490 brw_set_default_access_mode(p, BRW_ALIGN_1);
491 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
492 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
493 get_element_ud(inst->get_src(this->prog_data, 0), 0));
494 brw_set_default_access_mode(p, BRW_ALIGN_16);
495 brw_pop_insn_state(p);
496 }
497
498 void
499 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
500 {
501 struct brw_reg src = brw_message_reg(inst->base_mrf);
502 brw_urb_WRITE(p,
503 brw_null_reg(), /* dest */
504 inst->base_mrf, /* starting mrf reg nr */
505 src,
506 BRW_URB_WRITE_EOT | inst->urb_write_flags,
507 brw->gen >= 8 ? 2 : 1,/* message len */
508 0, /* response len */
509 0, /* urb destination offset */
510 BRW_URB_SWIZZLE_INTERLEAVE);
511 }
512
513 void
514 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
515 struct brw_reg src0,
516 struct brw_reg src1)
517 {
518 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
519 * Header: M0.3):
520 *
521 * Slot 0 Offset. This field, after adding to the Global Offset field
522 * in the message descriptor, specifies the offset (in 256-bit units)
523 * from the start of the URB entry, as referenced by URB Handle 0, at
524 * which the data will be accessed.
525 *
526 * Similar text describes DWORD M0.4, which is slot 1 offset.
527 *
528 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
529 * of the register for geometry shader invocations 0 and 1) by the
530 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
531 *
532 * We can do this with the following EU instruction:
533 *
534 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
535 */
536 brw_push_insn_state(p);
537 brw_set_default_access_mode(p, BRW_ALIGN_1);
538 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
539 assert(brw->gen >= 7 &&
540 src1.file == BRW_IMMEDIATE_VALUE &&
541 src1.type == BRW_REGISTER_TYPE_UD &&
542 src1.dw1.ud <= USHRT_MAX);
543 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
544 retype(src1, BRW_REGISTER_TYPE_UW));
545 brw_set_default_access_mode(p, BRW_ALIGN_16);
546 brw_pop_insn_state(p);
547 }
548
549 void
550 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
551 struct brw_reg src)
552 {
553 brw_push_insn_state(p);
554 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
555
556 if (brw->gen >= 8) {
557 /* Move the vertex count into the second MRF for the EOT write. */
558 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
559 src);
560 } else {
561 /* If we think of the src and dst registers as composed of 8 DWORDs each,
562 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
563 * them to WORDs, and then pack them into DWORD 2 of dst.
564 *
565 * It's easier to get the EU to do this if we think of the src and dst
566 * registers as composed of 16 WORDS each; then, we want to pick up the
567 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
568 * of dst.
569 *
570 * We can do that by the following EU instruction:
571 *
572 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
573 */
574 brw_set_default_access_mode(p, BRW_ALIGN_1);
575 brw_MOV(p,
576 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
577 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
578 brw_set_default_access_mode(p, BRW_ALIGN_16);
579 }
580 brw_pop_insn_state(p);
581 }
582
583 void
584 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
585 struct brw_reg dst,
586 struct brw_reg src0,
587 struct brw_reg src1)
588 {
589 int binding = inst->sol_binding;
590 bool final_write = inst->sol_final_write;
591
592 brw_push_insn_state(p);
593 /* Copy Vertex data into M0.x */
594 brw_MOV(p, stride(dst, 4, 4, 1),
595 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
596
597 /* Send SVB Write */
598 brw_svb_write(p,
599 final_write ? src1 : brw_null_reg(), /* dest == src1 */
600 1, /* msg_reg_nr */
601 dst, /* src0 == previous dst */
602 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
603 final_write); /* send_commit_msg */
604
605 /* Finally, wait for the write commit to occur so that we can proceed to
606 * other things safely.
607 *
608 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
609 *
610 * The write commit does not modify the destination register, but
611 * merely clears the dependency associated with the destination
612 * register. Thus, a simple “mov” instruction using the register as a
613 * source is sufficient to wait for the write commit to occur.
614 */
615 if (final_write) {
616 brw_MOV(p, src1, src1);
617 }
618 brw_pop_insn_state(p);
619 }
620
621 void
622 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
623 struct brw_reg dst,
624 struct brw_reg src)
625 {
626
627 int vertex = inst->sol_vertex;
628 brw_push_insn_state(p);
629 brw_set_default_access_mode(p, BRW_ALIGN_1);
630 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
631 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
632 brw_pop_insn_state(p);
633 }
634
635 void
636 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
637 {
638 brw_push_insn_state(p);
639 brw_set_default_access_mode(p, BRW_ALIGN_1);
640 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
641 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
642 brw_pop_insn_state(p);
643 }
644
645 void
646 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
647 {
648 /* We want to left shift just DWORD 4 (the x component belonging to the
649 * second geometry shader invocation) by 4 bits. So generate the
650 * instruction:
651 *
652 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
653 */
654 dst = suboffset(vec1(dst), 4);
655 brw_push_insn_state(p);
656 brw_set_default_access_mode(p, BRW_ALIGN_1);
657 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
658 brw_SHL(p, dst, dst, brw_imm_ud(4));
659 brw_pop_insn_state(p);
660 }
661
662 void
663 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
664 struct brw_reg src)
665 {
666 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
667 * Header: M0.5):
668 *
669 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
670 *
671 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
672 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
673 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
674 * channel enable to determine the final channel enable. For the
675 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
676 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
677 * in the writeback message. For the URB_WRITE_OWORD &
678 * URB_WRITE_HWORD messages, when final channel enable is 1 it
679 * indicates that Vertex 1 DATA [3] will be written to the surface.
680 *
681 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
682 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
683 *
684 * 14 Vertex 1 DATA [2] Channel Mask
685 * 13 Vertex 1 DATA [1] Channel Mask
686 * 12 Vertex 1 DATA [0] Channel Mask
687 * 11 Vertex 0 DATA [3] Channel Mask
688 * 10 Vertex 0 DATA [2] Channel Mask
689 * 9 Vertex 0 DATA [1] Channel Mask
690 * 8 Vertex 0 DATA [0] Channel Mask
691 *
692 * (This is from a section of the PRM that is agnostic to the particular
693 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
694 * geometry shader invocations 0 and 1, respectively). Since we have the
695 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
696 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
697 * DWORD 4, we just need to OR them together and store the result in bits
698 * 15:8 of DWORD 5.
699 *
700 * It's easier to get the EU to do this if we think of the src and dst
701 * registers as composed of 32 bytes each; then, we want to pick up the
702 * contents of bytes 0 and 16 from src, OR them together, and store them in
703 * byte 21.
704 *
705 * We can do that by the following EU instruction:
706 *
707 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
708 *
709 * Note: this relies on the source register having zeros in (a) bits 7:4 of
710 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
711 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
712 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
713 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
714 * contain valid channel mask values (which are in the range 0x0-0xf).
715 */
716 dst = retype(dst, BRW_REGISTER_TYPE_UB);
717 src = retype(src, BRW_REGISTER_TYPE_UB);
718 brw_push_insn_state(p);
719 brw_set_default_access_mode(p, BRW_ALIGN_1);
720 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
721 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
722 brw_pop_insn_state(p);
723 }
724
725 void
726 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
727 {
728 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
729 * and store into dst.0 & dst.4. So generate the instruction:
730 *
731 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
732 */
733 brw_push_insn_state(p);
734 brw_set_default_access_mode(p, BRW_ALIGN_1);
735 dst = retype(dst, BRW_REGISTER_TYPE_UD);
736 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
737 brw_SHR(p, dst, stride(r0, 1, 4, 0),
738 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
739 brw_pop_insn_state(p);
740 }
741
742 void
743 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
744 struct brw_reg src0,
745 struct brw_reg src1,
746 struct brw_reg src2)
747 {
748 brw_push_insn_state(p);
749 brw_set_default_access_mode(p, BRW_ALIGN_1);
750 /* Save src0 data in 16:31 bits of dst.0 */
751 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
752 brw_imm_ud(0xffffu));
753 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
754 /* Save src1 data in 0:15 bits of dst.0 */
755 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
756 brw_imm_ud(0xffffu));
757 brw_OR(p, suboffset(vec1(dst), 0),
758 suboffset(vec1(dst), 0),
759 suboffset(vec1(src2), 0));
760 brw_pop_insn_state(p);
761 }
762
763 void
764 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
765 struct brw_reg dst,
766 struct brw_reg src0,
767 struct brw_reg src1)
768 {
769 /* This opcode uses an implied MRF register for:
770 * - the header of the ff_sync message. And as such it is expected to be
771 * initialized to r0 before calling here.
772 * - the destination where we will write the allocated URB handle.
773 */
774 struct brw_reg header =
775 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
776
777 /* Overwrite dword 0 of the header (SO vertices to write) and
778 * dword 1 (number of primitives written).
779 */
780 brw_push_insn_state(p);
781 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
782 brw_set_default_access_mode(p, BRW_ALIGN_1);
783 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
784 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
785 brw_pop_insn_state(p);
786
787 /* Allocate URB handle in dst */
788 brw_ff_sync(p,
789 dst,
790 0,
791 header,
792 1, /* allocate */
793 1, /* response length */
794 0 /* eot */);
795
796 /* Now put allocated urb handle in header.0 */
797 brw_push_insn_state(p);
798 brw_set_default_access_mode(p, BRW_ALIGN_1);
799 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
800 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
801
802 /* src1 is not an immediate when we use transform feedback */
803 if (src1.file != BRW_IMMEDIATE_VALUE)
804 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
805
806 brw_pop_insn_state(p);
807 }
808
809 void
810 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
811 {
812 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
813 struct brw_reg src = brw_vec8_grf(0, 0);
814 brw_push_insn_state(p);
815 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
816 brw_set_default_access_mode(p, BRW_ALIGN_1);
817 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
818 brw_pop_insn_state(p);
819 }
820
821 void
822 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
823 struct brw_reg index)
824 {
825 int second_vertex_offset;
826
827 if (brw->gen >= 6)
828 second_vertex_offset = 1;
829 else
830 second_vertex_offset = 16;
831
832 m1 = retype(m1, BRW_REGISTER_TYPE_D);
833
834 /* Set up M1 (message payload). Only the block offsets in M1.0 and
835 * M1.4 are used, and the rest are ignored.
836 */
837 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
838 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
839 struct brw_reg index_0 = suboffset(vec1(index), 0);
840 struct brw_reg index_4 = suboffset(vec1(index), 4);
841
842 brw_push_insn_state(p);
843 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
844 brw_set_default_access_mode(p, BRW_ALIGN_1);
845
846 brw_MOV(p, m1_0, index_0);
847
848 if (index.file == BRW_IMMEDIATE_VALUE) {
849 index_4.dw1.ud += second_vertex_offset;
850 brw_MOV(p, m1_4, index_4);
851 } else {
852 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
853 }
854
855 brw_pop_insn_state(p);
856 }
857
858 void
859 vec4_generator::generate_unpack_flags(struct brw_reg dst)
860 {
861 brw_push_insn_state(p);
862 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
863 brw_set_default_access_mode(p, BRW_ALIGN_1);
864
865 struct brw_reg flags = brw_flag_reg(0, 0);
866 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
867 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
868
869 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
870 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
871 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
872
873 brw_pop_insn_state(p);
874 }
875
876 void
877 vec4_generator::generate_scratch_read(vec4_instruction *inst,
878 struct brw_reg dst,
879 struct brw_reg index)
880 {
881 struct brw_reg header = brw_vec8_grf(0, 0);
882
883 gen6_resolve_implied_move(p, &header, inst->base_mrf);
884
885 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
886 index);
887
888 uint32_t msg_type;
889
890 if (brw->gen >= 6)
891 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
892 else if (brw->gen == 5 || brw->is_g4x)
893 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
894 else
895 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
896
897 /* Each of the 8 channel enables is considered for whether each
898 * dword is written.
899 */
900 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
901 brw_set_dest(p, send, dst);
902 brw_set_src0(p, send, header);
903 if (brw->gen < 6)
904 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
905 brw_set_dp_read_message(p, send,
906 255, /* binding table index: stateless access */
907 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
908 msg_type,
909 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
910 2, /* mlen */
911 true, /* header_present */
912 1 /* rlen */);
913 }
914
915 void
916 vec4_generator::generate_scratch_write(vec4_instruction *inst,
917 struct brw_reg dst,
918 struct brw_reg src,
919 struct brw_reg index)
920 {
921 struct brw_reg header = brw_vec8_grf(0, 0);
922 bool write_commit;
923
924 /* If the instruction is predicated, we'll predicate the send, not
925 * the header setup.
926 */
927 brw_set_default_predicate_control(p, false);
928
929 gen6_resolve_implied_move(p, &header, inst->base_mrf);
930
931 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
932 index);
933
934 brw_MOV(p,
935 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
936 retype(src, BRW_REGISTER_TYPE_D));
937
938 uint32_t msg_type;
939
940 if (brw->gen >= 7)
941 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
942 else if (brw->gen == 6)
943 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
944 else
945 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
946
947 brw_set_default_predicate_control(p, inst->predicate);
948
949 /* Pre-gen6, we have to specify write commits to ensure ordering
950 * between reads and writes within a thread. Afterwards, that's
951 * guaranteed and write commits only matter for inter-thread
952 * synchronization.
953 */
954 if (brw->gen >= 6) {
955 write_commit = false;
956 } else {
957 /* The visitor set up our destination register to be g0. This
958 * means that when the next read comes along, we will end up
959 * reading from g0 and causing a block on the write commit. For
960 * write-after-read, we are relying on the value of the previous
961 * read being used (and thus blocking on completion) before our
962 * write is executed. This means we have to be careful in
963 * instruction scheduling to not violate this assumption.
964 */
965 write_commit = true;
966 }
967
968 /* Each of the 8 channel enables is considered for whether each
969 * dword is written.
970 */
971 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
972 brw_set_dest(p, send, dst);
973 brw_set_src0(p, send, header);
974 if (brw->gen < 6)
975 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
976 brw_set_dp_write_message(p, send,
977 255, /* binding table index: stateless access */
978 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
979 msg_type,
980 3, /* mlen */
981 true, /* header present */
982 false, /* not a render target write */
983 write_commit, /* rlen */
984 false, /* eot */
985 write_commit);
986 }
987
988 void
989 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
990 struct brw_reg dst,
991 struct brw_reg index,
992 struct brw_reg offset)
993 {
994 assert(index.file == BRW_IMMEDIATE_VALUE &&
995 index.type == BRW_REGISTER_TYPE_UD);
996 uint32_t surf_index = index.dw1.ud;
997
998 struct brw_reg header = brw_vec8_grf(0, 0);
999
1000 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1001
1002 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
1003 offset);
1004
1005 uint32_t msg_type;
1006
1007 if (brw->gen >= 6)
1008 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1009 else if (brw->gen == 5 || brw->is_g4x)
1010 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1011 else
1012 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1013
1014 /* Each of the 8 channel enables is considered for whether each
1015 * dword is written.
1016 */
1017 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1018 brw_set_dest(p, send, dst);
1019 brw_set_src0(p, send, header);
1020 if (brw->gen < 6)
1021 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
1022 brw_set_dp_read_message(p, send,
1023 surf_index,
1024 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1025 msg_type,
1026 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1027 2, /* mlen */
1028 true, /* header_present */
1029 1 /* rlen */);
1030
1031 brw_mark_surface_used(&prog_data->base, surf_index);
1032 }
1033
1034 void
1035 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1036 struct brw_reg dst,
1037 struct brw_reg surf_index,
1038 struct brw_reg offset)
1039 {
1040 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1041
1042 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1043
1044 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1045 brw_set_dest(p, insn, dst);
1046 brw_set_src0(p, insn, offset);
1047 brw_set_sampler_message(p, insn,
1048 surf_index.dw1.ud,
1049 0, /* LD message ignores sampler unit */
1050 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1051 1, /* rlen */
1052 inst->mlen,
1053 inst->header_present,
1054 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1055 0);
1056
1057 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1058
1059 } else {
1060
1061 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1062
1063 brw_push_insn_state(p);
1064 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1065 brw_set_default_access_mode(p, BRW_ALIGN_1);
1066
1067 /* a0.0 = surf_index & 0xff */
1068 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1069 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1070 brw_set_dest(p, insn_and, addr);
1071 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1072 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1073
1074 brw_pop_insn_state(p);
1075
1076 /* dst = send(offset, a0.0 | <descriptor>) */
1077 brw_inst *insn = brw_send_indirect_message(
1078 p, BRW_SFID_SAMPLER, dst, offset, addr);
1079 brw_set_sampler_message(p, insn,
1080 0 /* surface */,
1081 0 /* sampler */,
1082 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1083 1 /* rlen */,
1084 inst->mlen,
1085 inst->header_present,
1086 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1087 0);
1088
1089 /* visitor knows more than we do about the surface limit required,
1090 * so has already done marking.
1091 */
1092 }
1093 }
1094
1095 void
1096 vec4_generator::generate_set_simd4x2_header_gen9(vec4_instruction *inst,
1097 struct brw_reg dst)
1098 {
1099 brw_push_insn_state(p);
1100 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1101
1102 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1103
1104 brw_set_default_access_mode(p, BRW_ALIGN_1);
1105 brw_MOV(p, get_element_ud(dst, 2),
1106 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1107
1108 brw_pop_insn_state(p);
1109 }
1110
1111 void
1112 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1113 struct brw_reg dst,
1114 struct brw_reg atomic_op,
1115 struct brw_reg surf_index)
1116 {
1117 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1118 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1119 surf_index.file == BRW_IMMEDIATE_VALUE &&
1120 surf_index.type == BRW_REGISTER_TYPE_UD);
1121
1122 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1123 atomic_op.dw1.ud, surf_index.dw1.ud,
1124 inst->mlen, true);
1125
1126 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1127 }
1128
1129 void
1130 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1131 struct brw_reg dst,
1132 struct brw_reg surf_index)
1133 {
1134 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1135 surf_index.type == BRW_REGISTER_TYPE_UD);
1136
1137 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1138 surf_index.dw1.ud, inst->mlen, 1);
1139
1140 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1141 }
1142
1143 void
1144 vec4_generator::generate_code(const cfg_t *cfg)
1145 {
1146 struct annotation_info annotation;
1147 memset(&annotation, 0, sizeof(annotation));
1148 int loop_count = 0;
1149
1150 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1151 struct brw_reg src[3], dst;
1152
1153 if (unlikely(debug_flag))
1154 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1155
1156 for (unsigned int i = 0; i < 3; i++) {
1157 src[i] = inst->get_src(this->prog_data, i);
1158 }
1159 dst = inst->get_dst();
1160
1161 brw_set_default_predicate_control(p, inst->predicate);
1162 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1163 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1164 brw_set_default_saturate(p, inst->saturate);
1165 brw_set_default_mask_control(p, inst->force_writemask_all);
1166 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1167
1168 unsigned pre_emit_nr_insn = p->nr_insn;
1169
1170 if (dst.width == BRW_WIDTH_4) {
1171 /* This happens in attribute fixups for "dual instanced" geometry
1172 * shaders, since they use attributes that are vec4's. Since the exec
1173 * width is only 4, it's essential that the caller set
1174 * force_writemask_all in order to make sure the instruction is executed
1175 * regardless of which channels are enabled.
1176 */
1177 assert(inst->force_writemask_all);
1178
1179 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1180 * the following register region restrictions (from Graphics BSpec:
1181 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1182 * > Register Region Restrictions)
1183 *
1184 * 1. ExecSize must be greater than or equal to Width.
1185 *
1186 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1187 * to Width * HorzStride."
1188 */
1189 for (int i = 0; i < 3; i++) {
1190 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1191 src[i] = stride(src[i], 4, 4, 1);
1192 }
1193 }
1194
1195 switch (inst->opcode) {
1196 case VEC4_OPCODE_UNPACK_UNIFORM:
1197 case BRW_OPCODE_MOV:
1198 brw_MOV(p, dst, src[0]);
1199 break;
1200 case BRW_OPCODE_ADD:
1201 brw_ADD(p, dst, src[0], src[1]);
1202 break;
1203 case BRW_OPCODE_MUL:
1204 brw_MUL(p, dst, src[0], src[1]);
1205 break;
1206 case BRW_OPCODE_MACH:
1207 brw_MACH(p, dst, src[0], src[1]);
1208 break;
1209
1210 case BRW_OPCODE_MAD:
1211 assert(brw->gen >= 6);
1212 brw_MAD(p, dst, src[0], src[1], src[2]);
1213 break;
1214
1215 case BRW_OPCODE_FRC:
1216 brw_FRC(p, dst, src[0]);
1217 break;
1218 case BRW_OPCODE_RNDD:
1219 brw_RNDD(p, dst, src[0]);
1220 break;
1221 case BRW_OPCODE_RNDE:
1222 brw_RNDE(p, dst, src[0]);
1223 break;
1224 case BRW_OPCODE_RNDZ:
1225 brw_RNDZ(p, dst, src[0]);
1226 break;
1227
1228 case BRW_OPCODE_AND:
1229 brw_AND(p, dst, src[0], src[1]);
1230 break;
1231 case BRW_OPCODE_OR:
1232 brw_OR(p, dst, src[0], src[1]);
1233 break;
1234 case BRW_OPCODE_XOR:
1235 brw_XOR(p, dst, src[0], src[1]);
1236 break;
1237 case BRW_OPCODE_NOT:
1238 brw_NOT(p, dst, src[0]);
1239 break;
1240 case BRW_OPCODE_ASR:
1241 brw_ASR(p, dst, src[0], src[1]);
1242 break;
1243 case BRW_OPCODE_SHR:
1244 brw_SHR(p, dst, src[0], src[1]);
1245 break;
1246 case BRW_OPCODE_SHL:
1247 brw_SHL(p, dst, src[0], src[1]);
1248 break;
1249
1250 case BRW_OPCODE_CMP:
1251 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1252 break;
1253 case BRW_OPCODE_SEL:
1254 brw_SEL(p, dst, src[0], src[1]);
1255 break;
1256
1257 case BRW_OPCODE_DPH:
1258 brw_DPH(p, dst, src[0], src[1]);
1259 break;
1260
1261 case BRW_OPCODE_DP4:
1262 brw_DP4(p, dst, src[0], src[1]);
1263 break;
1264
1265 case BRW_OPCODE_DP3:
1266 brw_DP3(p, dst, src[0], src[1]);
1267 break;
1268
1269 case BRW_OPCODE_DP2:
1270 brw_DP2(p, dst, src[0], src[1]);
1271 break;
1272
1273 case BRW_OPCODE_F32TO16:
1274 assert(brw->gen >= 7);
1275 brw_F32TO16(p, dst, src[0]);
1276 break;
1277
1278 case BRW_OPCODE_F16TO32:
1279 assert(brw->gen >= 7);
1280 brw_F16TO32(p, dst, src[0]);
1281 break;
1282
1283 case BRW_OPCODE_LRP:
1284 assert(brw->gen >= 6);
1285 brw_LRP(p, dst, src[0], src[1], src[2]);
1286 break;
1287
1288 case BRW_OPCODE_BFREV:
1289 assert(brw->gen >= 7);
1290 /* BFREV only supports UD type for src and dst. */
1291 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1292 retype(src[0], BRW_REGISTER_TYPE_UD));
1293 break;
1294 case BRW_OPCODE_FBH:
1295 assert(brw->gen >= 7);
1296 /* FBH only supports UD type for dst. */
1297 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1298 break;
1299 case BRW_OPCODE_FBL:
1300 assert(brw->gen >= 7);
1301 /* FBL only supports UD type for dst. */
1302 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1303 break;
1304 case BRW_OPCODE_CBIT:
1305 assert(brw->gen >= 7);
1306 /* CBIT only supports UD type for dst. */
1307 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1308 break;
1309 case BRW_OPCODE_ADDC:
1310 assert(brw->gen >= 7);
1311 brw_ADDC(p, dst, src[0], src[1]);
1312 break;
1313 case BRW_OPCODE_SUBB:
1314 assert(brw->gen >= 7);
1315 brw_SUBB(p, dst, src[0], src[1]);
1316 break;
1317 case BRW_OPCODE_MAC:
1318 brw_MAC(p, dst, src[0], src[1]);
1319 break;
1320
1321 case BRW_OPCODE_BFE:
1322 assert(brw->gen >= 7);
1323 brw_BFE(p, dst, src[0], src[1], src[2]);
1324 break;
1325
1326 case BRW_OPCODE_BFI1:
1327 assert(brw->gen >= 7);
1328 brw_BFI1(p, dst, src[0], src[1]);
1329 break;
1330 case BRW_OPCODE_BFI2:
1331 assert(brw->gen >= 7);
1332 brw_BFI2(p, dst, src[0], src[1], src[2]);
1333 break;
1334
1335 case BRW_OPCODE_IF:
1336 if (inst->src[0].file != BAD_FILE) {
1337 /* The instruction has an embedded compare (only allowed on gen6) */
1338 assert(brw->gen == 6);
1339 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1340 } else {
1341 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1342 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1343 }
1344 break;
1345
1346 case BRW_OPCODE_ELSE:
1347 brw_ELSE(p);
1348 break;
1349 case BRW_OPCODE_ENDIF:
1350 brw_ENDIF(p);
1351 break;
1352
1353 case BRW_OPCODE_DO:
1354 brw_DO(p, BRW_EXECUTE_8);
1355 break;
1356
1357 case BRW_OPCODE_BREAK:
1358 brw_BREAK(p);
1359 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1360 break;
1361 case BRW_OPCODE_CONTINUE:
1362 brw_CONT(p);
1363 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1364 break;
1365
1366 case BRW_OPCODE_WHILE:
1367 brw_WHILE(p);
1368 loop_count++;
1369 break;
1370
1371 case SHADER_OPCODE_RCP:
1372 case SHADER_OPCODE_RSQ:
1373 case SHADER_OPCODE_SQRT:
1374 case SHADER_OPCODE_EXP2:
1375 case SHADER_OPCODE_LOG2:
1376 case SHADER_OPCODE_SIN:
1377 case SHADER_OPCODE_COS:
1378 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1379 if (brw->gen >= 7) {
1380 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1381 brw_null_reg());
1382 } else if (brw->gen == 6) {
1383 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1384 } else {
1385 generate_math1_gen4(inst, dst, src[0]);
1386 }
1387 break;
1388
1389 case SHADER_OPCODE_POW:
1390 case SHADER_OPCODE_INT_QUOTIENT:
1391 case SHADER_OPCODE_INT_REMAINDER:
1392 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1393 if (brw->gen >= 7) {
1394 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1395 } else if (brw->gen == 6) {
1396 generate_math_gen6(inst, dst, src[0], src[1]);
1397 } else {
1398 generate_math2_gen4(inst, dst, src[0], src[1]);
1399 }
1400 break;
1401
1402 case SHADER_OPCODE_TEX:
1403 case SHADER_OPCODE_TXD:
1404 case SHADER_OPCODE_TXF:
1405 case SHADER_OPCODE_TXF_CMS:
1406 case SHADER_OPCODE_TXF_MCS:
1407 case SHADER_OPCODE_TXL:
1408 case SHADER_OPCODE_TXS:
1409 case SHADER_OPCODE_TG4:
1410 case SHADER_OPCODE_TG4_OFFSET:
1411 generate_tex(inst, dst, src[0], src[1]);
1412 break;
1413
1414 case VS_OPCODE_URB_WRITE:
1415 generate_vs_urb_write(inst);
1416 break;
1417
1418 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1419 generate_scratch_read(inst, dst, src[0]);
1420 break;
1421
1422 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1423 generate_scratch_write(inst, dst, src[0], src[1]);
1424 break;
1425
1426 case VS_OPCODE_PULL_CONSTANT_LOAD:
1427 generate_pull_constant_load(inst, dst, src[0], src[1]);
1428 break;
1429
1430 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1431 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1432 break;
1433
1434 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1435 generate_set_simd4x2_header_gen9(inst, dst);
1436 break;
1437
1438 case GS_OPCODE_URB_WRITE:
1439 generate_gs_urb_write(inst);
1440 break;
1441
1442 case GS_OPCODE_URB_WRITE_ALLOCATE:
1443 generate_gs_urb_write_allocate(inst);
1444 break;
1445
1446 case GS_OPCODE_SVB_WRITE:
1447 generate_gs_svb_write(inst, dst, src[0], src[1]);
1448 break;
1449
1450 case GS_OPCODE_SVB_SET_DST_INDEX:
1451 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1452 break;
1453
1454 case GS_OPCODE_THREAD_END:
1455 generate_gs_thread_end(inst);
1456 break;
1457
1458 case GS_OPCODE_SET_WRITE_OFFSET:
1459 generate_gs_set_write_offset(dst, src[0], src[1]);
1460 break;
1461
1462 case GS_OPCODE_SET_VERTEX_COUNT:
1463 generate_gs_set_vertex_count(dst, src[0]);
1464 break;
1465
1466 case GS_OPCODE_FF_SYNC:
1467 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1468 break;
1469
1470 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1471 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1472 break;
1473
1474 case GS_OPCODE_SET_PRIMITIVE_ID:
1475 generate_gs_set_primitive_id(dst);
1476 break;
1477
1478 case GS_OPCODE_SET_DWORD_2:
1479 generate_gs_set_dword_2(dst, src[0]);
1480 break;
1481
1482 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1483 generate_gs_prepare_channel_masks(dst);
1484 break;
1485
1486 case GS_OPCODE_SET_CHANNEL_MASKS:
1487 generate_gs_set_channel_masks(dst, src[0]);
1488 break;
1489
1490 case GS_OPCODE_GET_INSTANCE_ID:
1491 generate_gs_get_instance_id(dst);
1492 break;
1493
1494 case SHADER_OPCODE_SHADER_TIME_ADD:
1495 brw_shader_time_add(p, src[0],
1496 prog_data->base.binding_table.shader_time_start);
1497 brw_mark_surface_used(&prog_data->base,
1498 prog_data->base.binding_table.shader_time_start);
1499 break;
1500
1501 case SHADER_OPCODE_UNTYPED_ATOMIC:
1502 generate_untyped_atomic(inst, dst, src[0], src[1]);
1503 break;
1504
1505 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1506 generate_untyped_surface_read(inst, dst, src[0]);
1507 break;
1508
1509 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1510 generate_unpack_flags(dst);
1511 break;
1512
1513 case VEC4_OPCODE_MOV_BYTES: {
1514 /* Moves the low byte from each channel, using an Align1 access mode
1515 * and a <4,1,0> source region.
1516 */
1517 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1518 src[0].type == BRW_REGISTER_TYPE_B);
1519
1520 brw_set_default_access_mode(p, BRW_ALIGN_1);
1521 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1522 src[0].width = BRW_WIDTH_1;
1523 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1524 brw_MOV(p, dst, src[0]);
1525 brw_set_default_access_mode(p, BRW_ALIGN_16);
1526 break;
1527 }
1528
1529 case VEC4_OPCODE_PACK_BYTES: {
1530 /* Is effectively:
1531 *
1532 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1533 *
1534 * but destinations' only regioning is horizontal stride, so instead we
1535 * have to use two instructions:
1536 *
1537 * mov(4) dst<1>:UB src<4,1,0>:UB
1538 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1539 *
1540 * where they pack the four bytes from the low and high four DW.
1541 */
1542 assert(is_power_of_two(dst.dw1.bits.writemask) &&
1543 dst.dw1.bits.writemask != 0);
1544 unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
1545
1546 dst.type = BRW_REGISTER_TYPE_UB;
1547
1548 brw_set_default_access_mode(p, BRW_ALIGN_1);
1549
1550 src[0].type = BRW_REGISTER_TYPE_UB;
1551 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1552 src[0].width = BRW_WIDTH_1;
1553 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1554 dst.subnr = offset * 4;
1555 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1556 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1557 brw_inst_set_no_dd_clear(brw, insn, true);
1558 brw_inst_set_no_dd_check(brw, insn, inst->no_dd_check);
1559
1560 src[0].subnr = 16;
1561 dst.subnr = 16 + offset * 4;
1562 insn = brw_MOV(p, dst, src[0]);
1563 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1564 brw_inst_set_no_dd_clear(brw, insn, inst->no_dd_clear);
1565 brw_inst_set_no_dd_check(brw, insn, true);
1566
1567 brw_set_default_access_mode(p, BRW_ALIGN_16);
1568 break;
1569 }
1570
1571 default:
1572 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1573 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1574 opcode_descs[inst->opcode].name);
1575 } else {
1576 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1577 }
1578 abort();
1579 }
1580
1581 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1582 /* Handled dependency hints in the generator. */
1583
1584 assert(!inst->conditional_mod);
1585 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1586 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1587 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1588 "emitting more than 1 instruction");
1589
1590 brw_inst *last = &p->store[pre_emit_nr_insn];
1591
1592 if (inst->conditional_mod)
1593 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1594 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1595 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1596 }
1597 }
1598
1599 brw_set_uip_jip(p);
1600 annotation_finalize(&annotation, p->next_insn_offset);
1601
1602 int before_size = p->next_insn_offset;
1603 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1604 int after_size = p->next_insn_offset;
1605
1606 if (unlikely(debug_flag)) {
1607 if (shader_prog) {
1608 fprintf(stderr, "Native code for %s %s shader %d:\n",
1609 shader_prog->Label ? shader_prog->Label : "unnamed",
1610 stage_name, shader_prog->Name);
1611 } else {
1612 fprintf(stderr, "Native code for %s program %d:\n", stage_name,
1613 prog->Id);
1614 }
1615 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1616 " bytes (%.0f%%)\n",
1617 stage_abbrev,
1618 before_size / 16, loop_count, before_size, after_size,
1619 100.0f * (before_size - after_size) / before_size);
1620
1621 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1622 ralloc_free(annotation.ann);
1623 }
1624
1625 static GLuint msg_id = 0;
1626 _mesa_gl_debug(&brw->ctx, &msg_id,
1627 MESA_DEBUG_SOURCE_SHADER_COMPILER,
1628 MESA_DEBUG_TYPE_OTHER,
1629 MESA_DEBUG_SEVERITY_NOTIFICATION,
1630 "%s vec4 shader: %d inst, %d loops, "
1631 "compacted %d to %d bytes.\n",
1632 stage_abbrev,
1633 before_size / 16, loop_count,
1634 before_size, after_size);
1635 }
1636
1637 const unsigned *
1638 vec4_generator::generate_assembly(const cfg_t *cfg,
1639 unsigned *assembly_size)
1640 {
1641 brw_set_default_access_mode(p, BRW_ALIGN_16);
1642 generate_code(cfg);
1643
1644 return brw_get_program(p, assembly_size);
1645 }
1646
1647 } /* namespace brw */