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[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
104 (src[i].reg + src[i].reg_offset) / 2,
105 ((src[i].reg + src[i].reg_offset) % 2) * 4),
106 0, 4, 1);
107 brw_reg = retype(brw_reg, src[i].type);
108 brw_reg.dw1.bits.swizzle = src[i].swizzle;
109 if (src[i].abs)
110 brw_reg = brw_abs(brw_reg);
111 if (src[i].negate)
112 brw_reg = negate(brw_reg);
113
114 /* This should have been moved to pull constants. */
115 assert(!src[i].reladdr);
116 break;
117
118 case HW_REG:
119 brw_reg = src[i].fixed_hw_reg;
120 break;
121
122 case BAD_FILE:
123 /* Probably unused. */
124 brw_reg = brw_null_reg();
125 break;
126 case ATTR:
127 default:
128 assert(!"not reached");
129 brw_reg = brw_null_reg();
130 break;
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
146
147 p = rzalloc(mem_ctx, struct brw_compile);
148 brw_init_compile(brw, p, mem_ctx);
149 }
150
151 vec4_generator::~vec4_generator()
152 {
153 }
154
155 void
156 vec4_generator::mark_surface_used(unsigned surf_index)
157 {
158 assert(surf_index < BRW_MAX_SURFACES);
159
160 prog_data->base.binding_table.size_bytes =
161 MAX2(prog_data->base.binding_table.size_bytes, (surf_index + 1) * 4);
162 }
163
164 void
165 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
166 struct brw_reg dst,
167 struct brw_reg src)
168 {
169 brw_math(p,
170 dst,
171 brw_math_function(inst->opcode),
172 inst->base_mrf,
173 src,
174 BRW_MATH_DATA_VECTOR,
175 BRW_MATH_PRECISION_FULL);
176 }
177
178 static void
179 check_gen6_math_src_arg(struct brw_reg src)
180 {
181 /* Source swizzles are ignored. */
182 assert(!src.abs);
183 assert(!src.negate);
184 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
185 }
186
187 void
188 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
189 struct brw_reg dst,
190 struct brw_reg src)
191 {
192 /* Can't do writemask because math can't be align16. */
193 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
194 check_gen6_math_src_arg(src);
195
196 brw_set_access_mode(p, BRW_ALIGN_1);
197 brw_math(p,
198 dst,
199 brw_math_function(inst->opcode),
200 inst->base_mrf,
201 src,
202 BRW_MATH_DATA_SCALAR,
203 BRW_MATH_PRECISION_FULL);
204 brw_set_access_mode(p, BRW_ALIGN_16);
205 }
206
207 void
208 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
209 struct brw_reg dst,
210 struct brw_reg src0,
211 struct brw_reg src1)
212 {
213 brw_math2(p,
214 dst,
215 brw_math_function(inst->opcode),
216 src0, src1);
217 }
218
219 void
220 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
221 struct brw_reg dst,
222 struct brw_reg src0,
223 struct brw_reg src1)
224 {
225 /* Can't do writemask because math can't be align16. */
226 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0);
229 check_gen6_math_src_arg(src1);
230
231 brw_set_access_mode(p, BRW_ALIGN_1);
232 brw_math2(p,
233 dst,
234 brw_math_function(inst->opcode),
235 src0, src1);
236 brw_set_access_mode(p, BRW_ALIGN_16);
237 }
238
239 void
240 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
241 struct brw_reg dst,
242 struct brw_reg src0,
243 struct brw_reg src1)
244 {
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
246 * "Message Payload":
247 *
248 * "Operand0[7]. For the INT DIV functions, this operand is the
249 * denominator."
250 * ...
251 * "Operand1[7]. For the INT DIV functions, this operand is the
252 * numerator."
253 */
254 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
255 struct brw_reg &op0 = is_int_div ? src1 : src0;
256 struct brw_reg &op1 = is_int_div ? src0 : src1;
257
258 brw_push_insn_state(p);
259 brw_set_saturate(p, false);
260 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
262 brw_pop_insn_state(p);
263
264 brw_math(p,
265 dst,
266 brw_math_function(inst->opcode),
267 inst->base_mrf,
268 op0,
269 BRW_MATH_DATA_VECTOR,
270 BRW_MATH_PRECISION_FULL);
271 }
272
273 void
274 vec4_generator::generate_tex(vec4_instruction *inst,
275 struct brw_reg dst,
276 struct brw_reg src)
277 {
278 int msg_type = -1;
279
280 if (brw->gen >= 5) {
281 switch (inst->opcode) {
282 case SHADER_OPCODE_TEX:
283 case SHADER_OPCODE_TXL:
284 if (inst->shadow_compare) {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
286 } else {
287 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
288 }
289 break;
290 case SHADER_OPCODE_TXD:
291 if (inst->shadow_compare) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw->is_haswell);
294 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
295 } else {
296 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
297 }
298 break;
299 case SHADER_OPCODE_TXF:
300 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
301 break;
302 case SHADER_OPCODE_TXF_MS:
303 if (brw->gen >= 7)
304 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
305 else
306 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
307 break;
308 case SHADER_OPCODE_TXS:
309 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
310 break;
311 case SHADER_OPCODE_TG4:
312 if (inst->shadow_compare) {
313 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
314 } else {
315 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
316 }
317 break;
318 case SHADER_OPCODE_TG4_OFFSET:
319 if (inst->shadow_compare) {
320 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
321 } else {
322 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
323 }
324 break;
325 default:
326 assert(!"should not get here: invalid VS texture opcode");
327 break;
328 }
329 } else {
330 switch (inst->opcode) {
331 case SHADER_OPCODE_TEX:
332 case SHADER_OPCODE_TXL:
333 if (inst->shadow_compare) {
334 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
335 assert(inst->mlen == 3);
336 } else {
337 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
338 assert(inst->mlen == 2);
339 }
340 break;
341 case SHADER_OPCODE_TXD:
342 /* There is no sample_d_c message; comparisons are done manually. */
343 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
344 assert(inst->mlen == 4);
345 break;
346 case SHADER_OPCODE_TXF:
347 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
348 assert(inst->mlen == 2);
349 break;
350 case SHADER_OPCODE_TXS:
351 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
352 assert(inst->mlen == 2);
353 break;
354 default:
355 assert(!"should not get here: invalid VS texture opcode");
356 break;
357 }
358 }
359
360 assert(msg_type != -1);
361
362 /* Load the message header if present. If there's a texture offset, we need
363 * to set it up explicitly and load the offset bitfield. Otherwise, we can
364 * use an implied move from g0 to the first message register.
365 */
366 if (inst->texture_offset) {
367 /* Explicitly set up the message header by copying g0 to the MRF. */
368 brw_push_insn_state(p);
369 brw_set_mask_control(p, BRW_MASK_DISABLE);
370 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
371 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
372
373 /* Then set the offset bits in DWord 2. */
374 brw_set_access_mode(p, BRW_ALIGN_1);
375 brw_MOV(p,
376 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
377 BRW_REGISTER_TYPE_UD),
378 brw_imm_ud(inst->texture_offset));
379 brw_pop_insn_state(p);
380 } else if (inst->header_present) {
381 /* Set up an implied move from g0 to the MRF. */
382 src = brw_vec8_grf(0, 0);
383 }
384
385 uint32_t return_format;
386
387 switch (dst.type) {
388 case BRW_REGISTER_TYPE_D:
389 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
390 break;
391 case BRW_REGISTER_TYPE_UD:
392 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
393 break;
394 default:
395 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
396 break;
397 }
398
399 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
400 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
401 ? prog_data->base.binding_table.gather_texture_start
402 : prog_data->base.binding_table.texture_start) + inst->sampler;
403
404 brw_SAMPLE(p,
405 dst,
406 inst->base_mrf,
407 src,
408 surface_index,
409 inst->sampler,
410 msg_type,
411 1, /* response length */
412 inst->mlen,
413 inst->header_present,
414 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
415 return_format);
416
417 mark_surface_used(surface_index);
418 }
419
420 void
421 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
422 {
423 brw_urb_WRITE(p,
424 brw_null_reg(), /* dest */
425 inst->base_mrf, /* starting mrf reg nr */
426 brw_vec8_grf(0, 0), /* src */
427 inst->urb_write_flags,
428 inst->mlen,
429 0, /* response len */
430 inst->offset, /* urb destination offset */
431 BRW_URB_SWIZZLE_INTERLEAVE);
432 }
433
434 void
435 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
436 {
437 struct brw_reg src = brw_message_reg(inst->base_mrf);
438 brw_urb_WRITE(p,
439 brw_null_reg(), /* dest */
440 inst->base_mrf, /* starting mrf reg nr */
441 src,
442 inst->urb_write_flags,
443 inst->mlen,
444 0, /* response len */
445 inst->offset, /* urb destination offset */
446 BRW_URB_SWIZZLE_INTERLEAVE);
447 }
448
449 void
450 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
451 {
452 struct brw_reg src = brw_message_reg(inst->base_mrf);
453 brw_urb_WRITE(p,
454 brw_null_reg(), /* dest */
455 inst->base_mrf, /* starting mrf reg nr */
456 src,
457 BRW_URB_WRITE_EOT,
458 1, /* message len */
459 0, /* response len */
460 0, /* urb destination offset */
461 BRW_URB_SWIZZLE_INTERLEAVE);
462 }
463
464 void
465 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
466 struct brw_reg src0,
467 struct brw_reg src1)
468 {
469 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
470 * Header: M0.3):
471 *
472 * Slot 0 Offset. This field, after adding to the Global Offset field
473 * in the message descriptor, specifies the offset (in 256-bit units)
474 * from the start of the URB entry, as referenced by URB Handle 0, at
475 * which the data will be accessed.
476 *
477 * Similar text describes DWORD M0.4, which is slot 1 offset.
478 *
479 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
480 * of the register for geometry shader invocations 0 and 1) by the
481 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
482 *
483 * We can do this with the following EU instruction:
484 *
485 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
486 */
487 brw_push_insn_state(p);
488 brw_set_access_mode(p, BRW_ALIGN_1);
489 brw_set_mask_control(p, BRW_MASK_DISABLE);
490 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
491 src1);
492 brw_set_access_mode(p, BRW_ALIGN_16);
493 brw_pop_insn_state(p);
494 }
495
496 void
497 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
498 struct brw_reg src)
499 {
500 brw_push_insn_state(p);
501 brw_set_access_mode(p, BRW_ALIGN_1);
502 brw_set_mask_control(p, BRW_MASK_DISABLE);
503
504 /* If we think of the src and dst registers as composed of 8 DWORDs each,
505 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
506 * them to WORDs, and then pack them into DWORD 2 of dst.
507 *
508 * It's easier to get the EU to do this if we think of the src and dst
509 * registers as composed of 16 WORDS each; then, we want to pick up the
510 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
511 * dst.
512 *
513 * We can do that by the following EU instruction:
514 *
515 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
516 */
517 brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
518 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
519 brw_set_access_mode(p, BRW_ALIGN_16);
520 brw_pop_insn_state(p);
521 }
522
523 void
524 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
525 struct brw_reg src)
526 {
527 assert(src.file == BRW_IMMEDIATE_VALUE);
528
529 brw_push_insn_state(p);
530 brw_set_access_mode(p, BRW_ALIGN_1);
531 brw_set_mask_control(p, BRW_MASK_DISABLE);
532 brw_MOV(p, suboffset(vec1(dst), 2), src);
533 brw_set_access_mode(p, BRW_ALIGN_16);
534 brw_pop_insn_state(p);
535 }
536
537 void
538 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
539 {
540 /* We want to left shift just DWORD 4 (the x component belonging to the
541 * second geometry shader invocation) by 4 bits. So generate the
542 * instruction:
543 *
544 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
545 */
546 dst = suboffset(vec1(dst), 4);
547 brw_push_insn_state(p);
548 brw_set_access_mode(p, BRW_ALIGN_1);
549 brw_set_mask_control(p, BRW_MASK_DISABLE);
550 brw_SHL(p, dst, dst, brw_imm_ud(4));
551 brw_pop_insn_state(p);
552 }
553
554 void
555 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
556 struct brw_reg src)
557 {
558 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
559 * Header: M0.5):
560 *
561 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
562 *
563 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
564 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
565 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
566 * channel enable to determine the final channel enable. For the
567 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
568 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
569 * in the writeback message. For the URB_WRITE_OWORD &
570 * URB_WRITE_HWORD messages, when final channel enable is 1 it
571 * indicates that Vertex 1 DATA [3] will be written to the surface.
572 *
573 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
574 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
575 *
576 * 14 Vertex 1 DATA [2] Channel Mask
577 * 13 Vertex 1 DATA [1] Channel Mask
578 * 12 Vertex 1 DATA [0] Channel Mask
579 * 11 Vertex 0 DATA [3] Channel Mask
580 * 10 Vertex 0 DATA [2] Channel Mask
581 * 9 Vertex 0 DATA [1] Channel Mask
582 * 8 Vertex 0 DATA [0] Channel Mask
583 *
584 * (This is from a section of the PRM that is agnostic to the particular
585 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
586 * geometry shader invocations 0 and 1, respectively). Since we have the
587 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
588 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
589 * DWORD 4, we just need to OR them together and store the result in bits
590 * 15:8 of DWORD 5.
591 *
592 * It's easier to get the EU to do this if we think of the src and dst
593 * registers as composed of 32 bytes each; then, we want to pick up the
594 * contents of bytes 0 and 16 from src, OR them together, and store them in
595 * byte 21.
596 *
597 * We can do that by the following EU instruction:
598 *
599 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
600 *
601 * Note: this relies on the source register having zeros in (a) bits 7:4 of
602 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
603 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
604 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
605 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
606 * contain valid channel mask values (which are in the range 0x0-0xf).
607 */
608 dst = retype(dst, BRW_REGISTER_TYPE_UB);
609 src = retype(src, BRW_REGISTER_TYPE_UB);
610 brw_push_insn_state(p);
611 brw_set_access_mode(p, BRW_ALIGN_1);
612 brw_set_mask_control(p, BRW_MASK_DISABLE);
613 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
614 brw_pop_insn_state(p);
615 }
616
617 void
618 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
619 struct brw_reg index)
620 {
621 int second_vertex_offset;
622
623 if (brw->gen >= 6)
624 second_vertex_offset = 1;
625 else
626 second_vertex_offset = 16;
627
628 m1 = retype(m1, BRW_REGISTER_TYPE_D);
629
630 /* Set up M1 (message payload). Only the block offsets in M1.0 and
631 * M1.4 are used, and the rest are ignored.
632 */
633 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
634 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
635 struct brw_reg index_0 = suboffset(vec1(index), 0);
636 struct brw_reg index_4 = suboffset(vec1(index), 4);
637
638 brw_push_insn_state(p);
639 brw_set_mask_control(p, BRW_MASK_DISABLE);
640 brw_set_access_mode(p, BRW_ALIGN_1);
641
642 brw_MOV(p, m1_0, index_0);
643
644 if (index.file == BRW_IMMEDIATE_VALUE) {
645 index_4.dw1.ud += second_vertex_offset;
646 brw_MOV(p, m1_4, index_4);
647 } else {
648 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
649 }
650
651 brw_pop_insn_state(p);
652 }
653
654 void
655 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
656 struct brw_reg dst)
657 {
658 brw_push_insn_state(p);
659 brw_set_mask_control(p, BRW_MASK_DISABLE);
660 brw_set_access_mode(p, BRW_ALIGN_1);
661
662 struct brw_reg flags = brw_flag_reg(0, 0);
663 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
664 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
665
666 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
667 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
668 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
669
670 brw_pop_insn_state(p);
671 }
672
673 void
674 vec4_generator::generate_scratch_read(vec4_instruction *inst,
675 struct brw_reg dst,
676 struct brw_reg index)
677 {
678 struct brw_reg header = brw_vec8_grf(0, 0);
679
680 gen6_resolve_implied_move(p, &header, inst->base_mrf);
681
682 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
683 index);
684
685 uint32_t msg_type;
686
687 if (brw->gen >= 6)
688 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
689 else if (brw->gen == 5 || brw->is_g4x)
690 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
691 else
692 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
693
694 /* Each of the 8 channel enables is considered for whether each
695 * dword is written.
696 */
697 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
698 brw_set_dest(p, send, dst);
699 brw_set_src0(p, send, header);
700 if (brw->gen < 6)
701 send->header.destreg__conditionalmod = inst->base_mrf;
702 brw_set_dp_read_message(p, send,
703 255, /* binding table index: stateless access */
704 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
705 msg_type,
706 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
707 2, /* mlen */
708 true, /* header_present */
709 1 /* rlen */);
710 }
711
712 void
713 vec4_generator::generate_scratch_write(vec4_instruction *inst,
714 struct brw_reg dst,
715 struct brw_reg src,
716 struct brw_reg index)
717 {
718 struct brw_reg header = brw_vec8_grf(0, 0);
719 bool write_commit;
720
721 /* If the instruction is predicated, we'll predicate the send, not
722 * the header setup.
723 */
724 brw_set_predicate_control(p, false);
725
726 gen6_resolve_implied_move(p, &header, inst->base_mrf);
727
728 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
729 index);
730
731 brw_MOV(p,
732 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
733 retype(src, BRW_REGISTER_TYPE_D));
734
735 uint32_t msg_type;
736
737 if (brw->gen >= 7)
738 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
739 else if (brw->gen == 6)
740 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
741 else
742 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
743
744 brw_set_predicate_control(p, inst->predicate);
745
746 /* Pre-gen6, we have to specify write commits to ensure ordering
747 * between reads and writes within a thread. Afterwards, that's
748 * guaranteed and write commits only matter for inter-thread
749 * synchronization.
750 */
751 if (brw->gen >= 6) {
752 write_commit = false;
753 } else {
754 /* The visitor set up our destination register to be g0. This
755 * means that when the next read comes along, we will end up
756 * reading from g0 and causing a block on the write commit. For
757 * write-after-read, we are relying on the value of the previous
758 * read being used (and thus blocking on completion) before our
759 * write is executed. This means we have to be careful in
760 * instruction scheduling to not violate this assumption.
761 */
762 write_commit = true;
763 }
764
765 /* Each of the 8 channel enables is considered for whether each
766 * dword is written.
767 */
768 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
769 brw_set_dest(p, send, dst);
770 brw_set_src0(p, send, header);
771 if (brw->gen < 6)
772 send->header.destreg__conditionalmod = inst->base_mrf;
773 brw_set_dp_write_message(p, send,
774 255, /* binding table index: stateless access */
775 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
776 msg_type,
777 3, /* mlen */
778 true, /* header present */
779 false, /* not a render target write */
780 write_commit, /* rlen */
781 false, /* eot */
782 write_commit);
783 }
784
785 void
786 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
787 struct brw_reg dst,
788 struct brw_reg index,
789 struct brw_reg offset)
790 {
791 assert(brw->gen <= 7);
792 assert(index.file == BRW_IMMEDIATE_VALUE &&
793 index.type == BRW_REGISTER_TYPE_UD);
794 uint32_t surf_index = index.dw1.ud;
795
796 struct brw_reg header = brw_vec8_grf(0, 0);
797
798 gen6_resolve_implied_move(p, &header, inst->base_mrf);
799
800 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
801 offset);
802
803 uint32_t msg_type;
804
805 if (brw->gen >= 6)
806 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
807 else if (brw->gen == 5 || brw->is_g4x)
808 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
809 else
810 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
811
812 /* Each of the 8 channel enables is considered for whether each
813 * dword is written.
814 */
815 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
816 brw_set_dest(p, send, dst);
817 brw_set_src0(p, send, header);
818 if (brw->gen < 6)
819 send->header.destreg__conditionalmod = inst->base_mrf;
820 brw_set_dp_read_message(p, send,
821 surf_index,
822 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
823 msg_type,
824 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
825 2, /* mlen */
826 true, /* header_present */
827 1 /* rlen */);
828
829 mark_surface_used(surf_index);
830 }
831
832 void
833 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
834 struct brw_reg dst,
835 struct brw_reg surf_index,
836 struct brw_reg offset)
837 {
838 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
839 surf_index.type == BRW_REGISTER_TYPE_UD);
840
841 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
842 brw_set_dest(p, insn, dst);
843 brw_set_src0(p, insn, offset);
844 brw_set_sampler_message(p, insn,
845 surf_index.dw1.ud,
846 0, /* LD message ignores sampler unit */
847 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
848 1, /* rlen */
849 1, /* mlen */
850 false, /* no header */
851 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
852 0);
853
854 mark_surface_used(surf_index.dw1.ud);
855 }
856
857 void
858 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
859 struct brw_reg dst,
860 struct brw_reg atomic_op,
861 struct brw_reg surf_index)
862 {
863 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
864 atomic_op.type == BRW_REGISTER_TYPE_UD &&
865 surf_index.file == BRW_IMMEDIATE_VALUE &&
866 surf_index.type == BRW_REGISTER_TYPE_UD);
867
868 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
869 atomic_op.dw1.ud, surf_index.dw1.ud,
870 inst->mlen, 1);
871
872 mark_surface_used(surf_index.dw1.ud);
873 }
874
875 /**
876 * Generate assembly for a Vec4 IR instruction.
877 *
878 * \param instruction The Vec4 IR instruction to generate code for.
879 * \param dst The destination register.
880 * \param src An array of up to three source registers.
881 */
882 void
883 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
884 struct brw_reg dst,
885 struct brw_reg *src)
886 {
887 vec4_instruction *inst = (vec4_instruction *) instruction;
888
889 if (dst.width == BRW_WIDTH_4) {
890 /* This happens in attribute fixups for "dual instanced" geometry
891 * shaders, since they use attributes that are vec4's. Since the exec
892 * width is only 4, it's essential that the caller set
893 * force_writemask_all in order to make sure the instruction is executed
894 * regardless of which channels are enabled.
895 */
896 assert(inst->force_writemask_all);
897
898 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
899 * the following register region restrictions (from Graphics BSpec:
900 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
901 * > Register Region Restrictions)
902 *
903 * 1. ExecSize must be greater than or equal to Width.
904 *
905 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
906 * to Width * HorzStride."
907 */
908 for (int i = 0; i < 3; i++) {
909 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
910 src[i] = stride(src[i], 4, 4, 1);
911 }
912 }
913
914 switch (inst->opcode) {
915 case BRW_OPCODE_MOV:
916 brw_MOV(p, dst, src[0]);
917 break;
918 case BRW_OPCODE_ADD:
919 brw_ADD(p, dst, src[0], src[1]);
920 break;
921 case BRW_OPCODE_MUL:
922 brw_MUL(p, dst, src[0], src[1]);
923 break;
924 case BRW_OPCODE_MACH:
925 brw_set_acc_write_control(p, 1);
926 brw_MACH(p, dst, src[0], src[1]);
927 brw_set_acc_write_control(p, 0);
928 break;
929
930 case BRW_OPCODE_MAD:
931 assert(brw->gen >= 6);
932 brw_MAD(p, dst, src[0], src[1], src[2]);
933 break;
934
935 case BRW_OPCODE_FRC:
936 brw_FRC(p, dst, src[0]);
937 break;
938 case BRW_OPCODE_RNDD:
939 brw_RNDD(p, dst, src[0]);
940 break;
941 case BRW_OPCODE_RNDE:
942 brw_RNDE(p, dst, src[0]);
943 break;
944 case BRW_OPCODE_RNDZ:
945 brw_RNDZ(p, dst, src[0]);
946 break;
947
948 case BRW_OPCODE_AND:
949 brw_AND(p, dst, src[0], src[1]);
950 break;
951 case BRW_OPCODE_OR:
952 brw_OR(p, dst, src[0], src[1]);
953 break;
954 case BRW_OPCODE_XOR:
955 brw_XOR(p, dst, src[0], src[1]);
956 break;
957 case BRW_OPCODE_NOT:
958 brw_NOT(p, dst, src[0]);
959 break;
960 case BRW_OPCODE_ASR:
961 brw_ASR(p, dst, src[0], src[1]);
962 break;
963 case BRW_OPCODE_SHR:
964 brw_SHR(p, dst, src[0], src[1]);
965 break;
966 case BRW_OPCODE_SHL:
967 brw_SHL(p, dst, src[0], src[1]);
968 break;
969
970 case BRW_OPCODE_CMP:
971 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
972 break;
973 case BRW_OPCODE_SEL:
974 brw_SEL(p, dst, src[0], src[1]);
975 break;
976
977 case BRW_OPCODE_DPH:
978 brw_DPH(p, dst, src[0], src[1]);
979 break;
980
981 case BRW_OPCODE_DP4:
982 brw_DP4(p, dst, src[0], src[1]);
983 break;
984
985 case BRW_OPCODE_DP3:
986 brw_DP3(p, dst, src[0], src[1]);
987 break;
988
989 case BRW_OPCODE_DP2:
990 brw_DP2(p, dst, src[0], src[1]);
991 break;
992
993 case BRW_OPCODE_F32TO16:
994 assert(brw->gen >= 7);
995 brw_F32TO16(p, dst, src[0]);
996 break;
997
998 case BRW_OPCODE_F16TO32:
999 assert(brw->gen >= 7);
1000 brw_F16TO32(p, dst, src[0]);
1001 break;
1002
1003 case BRW_OPCODE_LRP:
1004 assert(brw->gen >= 6);
1005 brw_LRP(p, dst, src[0], src[1], src[2]);
1006 break;
1007
1008 case BRW_OPCODE_BFREV:
1009 assert(brw->gen >= 7);
1010 /* BFREV only supports UD type for src and dst. */
1011 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1012 retype(src[0], BRW_REGISTER_TYPE_UD));
1013 break;
1014 case BRW_OPCODE_FBH:
1015 assert(brw->gen >= 7);
1016 /* FBH only supports UD type for dst. */
1017 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1018 break;
1019 case BRW_OPCODE_FBL:
1020 assert(brw->gen >= 7);
1021 /* FBL only supports UD type for dst. */
1022 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1023 break;
1024 case BRW_OPCODE_CBIT:
1025 assert(brw->gen >= 7);
1026 /* CBIT only supports UD type for dst. */
1027 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1028 break;
1029 case BRW_OPCODE_ADDC:
1030 assert(brw->gen >= 7);
1031 brw_set_acc_write_control(p, 1);
1032 brw_ADDC(p, dst, src[0], src[1]);
1033 brw_set_acc_write_control(p, 0);
1034 break;
1035 case BRW_OPCODE_SUBB:
1036 assert(brw->gen >= 7);
1037 brw_set_acc_write_control(p, 1);
1038 brw_SUBB(p, dst, src[0], src[1]);
1039 brw_set_acc_write_control(p, 0);
1040 break;
1041
1042 case BRW_OPCODE_BFE:
1043 assert(brw->gen >= 7);
1044 brw_BFE(p, dst, src[0], src[1], src[2]);
1045 break;
1046
1047 case BRW_OPCODE_BFI1:
1048 assert(brw->gen >= 7);
1049 brw_BFI1(p, dst, src[0], src[1]);
1050 break;
1051 case BRW_OPCODE_BFI2:
1052 assert(brw->gen >= 7);
1053 brw_BFI2(p, dst, src[0], src[1], src[2]);
1054 break;
1055
1056 case BRW_OPCODE_IF:
1057 if (inst->src[0].file != BAD_FILE) {
1058 /* The instruction has an embedded compare (only allowed on gen6) */
1059 assert(brw->gen == 6);
1060 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1061 } else {
1062 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
1063 brw_inst->header.predicate_control = inst->predicate;
1064 }
1065 break;
1066
1067 case BRW_OPCODE_ELSE:
1068 brw_ELSE(p);
1069 break;
1070 case BRW_OPCODE_ENDIF:
1071 brw_ENDIF(p);
1072 break;
1073
1074 case BRW_OPCODE_DO:
1075 brw_DO(p, BRW_EXECUTE_8);
1076 break;
1077
1078 case BRW_OPCODE_BREAK:
1079 brw_BREAK(p);
1080 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1081 break;
1082 case BRW_OPCODE_CONTINUE:
1083 /* FINISHME: We need to write the loop instruction support still. */
1084 if (brw->gen >= 6)
1085 gen6_CONT(p);
1086 else
1087 brw_CONT(p);
1088 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1089 break;
1090
1091 case BRW_OPCODE_WHILE:
1092 brw_WHILE(p);
1093 break;
1094
1095 case SHADER_OPCODE_RCP:
1096 case SHADER_OPCODE_RSQ:
1097 case SHADER_OPCODE_SQRT:
1098 case SHADER_OPCODE_EXP2:
1099 case SHADER_OPCODE_LOG2:
1100 case SHADER_OPCODE_SIN:
1101 case SHADER_OPCODE_COS:
1102 if (brw->gen == 6) {
1103 generate_math1_gen6(inst, dst, src[0]);
1104 } else {
1105 /* Also works for Gen7. */
1106 generate_math1_gen4(inst, dst, src[0]);
1107 }
1108 break;
1109
1110 case SHADER_OPCODE_POW:
1111 case SHADER_OPCODE_INT_QUOTIENT:
1112 case SHADER_OPCODE_INT_REMAINDER:
1113 if (brw->gen >= 7) {
1114 generate_math2_gen7(inst, dst, src[0], src[1]);
1115 } else if (brw->gen == 6) {
1116 generate_math2_gen6(inst, dst, src[0], src[1]);
1117 } else {
1118 generate_math2_gen4(inst, dst, src[0], src[1]);
1119 }
1120 break;
1121
1122 case SHADER_OPCODE_TEX:
1123 case SHADER_OPCODE_TXD:
1124 case SHADER_OPCODE_TXF:
1125 case SHADER_OPCODE_TXF_MS:
1126 case SHADER_OPCODE_TXL:
1127 case SHADER_OPCODE_TXS:
1128 case SHADER_OPCODE_TG4:
1129 case SHADER_OPCODE_TG4_OFFSET:
1130 generate_tex(inst, dst, src[0]);
1131 break;
1132
1133 case VS_OPCODE_URB_WRITE:
1134 generate_vs_urb_write(inst);
1135 break;
1136
1137 case VS_OPCODE_SCRATCH_READ:
1138 generate_scratch_read(inst, dst, src[0]);
1139 break;
1140
1141 case VS_OPCODE_SCRATCH_WRITE:
1142 generate_scratch_write(inst, dst, src[0], src[1]);
1143 break;
1144
1145 case VS_OPCODE_PULL_CONSTANT_LOAD:
1146 generate_pull_constant_load(inst, dst, src[0], src[1]);
1147 break;
1148
1149 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1150 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1151 break;
1152
1153 case GS_OPCODE_URB_WRITE:
1154 generate_gs_urb_write(inst);
1155 break;
1156
1157 case GS_OPCODE_THREAD_END:
1158 generate_gs_thread_end(inst);
1159 break;
1160
1161 case GS_OPCODE_SET_WRITE_OFFSET:
1162 generate_gs_set_write_offset(dst, src[0], src[1]);
1163 break;
1164
1165 case GS_OPCODE_SET_VERTEX_COUNT:
1166 generate_gs_set_vertex_count(dst, src[0]);
1167 break;
1168
1169 case GS_OPCODE_SET_DWORD_2_IMMED:
1170 generate_gs_set_dword_2_immed(dst, src[0]);
1171 break;
1172
1173 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1174 generate_gs_prepare_channel_masks(dst);
1175 break;
1176
1177 case GS_OPCODE_SET_CHANNEL_MASKS:
1178 generate_gs_set_channel_masks(dst, src[0]);
1179 break;
1180
1181 case SHADER_OPCODE_SHADER_TIME_ADD:
1182 brw_shader_time_add(p, src[0],
1183 prog_data->base.binding_table.shader_time_start);
1184 mark_surface_used(prog_data->base.binding_table.shader_time_start);
1185 break;
1186
1187 case SHADER_OPCODE_UNTYPED_ATOMIC:
1188 generate_untyped_atomic(inst, dst, src[0], src[1]);
1189 break;
1190
1191 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1192 generate_unpack_flags(inst, dst);
1193 break;
1194
1195 default:
1196 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1197 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in VS\n",
1198 opcode_descs[inst->opcode].name);
1199 } else {
1200 _mesa_problem(&brw->ctx, "Unsupported opcode %d in VS", inst->opcode);
1201 }
1202 abort();
1203 }
1204 }
1205
1206 void
1207 vec4_generator::generate_code(exec_list *instructions)
1208 {
1209 int last_native_insn_offset = 0;
1210 const char *last_annotation_string = NULL;
1211 const void *last_annotation_ir = NULL;
1212
1213 if (unlikely(debug_flag)) {
1214 if (shader) {
1215 printf("Native code for vertex shader %d:\n", shader_prog->Name);
1216 } else {
1217 printf("Native code for vertex program %d:\n", prog->Id);
1218 }
1219 }
1220
1221 foreach_list(node, instructions) {
1222 vec4_instruction *inst = (vec4_instruction *)node;
1223 struct brw_reg src[3], dst;
1224
1225 if (unlikely(debug_flag)) {
1226 if (last_annotation_ir != inst->ir) {
1227 last_annotation_ir = inst->ir;
1228 if (last_annotation_ir) {
1229 printf(" ");
1230 if (shader) {
1231 ((ir_instruction *) last_annotation_ir)->print();
1232 } else {
1233 const prog_instruction *vpi;
1234 vpi = (const prog_instruction *) inst->ir;
1235 printf("%d: ", (int)(vpi - prog->Instructions));
1236 _mesa_fprint_instruction_opt(stdout, vpi, 0,
1237 PROG_PRINT_DEBUG, NULL);
1238 }
1239 printf("\n");
1240 }
1241 }
1242 if (last_annotation_string != inst->annotation) {
1243 last_annotation_string = inst->annotation;
1244 if (last_annotation_string)
1245 printf(" %s\n", last_annotation_string);
1246 }
1247 }
1248
1249 for (unsigned int i = 0; i < 3; i++) {
1250 src[i] = inst->get_src(this->prog_data, i);
1251 }
1252 dst = inst->get_dst();
1253
1254 brw_set_conditionalmod(p, inst->conditional_mod);
1255 brw_set_predicate_control(p, inst->predicate);
1256 brw_set_predicate_inverse(p, inst->predicate_inverse);
1257 brw_set_saturate(p, inst->saturate);
1258 brw_set_mask_control(p, inst->force_writemask_all);
1259
1260 unsigned pre_emit_nr_insn = p->nr_insn;
1261
1262 generate_vec4_instruction(inst, dst, src);
1263
1264 if (inst->no_dd_clear || inst->no_dd_check) {
1265 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1266 !"no_dd_check or no_dd_clear set for IR emitting more "
1267 "than 1 instruction");
1268
1269 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
1270
1271 if (inst->no_dd_clear)
1272 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
1273 if (inst->no_dd_check)
1274 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
1275 }
1276
1277 if (unlikely(debug_flag)) {
1278 brw_dump_compile(p, stdout,
1279 last_native_insn_offset, p->next_insn_offset);
1280 }
1281
1282 last_native_insn_offset = p->next_insn_offset;
1283 }
1284
1285 if (unlikely(debug_flag)) {
1286 printf("\n");
1287 }
1288
1289 brw_set_uip_jip(p);
1290
1291 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1292 * emit issues, it doesn't get the jump distances into the output,
1293 * which is often something we want to debug. So this is here in
1294 * case you're doing that.
1295 */
1296 if (0 && unlikely(debug_flag)) {
1297 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1298 }
1299 }
1300
1301 const unsigned *
1302 vec4_generator::generate_assembly(exec_list *instructions,
1303 unsigned *assembly_size)
1304 {
1305 brw_set_access_mode(p, BRW_ALIGN_16);
1306 generate_code(instructions);
1307 return brw_get_program(p, assembly_size);
1308 }
1309
1310 } /* namespace brw */