1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "main/macros.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
37 vec4_instruction::get_dst(void)
39 struct brw_reg brw_reg
;
43 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
44 brw_reg
= retype(brw_reg
, dst
.type
);
45 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
49 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
50 brw_reg
= retype(brw_reg
, dst
.type
);
51 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
55 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
56 brw_reg
= dst
.fixed_hw_reg
;
60 brw_reg
= brw_null_reg();
64 unreachable("not reached");
70 vec4_instruction::get_src(const struct brw_vue_prog_data
*prog_data
, int i
)
72 struct brw_reg brw_reg
;
74 switch (src
[i
].file
) {
76 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
77 brw_reg
= retype(brw_reg
, src
[i
].type
);
78 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
80 brw_reg
= brw_abs(brw_reg
);
82 brw_reg
= negate(brw_reg
);
86 switch (src
[i
].type
) {
87 case BRW_REGISTER_TYPE_F
:
88 brw_reg
= brw_imm_f(src
[i
].fixed_hw_reg
.dw1
.f
);
90 case BRW_REGISTER_TYPE_D
:
91 brw_reg
= brw_imm_d(src
[i
].fixed_hw_reg
.dw1
.d
);
93 case BRW_REGISTER_TYPE_UD
:
94 brw_reg
= brw_imm_ud(src
[i
].fixed_hw_reg
.dw1
.ud
);
96 case BRW_REGISTER_TYPE_VF
:
97 brw_reg
= brw_imm_vf(src
[i
].fixed_hw_reg
.dw1
.ud
);
100 unreachable("not reached");
105 brw_reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
106 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
107 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
109 brw_reg
= retype(brw_reg
, src
[i
].type
);
110 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
112 brw_reg
= brw_abs(brw_reg
);
114 brw_reg
= negate(brw_reg
);
116 /* This should have been moved to pull constants. */
117 assert(!src
[i
].reladdr
);
121 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
122 brw_reg
= src
[i
].fixed_hw_reg
;
126 /* Probably unused. */
127 brw_reg
= brw_null_reg();
131 unreachable("not reached");
137 vec4_generator::vec4_generator(struct brw_context
*brw
,
138 struct gl_shader_program
*shader_prog
,
139 struct gl_program
*prog
,
140 struct brw_vue_prog_data
*prog_data
,
143 const char *stage_name
,
144 const char *stage_abbrev
)
145 : brw(brw
), devinfo(brw
->intelScreen
->devinfo
),
146 shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
147 mem_ctx(mem_ctx
), stage_name(stage_name
), stage_abbrev(stage_abbrev
),
148 debug_flag(debug_flag
)
150 p
= rzalloc(mem_ctx
, struct brw_codegen
);
151 brw_init_codegen(brw
->intelScreen
->devinfo
, p
, mem_ctx
);
154 vec4_generator::~vec4_generator()
159 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
165 brw_math_function(inst
->opcode
),
168 BRW_MATH_PRECISION_FULL
);
172 check_gen6_math_src_arg(struct brw_reg src
)
174 /* Source swizzles are ignored. */
177 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
181 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
186 /* Can't do writemask because math can't be align16. */
187 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
188 /* Source swizzles are ignored. */
189 check_gen6_math_src_arg(src0
);
190 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
191 check_gen6_math_src_arg(src1
);
193 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
194 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
195 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
199 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
204 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
207 * "Operand0[7]. For the INT DIV functions, this operand is the
210 * "Operand1[7]. For the INT DIV functions, this operand is the
213 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
214 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
215 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
217 brw_push_insn_state(p
);
218 brw_set_default_saturate(p
, false);
219 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
220 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
221 brw_pop_insn_state(p
);
225 brw_math_function(inst
->opcode
),
228 BRW_MATH_PRECISION_FULL
);
232 vec4_generator::generate_tex(vec4_instruction
*inst
,
235 struct brw_reg sampler_index
)
239 if (devinfo
->gen
>= 5) {
240 switch (inst
->opcode
) {
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXL
:
243 if (inst
->shadow_compare
) {
244 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
246 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
249 case SHADER_OPCODE_TXD
:
250 if (inst
->shadow_compare
) {
251 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
252 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
253 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
255 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
258 case SHADER_OPCODE_TXF
:
259 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
261 case SHADER_OPCODE_TXF_CMS
:
262 if (devinfo
->gen
>= 7)
263 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
265 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
267 case SHADER_OPCODE_TXF_MCS
:
268 assert(devinfo
->gen
>= 7);
269 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
271 case SHADER_OPCODE_TXS
:
272 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
274 case SHADER_OPCODE_TG4
:
275 if (inst
->shadow_compare
) {
276 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
278 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
281 case SHADER_OPCODE_TG4_OFFSET
:
282 if (inst
->shadow_compare
) {
283 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
285 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
289 unreachable("should not get here: invalid vec4 texture opcode");
292 switch (inst
->opcode
) {
293 case SHADER_OPCODE_TEX
:
294 case SHADER_OPCODE_TXL
:
295 if (inst
->shadow_compare
) {
296 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
297 assert(inst
->mlen
== 3);
299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
300 assert(inst
->mlen
== 2);
303 case SHADER_OPCODE_TXD
:
304 /* There is no sample_d_c message; comparisons are done manually. */
305 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
306 assert(inst
->mlen
== 4);
308 case SHADER_OPCODE_TXF
:
309 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
310 assert(inst
->mlen
== 2);
312 case SHADER_OPCODE_TXS
:
313 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
314 assert(inst
->mlen
== 2);
317 unreachable("should not get here: invalid vec4 texture opcode");
321 assert(msg_type
!= -1);
323 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
325 /* Load the message header if present. If there's a texture offset, we need
326 * to set it up explicitly and load the offset bitfield. Otherwise, we can
327 * use an implied move from g0 to the first message register.
329 if (inst
->header_present
) {
330 if (devinfo
->gen
< 6 && !inst
->offset
) {
331 /* Set up an implied move from g0 to the MRF. */
332 src
= brw_vec8_grf(0, 0);
334 struct brw_reg header
=
335 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
338 /* Explicitly set up the message header by copying g0 to the MRF. */
339 brw_push_insn_state(p
);
340 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
341 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
343 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
346 /* Set the texel offset bits in DWord 2. */
349 if (devinfo
->gen
>= 9)
350 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
351 * based on bit 22 in the header.
353 dw2
|= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
;
356 brw_MOV(p
, get_element_ud(header
, 2), brw_imm_ud(dw2
));
358 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
);
359 brw_pop_insn_state(p
);
363 uint32_t return_format
;
366 case BRW_REGISTER_TYPE_D
:
367 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
369 case BRW_REGISTER_TYPE_UD
:
370 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
373 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
377 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
378 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
379 ? prog_data
->base
.binding_table
.gather_texture_start
380 : prog_data
->base
.binding_table
.texture_start
;
382 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
383 uint32_t sampler
= sampler_index
.dw1
.ud
;
389 sampler
+ base_binding_table_index
,
392 1, /* response length */
394 inst
->header_present
,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
398 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
400 /* Non-constant sampler index. */
401 /* Note: this clobbers `dst` as a temporary before emitting the send */
403 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
404 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
406 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
408 brw_push_insn_state(p
);
409 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
410 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
412 /* Some care required: `sampler` and `temp` may alias:
413 * addr = sampler & 0xff
414 * temp = (sampler << 8) & 0xf00
417 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
418 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
419 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
420 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
421 brw_OR(p
, addr
, addr
, temp
);
423 brw_pop_insn_state(p
);
425 /* dst = send(offset, a0.0 | <descriptor>) */
426 brw_inst
*insn
= brw_send_indirect_message(
427 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
428 brw_set_sampler_message(p
, insn
,
433 inst
->mlen
/* mlen */,
434 inst
->header_present
/* header */,
435 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
438 /* visitor knows more than we do about the surface limit required,
439 * so has already done marking.
445 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
448 brw_null_reg(), /* dest */
449 inst
->base_mrf
, /* starting mrf reg nr */
450 brw_vec8_grf(0, 0), /* src */
451 inst
->urb_write_flags
,
453 0, /* response len */
454 inst
->offset
, /* urb destination offset */
455 BRW_URB_SWIZZLE_INTERLEAVE
);
459 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
461 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
463 brw_null_reg(), /* dest */
464 inst
->base_mrf
, /* starting mrf reg nr */
466 inst
->urb_write_flags
,
468 0, /* response len */
469 inst
->offset
, /* urb destination offset */
470 BRW_URB_SWIZZLE_INTERLEAVE
);
474 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction
*inst
)
476 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
478 /* We pass the temporary passed in src0 as the writeback register */
480 inst
->get_src(this->prog_data
, 0), /* dest */
481 inst
->base_mrf
, /* starting mrf reg nr */
483 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
485 1, /* response len */
486 inst
->offset
, /* urb destination offset */
487 BRW_URB_SWIZZLE_INTERLEAVE
);
489 /* Now put allocated urb handle in dst.0 */
490 brw_push_insn_state(p
);
491 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
492 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
493 brw_MOV(p
, get_element_ud(inst
->get_dst(), 0),
494 get_element_ud(inst
->get_src(this->prog_data
, 0), 0));
495 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
496 brw_pop_insn_state(p
);
500 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
502 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
504 brw_null_reg(), /* dest */
505 inst
->base_mrf
, /* starting mrf reg nr */
507 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
508 devinfo
->gen
>= 8 ? 2 : 1,/* message len */
509 0, /* response len */
510 0, /* urb destination offset */
511 BRW_URB_SWIZZLE_INTERLEAVE
);
515 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
519 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
522 * Slot 0 Offset. This field, after adding to the Global Offset field
523 * in the message descriptor, specifies the offset (in 256-bit units)
524 * from the start of the URB entry, as referenced by URB Handle 0, at
525 * which the data will be accessed.
527 * Similar text describes DWORD M0.4, which is slot 1 offset.
529 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
530 * of the register for geometry shader invocations 0 and 1) by the
531 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
533 * We can do this with the following EU instruction:
535 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
537 brw_push_insn_state(p
);
538 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
539 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
540 assert(devinfo
->gen
>= 7 &&
541 src1
.file
== BRW_IMMEDIATE_VALUE
&&
542 src1
.type
== BRW_REGISTER_TYPE_UD
&&
543 src1
.dw1
.ud
<= USHRT_MAX
);
544 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
545 retype(src1
, BRW_REGISTER_TYPE_UW
));
546 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
547 brw_pop_insn_state(p
);
551 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
554 brw_push_insn_state(p
);
555 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
557 if (devinfo
->gen
>= 8) {
558 /* Move the vertex count into the second MRF for the EOT write. */
559 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
562 /* If we think of the src and dst registers as composed of 8 DWORDs each,
563 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
564 * them to WORDs, and then pack them into DWORD 2 of dst.
566 * It's easier to get the EU to do this if we think of the src and dst
567 * registers as composed of 16 WORDS each; then, we want to pick up the
568 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
571 * We can do that by the following EU instruction:
573 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
575 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
577 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
578 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
579 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
581 brw_pop_insn_state(p
);
585 vec4_generator::generate_gs_svb_write(vec4_instruction
*inst
,
590 int binding
= inst
->sol_binding
;
591 bool final_write
= inst
->sol_final_write
;
593 brw_push_insn_state(p
);
594 /* Copy Vertex data into M0.x */
595 brw_MOV(p
, stride(dst
, 4, 4, 1),
596 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
600 final_write
? src1
: brw_null_reg(), /* dest == src1 */
602 dst
, /* src0 == previous dst */
603 SURF_INDEX_GEN6_SOL_BINDING(binding
), /* binding_table_index */
604 final_write
); /* send_commit_msg */
606 /* Finally, wait for the write commit to occur so that we can proceed to
607 * other things safely.
609 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
611 * The write commit does not modify the destination register, but
612 * merely clears the dependency associated with the destination
613 * register. Thus, a simple “mov” instruction using the register as a
614 * source is sufficient to wait for the write commit to occur.
617 brw_MOV(p
, src1
, src1
);
619 brw_pop_insn_state(p
);
623 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction
*inst
,
628 int vertex
= inst
->sol_vertex
;
629 brw_push_insn_state(p
);
630 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
631 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
632 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
633 brw_pop_insn_state(p
);
637 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst
, struct brw_reg src
)
639 brw_push_insn_state(p
);
640 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
641 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
642 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
643 brw_pop_insn_state(p
);
647 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
649 /* We want to left shift just DWORD 4 (the x component belonging to the
650 * second geometry shader invocation) by 4 bits. So generate the
653 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
655 dst
= suboffset(vec1(dst
), 4);
656 brw_push_insn_state(p
);
657 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
658 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
659 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
660 brw_pop_insn_state(p
);
664 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
667 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
670 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
672 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
673 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
674 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
675 * channel enable to determine the final channel enable. For the
676 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
677 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
678 * in the writeback message. For the URB_WRITE_OWORD &
679 * URB_WRITE_HWORD messages, when final channel enable is 1 it
680 * indicates that Vertex 1 DATA [3] will be written to the surface.
682 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
683 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
685 * 14 Vertex 1 DATA [2] Channel Mask
686 * 13 Vertex 1 DATA [1] Channel Mask
687 * 12 Vertex 1 DATA [0] Channel Mask
688 * 11 Vertex 0 DATA [3] Channel Mask
689 * 10 Vertex 0 DATA [2] Channel Mask
690 * 9 Vertex 0 DATA [1] Channel Mask
691 * 8 Vertex 0 DATA [0] Channel Mask
693 * (This is from a section of the PRM that is agnostic to the particular
694 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
695 * geometry shader invocations 0 and 1, respectively). Since we have the
696 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
697 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
698 * DWORD 4, we just need to OR them together and store the result in bits
701 * It's easier to get the EU to do this if we think of the src and dst
702 * registers as composed of 32 bytes each; then, we want to pick up the
703 * contents of bytes 0 and 16 from src, OR them together, and store them in
706 * We can do that by the following EU instruction:
708 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
710 * Note: this relies on the source register having zeros in (a) bits 7:4 of
711 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
712 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
713 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
714 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
715 * contain valid channel mask values (which are in the range 0x0-0xf).
717 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
718 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
719 brw_push_insn_state(p
);
720 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
721 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
722 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
723 brw_pop_insn_state(p
);
727 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
729 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
730 * and store into dst.0 & dst.4. So generate the instruction:
732 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
734 brw_push_insn_state(p
);
735 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
736 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
737 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
738 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
739 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
740 brw_pop_insn_state(p
);
744 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst
,
749 brw_push_insn_state(p
);
750 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
751 /* Save src0 data in 16:31 bits of dst.0 */
752 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
753 brw_imm_ud(0xffffu
));
754 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
755 /* Save src1 data in 0:15 bits of dst.0 */
756 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
757 brw_imm_ud(0xffffu
));
758 brw_OR(p
, suboffset(vec1(dst
), 0),
759 suboffset(vec1(dst
), 0),
760 suboffset(vec1(src2
), 0));
761 brw_pop_insn_state(p
);
765 vec4_generator::generate_gs_ff_sync(vec4_instruction
*inst
,
770 /* This opcode uses an implied MRF register for:
771 * - the header of the ff_sync message. And as such it is expected to be
772 * initialized to r0 before calling here.
773 * - the destination where we will write the allocated URB handle.
775 struct brw_reg header
=
776 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
778 /* Overwrite dword 0 of the header (SO vertices to write) and
779 * dword 1 (number of primitives written).
781 brw_push_insn_state(p
);
782 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
783 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
784 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(src1
, 0));
785 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
786 brw_pop_insn_state(p
);
788 /* Allocate URB handle in dst */
794 1, /* response length */
797 /* Now put allocated urb handle in header.0 */
798 brw_push_insn_state(p
);
799 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
800 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
801 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
803 /* src1 is not an immediate when we use transform feedback */
804 if (src1
.file
!= BRW_IMMEDIATE_VALUE
)
805 brw_MOV(p
, brw_vec4_grf(src1
.nr
, 0), brw_vec4_grf(dst
.nr
, 1));
807 brw_pop_insn_state(p
);
811 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst
)
813 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
814 struct brw_reg src
= brw_vec8_grf(0, 0);
815 brw_push_insn_state(p
);
816 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
817 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
818 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
819 brw_pop_insn_state(p
);
823 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
824 struct brw_reg index
)
826 int second_vertex_offset
;
828 if (devinfo
->gen
>= 6)
829 second_vertex_offset
= 1;
831 second_vertex_offset
= 16;
833 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
835 /* Set up M1 (message payload). Only the block offsets in M1.0 and
836 * M1.4 are used, and the rest are ignored.
838 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
839 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
840 struct brw_reg index_0
= suboffset(vec1(index
), 0);
841 struct brw_reg index_4
= suboffset(vec1(index
), 4);
843 brw_push_insn_state(p
);
844 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
845 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
847 brw_MOV(p
, m1_0
, index_0
);
849 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
850 index_4
.dw1
.ud
+= second_vertex_offset
;
851 brw_MOV(p
, m1_4
, index_4
);
853 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
856 brw_pop_insn_state(p
);
860 vec4_generator::generate_unpack_flags(struct brw_reg dst
)
862 brw_push_insn_state(p
);
863 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
864 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
866 struct brw_reg flags
= brw_flag_reg(0, 0);
867 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
868 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
870 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
871 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
872 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
874 brw_pop_insn_state(p
);
878 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
880 struct brw_reg index
)
882 struct brw_reg header
= brw_vec8_grf(0, 0);
884 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
886 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
891 if (devinfo
->gen
>= 6)
892 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
893 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
894 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
896 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
898 /* Each of the 8 channel enables is considered for whether each
901 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
902 brw_set_dest(p
, send
, dst
);
903 brw_set_src0(p
, send
, header
);
904 if (devinfo
->gen
< 6)
905 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
906 brw_set_dp_read_message(p
, send
,
907 255, /* binding table index: stateless access */
908 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
910 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
912 true, /* header_present */
917 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
920 struct brw_reg index
)
922 struct brw_reg header
= brw_vec8_grf(0, 0);
925 /* If the instruction is predicated, we'll predicate the send, not
928 brw_set_default_predicate_control(p
, false);
930 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
932 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
936 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
937 retype(src
, BRW_REGISTER_TYPE_D
));
941 if (devinfo
->gen
>= 7)
942 msg_type
= GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
;
943 else if (devinfo
->gen
== 6)
944 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
946 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
948 brw_set_default_predicate_control(p
, inst
->predicate
);
950 /* Pre-gen6, we have to specify write commits to ensure ordering
951 * between reads and writes within a thread. Afterwards, that's
952 * guaranteed and write commits only matter for inter-thread
955 if (devinfo
->gen
>= 6) {
956 write_commit
= false;
958 /* The visitor set up our destination register to be g0. This
959 * means that when the next read comes along, we will end up
960 * reading from g0 and causing a block on the write commit. For
961 * write-after-read, we are relying on the value of the previous
962 * read being used (and thus blocking on completion) before our
963 * write is executed. This means we have to be careful in
964 * instruction scheduling to not violate this assumption.
969 /* Each of the 8 channel enables is considered for whether each
972 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
973 brw_set_dest(p
, send
, dst
);
974 brw_set_src0(p
, send
, header
);
975 if (devinfo
->gen
< 6)
976 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
977 brw_set_dp_write_message(p
, send
,
978 255, /* binding table index: stateless access */
979 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
982 true, /* header present */
983 false, /* not a render target write */
984 write_commit
, /* rlen */
990 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
992 struct brw_reg index
,
993 struct brw_reg offset
)
995 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
996 index
.type
== BRW_REGISTER_TYPE_UD
);
997 uint32_t surf_index
= index
.dw1
.ud
;
999 struct brw_reg header
= brw_vec8_grf(0, 0);
1001 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1003 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
1008 if (devinfo
->gen
>= 6)
1009 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1010 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1011 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1013 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1015 /* Each of the 8 channel enables is considered for whether each
1018 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1019 brw_set_dest(p
, send
, dst
);
1020 brw_set_src0(p
, send
, header
);
1021 if (devinfo
->gen
< 6)
1022 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1023 brw_set_dp_read_message(p
, send
,
1025 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1027 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
1029 true, /* header_present */
1032 brw_mark_surface_used(&prog_data
->base
, surf_index
);
1036 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
1038 struct brw_reg surf_index
,
1039 struct brw_reg offset
)
1041 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1043 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
1045 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1046 brw_set_dest(p
, insn
, dst
);
1047 brw_set_src0(p
, insn
, offset
);
1048 brw_set_sampler_message(p
, insn
,
1050 0, /* LD message ignores sampler unit */
1051 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1054 inst
->header_present
,
1055 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1058 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
1062 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1064 brw_push_insn_state(p
);
1065 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1066 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1068 /* a0.0 = surf_index & 0xff */
1069 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1070 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1071 brw_set_dest(p
, insn_and
, addr
);
1072 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1073 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1075 brw_pop_insn_state(p
);
1077 /* dst = send(offset, a0.0 | <descriptor>) */
1078 brw_inst
*insn
= brw_send_indirect_message(
1079 p
, BRW_SFID_SAMPLER
, dst
, offset
, addr
);
1080 brw_set_sampler_message(p
, insn
,
1083 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1086 inst
->header_present
,
1087 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1090 /* visitor knows more than we do about the surface limit required,
1091 * so has already done marking.
1097 vec4_generator::generate_set_simd4x2_header_gen9(vec4_instruction
*inst
,
1100 brw_push_insn_state(p
);
1101 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1103 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1104 brw_MOV(p
, vec8(dst
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1106 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1107 brw_MOV(p
, get_element_ud(dst
, 2),
1108 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1110 brw_pop_insn_state(p
);
1114 vec4_generator::generate_code(const cfg_t
*cfg
)
1116 struct annotation_info annotation
;
1117 memset(&annotation
, 0, sizeof(annotation
));
1120 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1121 struct brw_reg src
[3], dst
;
1123 if (unlikely(debug_flag
))
1124 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1126 for (unsigned int i
= 0; i
< 3; i
++) {
1127 src
[i
] = inst
->get_src(this->prog_data
, i
);
1129 dst
= inst
->get_dst();
1131 brw_set_default_predicate_control(p
, inst
->predicate
);
1132 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1133 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1134 brw_set_default_saturate(p
, inst
->saturate
);
1135 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1136 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1138 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1140 if (dst
.width
== BRW_WIDTH_4
) {
1141 /* This happens in attribute fixups for "dual instanced" geometry
1142 * shaders, since they use attributes that are vec4's. Since the exec
1143 * width is only 4, it's essential that the caller set
1144 * force_writemask_all in order to make sure the instruction is executed
1145 * regardless of which channels are enabled.
1147 assert(inst
->force_writemask_all
);
1149 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1150 * the following register region restrictions (from Graphics BSpec:
1151 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1152 * > Register Region Restrictions)
1154 * 1. ExecSize must be greater than or equal to Width.
1156 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1157 * to Width * HorzStride."
1159 for (int i
= 0; i
< 3; i
++) {
1160 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
1161 src
[i
] = stride(src
[i
], 4, 4, 1);
1165 switch (inst
->opcode
) {
1166 case VEC4_OPCODE_UNPACK_UNIFORM
:
1167 case BRW_OPCODE_MOV
:
1168 brw_MOV(p
, dst
, src
[0]);
1170 case BRW_OPCODE_ADD
:
1171 brw_ADD(p
, dst
, src
[0], src
[1]);
1173 case BRW_OPCODE_MUL
:
1174 brw_MUL(p
, dst
, src
[0], src
[1]);
1176 case BRW_OPCODE_MACH
:
1177 brw_MACH(p
, dst
, src
[0], src
[1]);
1180 case BRW_OPCODE_MAD
:
1181 assert(devinfo
->gen
>= 6);
1182 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1185 case BRW_OPCODE_FRC
:
1186 brw_FRC(p
, dst
, src
[0]);
1188 case BRW_OPCODE_RNDD
:
1189 brw_RNDD(p
, dst
, src
[0]);
1191 case BRW_OPCODE_RNDE
:
1192 brw_RNDE(p
, dst
, src
[0]);
1194 case BRW_OPCODE_RNDZ
:
1195 brw_RNDZ(p
, dst
, src
[0]);
1198 case BRW_OPCODE_AND
:
1199 brw_AND(p
, dst
, src
[0], src
[1]);
1202 brw_OR(p
, dst
, src
[0], src
[1]);
1204 case BRW_OPCODE_XOR
:
1205 brw_XOR(p
, dst
, src
[0], src
[1]);
1207 case BRW_OPCODE_NOT
:
1208 brw_NOT(p
, dst
, src
[0]);
1210 case BRW_OPCODE_ASR
:
1211 brw_ASR(p
, dst
, src
[0], src
[1]);
1213 case BRW_OPCODE_SHR
:
1214 brw_SHR(p
, dst
, src
[0], src
[1]);
1216 case BRW_OPCODE_SHL
:
1217 brw_SHL(p
, dst
, src
[0], src
[1]);
1220 case BRW_OPCODE_CMP
:
1221 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1223 case BRW_OPCODE_SEL
:
1224 brw_SEL(p
, dst
, src
[0], src
[1]);
1227 case BRW_OPCODE_DPH
:
1228 brw_DPH(p
, dst
, src
[0], src
[1]);
1231 case BRW_OPCODE_DP4
:
1232 brw_DP4(p
, dst
, src
[0], src
[1]);
1235 case BRW_OPCODE_DP3
:
1236 brw_DP3(p
, dst
, src
[0], src
[1]);
1239 case BRW_OPCODE_DP2
:
1240 brw_DP2(p
, dst
, src
[0], src
[1]);
1243 case BRW_OPCODE_F32TO16
:
1244 assert(devinfo
->gen
>= 7);
1245 brw_F32TO16(p
, dst
, src
[0]);
1248 case BRW_OPCODE_F16TO32
:
1249 assert(devinfo
->gen
>= 7);
1250 brw_F16TO32(p
, dst
, src
[0]);
1253 case BRW_OPCODE_LRP
:
1254 assert(devinfo
->gen
>= 6);
1255 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1258 case BRW_OPCODE_BFREV
:
1259 assert(devinfo
->gen
>= 7);
1260 /* BFREV only supports UD type for src and dst. */
1261 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1262 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1264 case BRW_OPCODE_FBH
:
1265 assert(devinfo
->gen
>= 7);
1266 /* FBH only supports UD type for dst. */
1267 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1269 case BRW_OPCODE_FBL
:
1270 assert(devinfo
->gen
>= 7);
1271 /* FBL only supports UD type for dst. */
1272 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1274 case BRW_OPCODE_CBIT
:
1275 assert(devinfo
->gen
>= 7);
1276 /* CBIT only supports UD type for dst. */
1277 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1279 case BRW_OPCODE_ADDC
:
1280 assert(devinfo
->gen
>= 7);
1281 brw_ADDC(p
, dst
, src
[0], src
[1]);
1283 case BRW_OPCODE_SUBB
:
1284 assert(devinfo
->gen
>= 7);
1285 brw_SUBB(p
, dst
, src
[0], src
[1]);
1287 case BRW_OPCODE_MAC
:
1288 brw_MAC(p
, dst
, src
[0], src
[1]);
1291 case BRW_OPCODE_BFE
:
1292 assert(devinfo
->gen
>= 7);
1293 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1296 case BRW_OPCODE_BFI1
:
1297 assert(devinfo
->gen
>= 7);
1298 brw_BFI1(p
, dst
, src
[0], src
[1]);
1300 case BRW_OPCODE_BFI2
:
1301 assert(devinfo
->gen
>= 7);
1302 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1306 if (inst
->src
[0].file
!= BAD_FILE
) {
1307 /* The instruction has an embedded compare (only allowed on gen6) */
1308 assert(devinfo
->gen
== 6);
1309 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1311 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1312 brw_inst_set_pred_control(p
->devinfo
, if_inst
, inst
->predicate
);
1316 case BRW_OPCODE_ELSE
:
1319 case BRW_OPCODE_ENDIF
:
1324 brw_DO(p
, BRW_EXECUTE_8
);
1327 case BRW_OPCODE_BREAK
:
1329 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1331 case BRW_OPCODE_CONTINUE
:
1333 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1336 case BRW_OPCODE_WHILE
:
1341 case SHADER_OPCODE_RCP
:
1342 case SHADER_OPCODE_RSQ
:
1343 case SHADER_OPCODE_SQRT
:
1344 case SHADER_OPCODE_EXP2
:
1345 case SHADER_OPCODE_LOG2
:
1346 case SHADER_OPCODE_SIN
:
1347 case SHADER_OPCODE_COS
:
1348 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1349 if (devinfo
->gen
>= 7) {
1350 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1352 } else if (devinfo
->gen
== 6) {
1353 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1355 generate_math1_gen4(inst
, dst
, src
[0]);
1359 case SHADER_OPCODE_POW
:
1360 case SHADER_OPCODE_INT_QUOTIENT
:
1361 case SHADER_OPCODE_INT_REMAINDER
:
1362 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1363 if (devinfo
->gen
>= 7) {
1364 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1365 } else if (devinfo
->gen
== 6) {
1366 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1368 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1372 case SHADER_OPCODE_TEX
:
1373 case SHADER_OPCODE_TXD
:
1374 case SHADER_OPCODE_TXF
:
1375 case SHADER_OPCODE_TXF_CMS
:
1376 case SHADER_OPCODE_TXF_MCS
:
1377 case SHADER_OPCODE_TXL
:
1378 case SHADER_OPCODE_TXS
:
1379 case SHADER_OPCODE_TG4
:
1380 case SHADER_OPCODE_TG4_OFFSET
:
1381 generate_tex(inst
, dst
, src
[0], src
[1]);
1384 case VS_OPCODE_URB_WRITE
:
1385 generate_vs_urb_write(inst
);
1388 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1389 generate_scratch_read(inst
, dst
, src
[0]);
1392 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1393 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1396 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1397 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1400 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1401 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1404 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
1405 generate_set_simd4x2_header_gen9(inst
, dst
);
1408 case GS_OPCODE_URB_WRITE
:
1409 generate_gs_urb_write(inst
);
1412 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1413 generate_gs_urb_write_allocate(inst
);
1416 case GS_OPCODE_SVB_WRITE
:
1417 generate_gs_svb_write(inst
, dst
, src
[0], src
[1]);
1420 case GS_OPCODE_SVB_SET_DST_INDEX
:
1421 generate_gs_svb_set_destination_index(inst
, dst
, src
[0]);
1424 case GS_OPCODE_THREAD_END
:
1425 generate_gs_thread_end(inst
);
1428 case GS_OPCODE_SET_WRITE_OFFSET
:
1429 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1432 case GS_OPCODE_SET_VERTEX_COUNT
:
1433 generate_gs_set_vertex_count(dst
, src
[0]);
1436 case GS_OPCODE_FF_SYNC
:
1437 generate_gs_ff_sync(inst
, dst
, src
[0], src
[1]);
1440 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1441 generate_gs_ff_sync_set_primitives(dst
, src
[0], src
[1], src
[2]);
1444 case GS_OPCODE_SET_PRIMITIVE_ID
:
1445 generate_gs_set_primitive_id(dst
);
1448 case GS_OPCODE_SET_DWORD_2
:
1449 generate_gs_set_dword_2(dst
, src
[0]);
1452 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1453 generate_gs_prepare_channel_masks(dst
);
1456 case GS_OPCODE_SET_CHANNEL_MASKS
:
1457 generate_gs_set_channel_masks(dst
, src
[0]);
1460 case GS_OPCODE_GET_INSTANCE_ID
:
1461 generate_gs_get_instance_id(dst
);
1464 case SHADER_OPCODE_SHADER_TIME_ADD
:
1465 brw_shader_time_add(p
, src
[0],
1466 prog_data
->base
.binding_table
.shader_time_start
);
1467 brw_mark_surface_used(&prog_data
->base
,
1468 prog_data
->base
.binding_table
.shader_time_start
);
1471 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1472 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
&&
1473 src
[2].file
== BRW_IMMEDIATE_VALUE
);
1474 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].dw1
.ud
, inst
->mlen
,
1475 !inst
->dst
.is_null());
1476 brw_mark_surface_used(&prog_data
->base
, src
[1].dw1
.ud
);
1479 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1480 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
&&
1481 src
[2].file
== BRW_IMMEDIATE_VALUE
);
1482 brw_untyped_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1484 brw_mark_surface_used(&prog_data
->base
, src
[1].dw1
.ud
);
1487 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1488 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1489 brw_untyped_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1493 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1494 generate_unpack_flags(dst
);
1497 case VEC4_OPCODE_MOV_BYTES
: {
1498 /* Moves the low byte from each channel, using an Align1 access mode
1499 * and a <4,1,0> source region.
1501 assert(src
[0].type
== BRW_REGISTER_TYPE_UB
||
1502 src
[0].type
== BRW_REGISTER_TYPE_B
);
1504 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1505 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1506 src
[0].width
= BRW_WIDTH_1
;
1507 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1508 brw_MOV(p
, dst
, src
[0]);
1509 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1513 case VEC4_OPCODE_PACK_BYTES
: {
1516 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1518 * but destinations' only regioning is horizontal stride, so instead we
1519 * have to use two instructions:
1521 * mov(4) dst<1>:UB src<4,1,0>:UB
1522 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1524 * where they pack the four bytes from the low and high four DW.
1526 assert(is_power_of_two(dst
.dw1
.bits
.writemask
) &&
1527 dst
.dw1
.bits
.writemask
!= 0);
1528 unsigned offset
= __builtin_ctz(dst
.dw1
.bits
.writemask
);
1530 dst
.type
= BRW_REGISTER_TYPE_UB
;
1532 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1534 src
[0].type
= BRW_REGISTER_TYPE_UB
;
1535 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1536 src
[0].width
= BRW_WIDTH_1
;
1537 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1538 dst
.subnr
= offset
* 4;
1539 struct brw_inst
*insn
= brw_MOV(p
, dst
, src
[0]);
1540 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1541 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, true);
1542 brw_inst_set_no_dd_check(p
->devinfo
, insn
, inst
->no_dd_check
);
1545 dst
.subnr
= 16 + offset
* 4;
1546 insn
= brw_MOV(p
, dst
, src
[0]);
1547 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1548 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, inst
->no_dd_clear
);
1549 brw_inst_set_no_dd_check(p
->devinfo
, insn
, true);
1551 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1556 unreachable("Unsupported opcode");
1559 if (inst
->opcode
== VEC4_OPCODE_PACK_BYTES
) {
1560 /* Handled dependency hints in the generator. */
1562 assert(!inst
->conditional_mod
);
1563 } else if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1564 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1565 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1566 "emitting more than 1 instruction");
1568 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1570 if (inst
->conditional_mod
)
1571 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
1572 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
1573 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
1578 annotation_finalize(&annotation
, p
->next_insn_offset
);
1580 int before_size
= p
->next_insn_offset
;
1581 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1582 int after_size
= p
->next_insn_offset
;
1584 if (unlikely(debug_flag
)) {
1586 fprintf(stderr
, "Native code for %s %s shader %d:\n",
1587 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1588 stage_name
, shader_prog
->Name
);
1590 fprintf(stderr
, "Native code for %s program %d:\n", stage_name
,
1593 fprintf(stderr
, "%s vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1594 " bytes (%.0f%%)\n",
1596 before_size
/ 16, loop_count
, before_size
, after_size
,
1597 100.0f
* (before_size
- after_size
) / before_size
);
1599 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
1601 ralloc_free(annotation
.ann
);
1604 static GLuint msg_id
= 0;
1605 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
1606 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1607 MESA_DEBUG_TYPE_OTHER
,
1608 MESA_DEBUG_SEVERITY_NOTIFICATION
,
1609 "%s vec4 shader: %d inst, %d loops, "
1610 "compacted %d to %d bytes.\n",
1612 before_size
/ 16, loop_count
,
1613 before_size
, after_size
);
1617 vec4_generator::generate_assembly(const cfg_t
*cfg
,
1618 unsigned *assembly_size
)
1620 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1623 return brw_get_program(p
, assembly_size
);
1626 } /* namespace brw */