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i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 default:
96 unreachable("not reached");
97 }
98 break;
99
100 case UNIFORM:
101 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
102 (src[i].reg + src[i].reg_offset) / 2,
103 ((src[i].reg + src[i].reg_offset) % 2) * 4),
104 0, 4, 1);
105 brw_reg = retype(brw_reg, src[i].type);
106 brw_reg.dw1.bits.swizzle = src[i].swizzle;
107 if (src[i].abs)
108 brw_reg = brw_abs(brw_reg);
109 if (src[i].negate)
110 brw_reg = negate(brw_reg);
111
112 /* This should have been moved to pull constants. */
113 assert(!src[i].reladdr);
114 break;
115
116 case HW_REG:
117 assert(src[i].type == src[i].fixed_hw_reg.type);
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 unreachable("not reached");
128 }
129
130 return brw_reg;
131 }
132
133 vec4_generator::vec4_generator(struct brw_context *brw,
134 struct gl_shader_program *shader_prog,
135 struct gl_program *prog,
136 struct brw_vec4_prog_data *prog_data,
137 void *mem_ctx,
138 bool debug_flag)
139 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
140 mem_ctx(mem_ctx), debug_flag(debug_flag)
141 {
142 p = rzalloc(mem_ctx, struct brw_compile);
143 brw_init_compile(brw, p, mem_ctx);
144 }
145
146 vec4_generator::~vec4_generator()
147 {
148 }
149
150 void
151 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
152 struct brw_reg dst,
153 struct brw_reg src)
154 {
155 gen4_math(p,
156 dst,
157 brw_math_function(inst->opcode),
158 inst->base_mrf,
159 src,
160 BRW_MATH_DATA_VECTOR,
161 BRW_MATH_PRECISION_FULL);
162 }
163
164 static void
165 check_gen6_math_src_arg(struct brw_reg src)
166 {
167 /* Source swizzles are ignored. */
168 assert(!src.abs);
169 assert(!src.negate);
170 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
171 }
172
173 void
174 vec4_generator::generate_math_gen6(vec4_instruction *inst,
175 struct brw_reg dst,
176 struct brw_reg src0,
177 struct brw_reg src1)
178 {
179 /* Can't do writemask because math can't be align16. */
180 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0);
183 if (src1.file == BRW_GENERAL_REGISTER_FILE)
184 check_gen6_math_src_arg(src1);
185
186 brw_set_default_access_mode(p, BRW_ALIGN_1);
187 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
188 brw_set_default_access_mode(p, BRW_ALIGN_16);
189 }
190
191 void
192 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
193 struct brw_reg dst,
194 struct brw_reg src0,
195 struct brw_reg src1)
196 {
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
198 * "Message Payload":
199 *
200 * "Operand0[7]. For the INT DIV functions, this operand is the
201 * denominator."
202 * ...
203 * "Operand1[7]. For the INT DIV functions, this operand is the
204 * numerator."
205 */
206 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
207 struct brw_reg &op0 = is_int_div ? src1 : src0;
208 struct brw_reg &op1 = is_int_div ? src0 : src1;
209
210 brw_push_insn_state(p);
211 brw_set_default_saturate(p, false);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
214 brw_pop_insn_state(p);
215
216 gen4_math(p,
217 dst,
218 brw_math_function(inst->opcode),
219 inst->base_mrf,
220 op0,
221 BRW_MATH_DATA_VECTOR,
222 BRW_MATH_PRECISION_FULL);
223 }
224
225 void
226 vec4_generator::generate_tex(vec4_instruction *inst,
227 struct brw_reg dst,
228 struct brw_reg src,
229 struct brw_reg sampler_index)
230 {
231 int msg_type = -1;
232
233 if (brw->gen >= 5) {
234 switch (inst->opcode) {
235 case SHADER_OPCODE_TEX:
236 case SHADER_OPCODE_TXL:
237 if (inst->shadow_compare) {
238 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
239 } else {
240 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
241 }
242 break;
243 case SHADER_OPCODE_TXD:
244 if (inst->shadow_compare) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw->gen >= 8 || brw->is_haswell);
247 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
248 } else {
249 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
250 }
251 break;
252 case SHADER_OPCODE_TXF:
253 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
254 break;
255 case SHADER_OPCODE_TXF_CMS:
256 if (brw->gen >= 7)
257 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
258 else
259 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
260 break;
261 case SHADER_OPCODE_TXF_MCS:
262 assert(brw->gen >= 7);
263 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
264 break;
265 case SHADER_OPCODE_TXS:
266 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
267 break;
268 case SHADER_OPCODE_TG4:
269 if (inst->shadow_compare) {
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
271 } else {
272 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
273 }
274 break;
275 case SHADER_OPCODE_TG4_OFFSET:
276 if (inst->shadow_compare) {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
278 } else {
279 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
280 }
281 break;
282 default:
283 unreachable("should not get here: invalid vec4 texture opcode");
284 }
285 } else {
286 switch (inst->opcode) {
287 case SHADER_OPCODE_TEX:
288 case SHADER_OPCODE_TXL:
289 if (inst->shadow_compare) {
290 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
291 assert(inst->mlen == 3);
292 } else {
293 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
294 assert(inst->mlen == 2);
295 }
296 break;
297 case SHADER_OPCODE_TXD:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
300 assert(inst->mlen == 4);
301 break;
302 case SHADER_OPCODE_TXF:
303 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
304 assert(inst->mlen == 2);
305 break;
306 case SHADER_OPCODE_TXS:
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
308 assert(inst->mlen == 2);
309 break;
310 default:
311 unreachable("should not get here: invalid vec4 texture opcode");
312 }
313 }
314
315 assert(msg_type != -1);
316
317 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
318
319 /* Load the message header if present. If there's a texture offset, we need
320 * to set it up explicitly and load the offset bitfield. Otherwise, we can
321 * use an implied move from g0 to the first message register.
322 */
323 if (inst->header_present) {
324 if (brw->gen < 6 && !inst->texture_offset) {
325 /* Set up an implied move from g0 to the MRF. */
326 src = brw_vec8_grf(0, 0);
327 } else {
328 struct brw_reg header =
329 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
330
331 /* Explicitly set up the message header by copying g0 to the MRF. */
332 brw_push_insn_state(p);
333 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
334 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
335
336 brw_set_default_access_mode(p, BRW_ALIGN_1);
337
338 if (inst->texture_offset) {
339 /* Set the texel offset bits in DWord 2. */
340 brw_MOV(p, get_element_ud(header, 2),
341 brw_imm_ud(inst->texture_offset));
342 }
343
344 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
345 brw_pop_insn_state(p);
346 }
347 }
348
349 uint32_t return_format;
350
351 switch (dst.type) {
352 case BRW_REGISTER_TYPE_D:
353 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
354 break;
355 case BRW_REGISTER_TYPE_UD:
356 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
357 break;
358 default:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
360 break;
361 }
362
363 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
364 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
365 ? prog_data->base.binding_table.gather_texture_start
366 : prog_data->base.binding_table.texture_start;
367
368 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
369 uint32_t sampler = sampler_index.dw1.ud;
370
371 brw_SAMPLE(p,
372 dst,
373 inst->base_mrf,
374 src,
375 sampler + base_binding_table_index,
376 sampler % 16,
377 msg_type,
378 1, /* response length */
379 inst->mlen,
380 inst->header_present,
381 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
382 return_format);
383
384 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
385 } else {
386 /* Non-constant sampler index. */
387 /* Note: this clobbers `dst` as a temporary before emitting the send */
388
389 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
390 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
391
392 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
393
394 brw_push_insn_state(p);
395 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
396 brw_set_default_access_mode(p, BRW_ALIGN_1);
397
398 /* Some care required: `sampler` and `temp` may alias:
399 * addr = sampler & 0xff
400 * temp = (sampler << 8) & 0xf00
401 * addr = addr | temp
402 */
403 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
404 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
405 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
406 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
407 brw_OR(p, addr, addr, temp);
408
409 /* a0.0 |= <descriptor> */
410 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
411 brw_set_sampler_message(p, insn_or,
412 0 /* surface */,
413 0 /* sampler */,
414 msg_type,
415 1 /* rlen */,
416 inst->mlen /* mlen */,
417 inst->header_present /* header */,
418 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
419 return_format);
420 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
421 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
422 brw_set_src0(p, insn_or, addr);
423 brw_set_dest(p, insn_or, addr);
424
425
426 /* dst = send(offset, a0.0) */
427 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
428 brw_set_dest(p, insn_send, dst);
429 brw_set_src0(p, insn_send, src);
430 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
431
432 brw_pop_insn_state(p);
433
434 /* visitor knows more than we do about the surface limit required,
435 * so has already done marking.
436 */
437 }
438 }
439
440 void
441 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
442 {
443 brw_urb_WRITE(p,
444 brw_null_reg(), /* dest */
445 inst->base_mrf, /* starting mrf reg nr */
446 brw_vec8_grf(0, 0), /* src */
447 inst->urb_write_flags,
448 inst->mlen,
449 0, /* response len */
450 inst->offset, /* urb destination offset */
451 BRW_URB_SWIZZLE_INTERLEAVE);
452 }
453
454 void
455 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
456 {
457 struct brw_reg src = brw_message_reg(inst->base_mrf);
458 brw_urb_WRITE(p,
459 brw_null_reg(), /* dest */
460 inst->base_mrf, /* starting mrf reg nr */
461 src,
462 inst->urb_write_flags,
463 inst->mlen,
464 0, /* response len */
465 inst->offset, /* urb destination offset */
466 BRW_URB_SWIZZLE_INTERLEAVE);
467 }
468
469 void
470 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
471 {
472 struct brw_reg src = brw_message_reg(inst->base_mrf);
473
474 /* We pass the temporary passed in src0 as the writeback register */
475 brw_urb_WRITE(p,
476 inst->get_src(this->prog_data, 0), /* dest */
477 inst->base_mrf, /* starting mrf reg nr */
478 src,
479 BRW_URB_WRITE_ALLOCATE_COMPLETE,
480 inst->mlen,
481 1, /* response len */
482 inst->offset, /* urb destination offset */
483 BRW_URB_SWIZZLE_INTERLEAVE);
484
485 /* Now put allocated urb handle in dst.0 */
486 brw_push_insn_state(p);
487 brw_set_default_access_mode(p, BRW_ALIGN_1);
488 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
489 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
490 get_element_ud(inst->get_src(this->prog_data, 0), 0));
491 brw_set_default_access_mode(p, BRW_ALIGN_16);
492 brw_pop_insn_state(p);
493 }
494
495 void
496 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
497 {
498 struct brw_reg src = brw_message_reg(inst->base_mrf);
499 brw_urb_WRITE(p,
500 brw_null_reg(), /* dest */
501 inst->base_mrf, /* starting mrf reg nr */
502 src,
503 BRW_URB_WRITE_EOT,
504 brw->gen >= 8 ? 2 : 1,/* message len */
505 0, /* response len */
506 0, /* urb destination offset */
507 BRW_URB_SWIZZLE_INTERLEAVE);
508 }
509
510 void
511 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
512 struct brw_reg src0,
513 struct brw_reg src1)
514 {
515 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
516 * Header: M0.3):
517 *
518 * Slot 0 Offset. This field, after adding to the Global Offset field
519 * in the message descriptor, specifies the offset (in 256-bit units)
520 * from the start of the URB entry, as referenced by URB Handle 0, at
521 * which the data will be accessed.
522 *
523 * Similar text describes DWORD M0.4, which is slot 1 offset.
524 *
525 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
526 * of the register for geometry shader invocations 0 and 1) by the
527 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
528 *
529 * We can do this with the following EU instruction:
530 *
531 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
532 */
533 brw_push_insn_state(p);
534 brw_set_default_access_mode(p, BRW_ALIGN_1);
535 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
536 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
537 src1);
538 brw_set_default_access_mode(p, BRW_ALIGN_16);
539 brw_pop_insn_state(p);
540 }
541
542 void
543 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
544 struct brw_reg src)
545 {
546 brw_push_insn_state(p);
547 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
548
549 if (brw->gen >= 8) {
550 /* Move the vertex count into the second MRF for the EOT write. */
551 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
552 src);
553 } else {
554 /* If we think of the src and dst registers as composed of 8 DWORDs each,
555 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
556 * them to WORDs, and then pack them into DWORD 2 of dst.
557 *
558 * It's easier to get the EU to do this if we think of the src and dst
559 * registers as composed of 16 WORDS each; then, we want to pick up the
560 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
561 * of dst.
562 *
563 * We can do that by the following EU instruction:
564 *
565 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
566 */
567 brw_set_default_access_mode(p, BRW_ALIGN_1);
568 brw_MOV(p,
569 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
570 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
571 brw_set_default_access_mode(p, BRW_ALIGN_16);
572 }
573 brw_pop_insn_state(p);
574 }
575
576 void
577 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
578 struct brw_reg src)
579 {
580 assert(src.file == BRW_IMMEDIATE_VALUE);
581
582 brw_push_insn_state(p);
583 brw_set_default_access_mode(p, BRW_ALIGN_1);
584 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
585 brw_MOV(p, suboffset(vec1(dst), 2), src);
586 brw_set_default_access_mode(p, BRW_ALIGN_16);
587 brw_pop_insn_state(p);
588 }
589
590 void
591 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
592 {
593 /* We want to left shift just DWORD 4 (the x component belonging to the
594 * second geometry shader invocation) by 4 bits. So generate the
595 * instruction:
596 *
597 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
598 */
599 dst = suboffset(vec1(dst), 4);
600 brw_push_insn_state(p);
601 brw_set_default_access_mode(p, BRW_ALIGN_1);
602 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
603 brw_SHL(p, dst, dst, brw_imm_ud(4));
604 brw_pop_insn_state(p);
605 }
606
607 void
608 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
609 struct brw_reg src)
610 {
611 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
612 * Header: M0.5):
613 *
614 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
615 *
616 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
617 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
618 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
619 * channel enable to determine the final channel enable. For the
620 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
621 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
622 * in the writeback message. For the URB_WRITE_OWORD &
623 * URB_WRITE_HWORD messages, when final channel enable is 1 it
624 * indicates that Vertex 1 DATA [3] will be written to the surface.
625 *
626 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
627 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
628 *
629 * 14 Vertex 1 DATA [2] Channel Mask
630 * 13 Vertex 1 DATA [1] Channel Mask
631 * 12 Vertex 1 DATA [0] Channel Mask
632 * 11 Vertex 0 DATA [3] Channel Mask
633 * 10 Vertex 0 DATA [2] Channel Mask
634 * 9 Vertex 0 DATA [1] Channel Mask
635 * 8 Vertex 0 DATA [0] Channel Mask
636 *
637 * (This is from a section of the PRM that is agnostic to the particular
638 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
639 * geometry shader invocations 0 and 1, respectively). Since we have the
640 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
641 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
642 * DWORD 4, we just need to OR them together and store the result in bits
643 * 15:8 of DWORD 5.
644 *
645 * It's easier to get the EU to do this if we think of the src and dst
646 * registers as composed of 32 bytes each; then, we want to pick up the
647 * contents of bytes 0 and 16 from src, OR them together, and store them in
648 * byte 21.
649 *
650 * We can do that by the following EU instruction:
651 *
652 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
653 *
654 * Note: this relies on the source register having zeros in (a) bits 7:4 of
655 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
656 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
657 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
658 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
659 * contain valid channel mask values (which are in the range 0x0-0xf).
660 */
661 dst = retype(dst, BRW_REGISTER_TYPE_UB);
662 src = retype(src, BRW_REGISTER_TYPE_UB);
663 brw_push_insn_state(p);
664 brw_set_default_access_mode(p, BRW_ALIGN_1);
665 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
666 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
667 brw_pop_insn_state(p);
668 }
669
670 void
671 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
672 {
673 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
674 * and store into dst.0 & dst.4. So generate the instruction:
675 *
676 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
677 */
678 brw_push_insn_state(p);
679 brw_set_default_access_mode(p, BRW_ALIGN_1);
680 dst = retype(dst, BRW_REGISTER_TYPE_UD);
681 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
682 brw_SHR(p, dst, stride(r0, 1, 4, 0),
683 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
684 brw_pop_insn_state(p);
685 }
686
687 void
688 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
689 struct brw_reg dst,
690 struct brw_reg src0)
691 {
692 /* This opcode uses an implied MRF register for:
693 * - the header of the ff_sync message. And as such it is expected to be
694 * initialized to r0 before calling here.
695 * - the destination where we will write the allocated URB handle.
696 */
697 struct brw_reg header =
698 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
699
700 /* Overwrite dword 0 of the header (cleared for now since we are not doing
701 * transform feedback) and dword 1 (to hold the number of primitives
702 * written).
703 */
704 brw_push_insn_state(p);
705 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
706 brw_set_default_access_mode(p, BRW_ALIGN_1);
707 brw_MOV(p, get_element_ud(header, 0), brw_imm_ud(0));
708 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
709 brw_pop_insn_state(p);
710
711 /* Allocate URB handle in dst */
712 brw_ff_sync(p,
713 dst,
714 0,
715 header,
716 1, /* allocate */
717 1, /* response length */
718 0 /* eot */);
719
720 /* Now put allocated urb handle in header.0 */
721 brw_push_insn_state(p);
722 brw_set_default_access_mode(p, BRW_ALIGN_1);
723 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
724 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
725 brw_pop_insn_state(p);
726 }
727
728 void
729 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
730 struct brw_reg index)
731 {
732 int second_vertex_offset;
733
734 if (brw->gen >= 6)
735 second_vertex_offset = 1;
736 else
737 second_vertex_offset = 16;
738
739 m1 = retype(m1, BRW_REGISTER_TYPE_D);
740
741 /* Set up M1 (message payload). Only the block offsets in M1.0 and
742 * M1.4 are used, and the rest are ignored.
743 */
744 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
745 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
746 struct brw_reg index_0 = suboffset(vec1(index), 0);
747 struct brw_reg index_4 = suboffset(vec1(index), 4);
748
749 brw_push_insn_state(p);
750 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
751 brw_set_default_access_mode(p, BRW_ALIGN_1);
752
753 brw_MOV(p, m1_0, index_0);
754
755 if (index.file == BRW_IMMEDIATE_VALUE) {
756 index_4.dw1.ud += second_vertex_offset;
757 brw_MOV(p, m1_4, index_4);
758 } else {
759 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
760 }
761
762 brw_pop_insn_state(p);
763 }
764
765 void
766 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
767 struct brw_reg dst)
768 {
769 brw_push_insn_state(p);
770 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
771 brw_set_default_access_mode(p, BRW_ALIGN_1);
772
773 struct brw_reg flags = brw_flag_reg(0, 0);
774 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
775 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
776
777 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
778 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
779 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
780
781 brw_pop_insn_state(p);
782 }
783
784 void
785 vec4_generator::generate_scratch_read(vec4_instruction *inst,
786 struct brw_reg dst,
787 struct brw_reg index)
788 {
789 struct brw_reg header = brw_vec8_grf(0, 0);
790
791 gen6_resolve_implied_move(p, &header, inst->base_mrf);
792
793 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
794 index);
795
796 uint32_t msg_type;
797
798 if (brw->gen >= 6)
799 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
800 else if (brw->gen == 5 || brw->is_g4x)
801 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
802 else
803 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
804
805 /* Each of the 8 channel enables is considered for whether each
806 * dword is written.
807 */
808 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
809 brw_set_dest(p, send, dst);
810 brw_set_src0(p, send, header);
811 if (brw->gen < 6)
812 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
813 brw_set_dp_read_message(p, send,
814 255, /* binding table index: stateless access */
815 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
816 msg_type,
817 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
818 2, /* mlen */
819 true, /* header_present */
820 1 /* rlen */);
821 }
822
823 void
824 vec4_generator::generate_scratch_write(vec4_instruction *inst,
825 struct brw_reg dst,
826 struct brw_reg src,
827 struct brw_reg index)
828 {
829 struct brw_reg header = brw_vec8_grf(0, 0);
830 bool write_commit;
831
832 /* If the instruction is predicated, we'll predicate the send, not
833 * the header setup.
834 */
835 brw_set_default_predicate_control(p, false);
836
837 gen6_resolve_implied_move(p, &header, inst->base_mrf);
838
839 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
840 index);
841
842 brw_MOV(p,
843 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
844 retype(src, BRW_REGISTER_TYPE_D));
845
846 uint32_t msg_type;
847
848 if (brw->gen >= 7)
849 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
850 else if (brw->gen == 6)
851 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
852 else
853 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
854
855 brw_set_default_predicate_control(p, inst->predicate);
856
857 /* Pre-gen6, we have to specify write commits to ensure ordering
858 * between reads and writes within a thread. Afterwards, that's
859 * guaranteed and write commits only matter for inter-thread
860 * synchronization.
861 */
862 if (brw->gen >= 6) {
863 write_commit = false;
864 } else {
865 /* The visitor set up our destination register to be g0. This
866 * means that when the next read comes along, we will end up
867 * reading from g0 and causing a block on the write commit. For
868 * write-after-read, we are relying on the value of the previous
869 * read being used (and thus blocking on completion) before our
870 * write is executed. This means we have to be careful in
871 * instruction scheduling to not violate this assumption.
872 */
873 write_commit = true;
874 }
875
876 /* Each of the 8 channel enables is considered for whether each
877 * dword is written.
878 */
879 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
880 brw_set_dest(p, send, dst);
881 brw_set_src0(p, send, header);
882 if (brw->gen < 6)
883 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
884 brw_set_dp_write_message(p, send,
885 255, /* binding table index: stateless access */
886 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
887 msg_type,
888 3, /* mlen */
889 true, /* header present */
890 false, /* not a render target write */
891 write_commit, /* rlen */
892 false, /* eot */
893 write_commit);
894 }
895
896 void
897 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
898 struct brw_reg dst,
899 struct brw_reg index,
900 struct brw_reg offset)
901 {
902 assert(index.file == BRW_IMMEDIATE_VALUE &&
903 index.type == BRW_REGISTER_TYPE_UD);
904 uint32_t surf_index = index.dw1.ud;
905
906 struct brw_reg header = brw_vec8_grf(0, 0);
907
908 gen6_resolve_implied_move(p, &header, inst->base_mrf);
909
910 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
911 offset);
912
913 uint32_t msg_type;
914
915 if (brw->gen >= 6)
916 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
917 else if (brw->gen == 5 || brw->is_g4x)
918 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
919 else
920 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
921
922 /* Each of the 8 channel enables is considered for whether each
923 * dword is written.
924 */
925 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
926 brw_set_dest(p, send, dst);
927 brw_set_src0(p, send, header);
928 if (brw->gen < 6)
929 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
930 brw_set_dp_read_message(p, send,
931 surf_index,
932 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
933 msg_type,
934 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
935 2, /* mlen */
936 true, /* header_present */
937 1 /* rlen */);
938
939 brw_mark_surface_used(&prog_data->base, surf_index);
940 }
941
942 void
943 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
944 struct brw_reg dst,
945 struct brw_reg surf_index,
946 struct brw_reg offset)
947 {
948 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
949
950 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
951
952 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
953 brw_set_dest(p, insn, dst);
954 brw_set_src0(p, insn, offset);
955 brw_set_sampler_message(p, insn,
956 surf_index.dw1.ud,
957 0, /* LD message ignores sampler unit */
958 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
959 1, /* rlen */
960 1, /* mlen */
961 false, /* no header */
962 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
963 0);
964
965 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
966
967 } else {
968
969 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
970
971 brw_push_insn_state(p);
972 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
973 brw_set_default_access_mode(p, BRW_ALIGN_1);
974
975 /* a0.0 = surf_index & 0xff */
976 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
977 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
978 brw_set_dest(p, insn_and, addr);
979 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
980 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
981
982
983 /* a0.0 |= <descriptor> */
984 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
985 brw_set_sampler_message(p, insn_or,
986 0 /* surface */,
987 0 /* sampler */,
988 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
989 1 /* rlen */,
990 1 /* mlen */,
991 false /* header */,
992 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
993 0);
994 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
995 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
996 brw_set_src0(p, insn_or, addr);
997 brw_set_dest(p, insn_or, addr);
998
999
1000 /* dst = send(offset, a0.0) */
1001 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1002 brw_set_dest(p, insn_send, dst);
1003 brw_set_src0(p, insn_send, offset);
1004 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1005
1006 brw_pop_insn_state(p);
1007
1008 /* visitor knows more than we do about the surface limit required,
1009 * so has already done marking.
1010 */
1011 }
1012 }
1013
1014 void
1015 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1016 struct brw_reg dst,
1017 struct brw_reg atomic_op,
1018 struct brw_reg surf_index)
1019 {
1020 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1021 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1022 surf_index.file == BRW_IMMEDIATE_VALUE &&
1023 surf_index.type == BRW_REGISTER_TYPE_UD);
1024
1025 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1026 atomic_op.dw1.ud, surf_index.dw1.ud,
1027 inst->mlen, 1);
1028
1029 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1030 }
1031
1032 void
1033 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1034 struct brw_reg dst,
1035 struct brw_reg surf_index)
1036 {
1037 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1038 surf_index.type == BRW_REGISTER_TYPE_UD);
1039
1040 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1041 surf_index.dw1.ud,
1042 inst->mlen, 1);
1043
1044 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1045 }
1046
1047 void
1048 vec4_generator::generate_code(const cfg_t *cfg)
1049 {
1050 struct annotation_info annotation;
1051 memset(&annotation, 0, sizeof(annotation));
1052 int loop_count = 0;
1053
1054 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1055 struct brw_reg src[3], dst;
1056
1057 if (unlikely(debug_flag))
1058 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1059
1060 for (unsigned int i = 0; i < 3; i++) {
1061 src[i] = inst->get_src(this->prog_data, i);
1062 }
1063 dst = inst->get_dst();
1064
1065 brw_set_default_predicate_control(p, inst->predicate);
1066 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1067 brw_set_default_saturate(p, inst->saturate);
1068 brw_set_default_mask_control(p, inst->force_writemask_all);
1069 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1070
1071 unsigned pre_emit_nr_insn = p->nr_insn;
1072
1073 if (dst.width == BRW_WIDTH_4) {
1074 /* This happens in attribute fixups for "dual instanced" geometry
1075 * shaders, since they use attributes that are vec4's. Since the exec
1076 * width is only 4, it's essential that the caller set
1077 * force_writemask_all in order to make sure the instruction is executed
1078 * regardless of which channels are enabled.
1079 */
1080 assert(inst->force_writemask_all);
1081
1082 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1083 * the following register region restrictions (from Graphics BSpec:
1084 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1085 * > Register Region Restrictions)
1086 *
1087 * 1. ExecSize must be greater than or equal to Width.
1088 *
1089 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1090 * to Width * HorzStride."
1091 */
1092 for (int i = 0; i < 3; i++) {
1093 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1094 src[i] = stride(src[i], 4, 4, 1);
1095 }
1096 }
1097
1098 switch (inst->opcode) {
1099 case BRW_OPCODE_MOV:
1100 brw_MOV(p, dst, src[0]);
1101 break;
1102 case BRW_OPCODE_ADD:
1103 brw_ADD(p, dst, src[0], src[1]);
1104 break;
1105 case BRW_OPCODE_MUL:
1106 brw_MUL(p, dst, src[0], src[1]);
1107 break;
1108 case BRW_OPCODE_MACH:
1109 brw_MACH(p, dst, src[0], src[1]);
1110 break;
1111
1112 case BRW_OPCODE_MAD:
1113 assert(brw->gen >= 6);
1114 brw_MAD(p, dst, src[0], src[1], src[2]);
1115 break;
1116
1117 case BRW_OPCODE_FRC:
1118 brw_FRC(p, dst, src[0]);
1119 break;
1120 case BRW_OPCODE_RNDD:
1121 brw_RNDD(p, dst, src[0]);
1122 break;
1123 case BRW_OPCODE_RNDE:
1124 brw_RNDE(p, dst, src[0]);
1125 break;
1126 case BRW_OPCODE_RNDZ:
1127 brw_RNDZ(p, dst, src[0]);
1128 break;
1129
1130 case BRW_OPCODE_AND:
1131 brw_AND(p, dst, src[0], src[1]);
1132 break;
1133 case BRW_OPCODE_OR:
1134 brw_OR(p, dst, src[0], src[1]);
1135 break;
1136 case BRW_OPCODE_XOR:
1137 brw_XOR(p, dst, src[0], src[1]);
1138 break;
1139 case BRW_OPCODE_NOT:
1140 brw_NOT(p, dst, src[0]);
1141 break;
1142 case BRW_OPCODE_ASR:
1143 brw_ASR(p, dst, src[0], src[1]);
1144 break;
1145 case BRW_OPCODE_SHR:
1146 brw_SHR(p, dst, src[0], src[1]);
1147 break;
1148 case BRW_OPCODE_SHL:
1149 brw_SHL(p, dst, src[0], src[1]);
1150 break;
1151
1152 case BRW_OPCODE_CMP:
1153 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1154 break;
1155 case BRW_OPCODE_SEL:
1156 brw_SEL(p, dst, src[0], src[1]);
1157 break;
1158
1159 case BRW_OPCODE_DPH:
1160 brw_DPH(p, dst, src[0], src[1]);
1161 break;
1162
1163 case BRW_OPCODE_DP4:
1164 brw_DP4(p, dst, src[0], src[1]);
1165 break;
1166
1167 case BRW_OPCODE_DP3:
1168 brw_DP3(p, dst, src[0], src[1]);
1169 break;
1170
1171 case BRW_OPCODE_DP2:
1172 brw_DP2(p, dst, src[0], src[1]);
1173 break;
1174
1175 case BRW_OPCODE_F32TO16:
1176 assert(brw->gen >= 7);
1177 brw_F32TO16(p, dst, src[0]);
1178 break;
1179
1180 case BRW_OPCODE_F16TO32:
1181 assert(brw->gen >= 7);
1182 brw_F16TO32(p, dst, src[0]);
1183 break;
1184
1185 case BRW_OPCODE_LRP:
1186 assert(brw->gen >= 6);
1187 brw_LRP(p, dst, src[0], src[1], src[2]);
1188 break;
1189
1190 case BRW_OPCODE_BFREV:
1191 assert(brw->gen >= 7);
1192 /* BFREV only supports UD type for src and dst. */
1193 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1194 retype(src[0], BRW_REGISTER_TYPE_UD));
1195 break;
1196 case BRW_OPCODE_FBH:
1197 assert(brw->gen >= 7);
1198 /* FBH only supports UD type for dst. */
1199 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1200 break;
1201 case BRW_OPCODE_FBL:
1202 assert(brw->gen >= 7);
1203 /* FBL only supports UD type for dst. */
1204 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1205 break;
1206 case BRW_OPCODE_CBIT:
1207 assert(brw->gen >= 7);
1208 /* CBIT only supports UD type for dst. */
1209 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1210 break;
1211 case BRW_OPCODE_ADDC:
1212 assert(brw->gen >= 7);
1213 brw_ADDC(p, dst, src[0], src[1]);
1214 break;
1215 case BRW_OPCODE_SUBB:
1216 assert(brw->gen >= 7);
1217 brw_SUBB(p, dst, src[0], src[1]);
1218 break;
1219 case BRW_OPCODE_MAC:
1220 brw_MAC(p, dst, src[0], src[1]);
1221 break;
1222
1223 case BRW_OPCODE_BFE:
1224 assert(brw->gen >= 7);
1225 brw_BFE(p, dst, src[0], src[1], src[2]);
1226 break;
1227
1228 case BRW_OPCODE_BFI1:
1229 assert(brw->gen >= 7);
1230 brw_BFI1(p, dst, src[0], src[1]);
1231 break;
1232 case BRW_OPCODE_BFI2:
1233 assert(brw->gen >= 7);
1234 brw_BFI2(p, dst, src[0], src[1], src[2]);
1235 break;
1236
1237 case BRW_OPCODE_IF:
1238 if (inst->src[0].file != BAD_FILE) {
1239 /* The instruction has an embedded compare (only allowed on gen6) */
1240 assert(brw->gen == 6);
1241 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1242 } else {
1243 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1244 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1245 }
1246 break;
1247
1248 case BRW_OPCODE_ELSE:
1249 brw_ELSE(p);
1250 break;
1251 case BRW_OPCODE_ENDIF:
1252 brw_ENDIF(p);
1253 break;
1254
1255 case BRW_OPCODE_DO:
1256 brw_DO(p, BRW_EXECUTE_8);
1257 break;
1258
1259 case BRW_OPCODE_BREAK:
1260 brw_BREAK(p);
1261 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1262 break;
1263 case BRW_OPCODE_CONTINUE:
1264 brw_CONT(p);
1265 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1266 break;
1267
1268 case BRW_OPCODE_WHILE:
1269 brw_WHILE(p);
1270 loop_count++;
1271 break;
1272
1273 case SHADER_OPCODE_RCP:
1274 case SHADER_OPCODE_RSQ:
1275 case SHADER_OPCODE_SQRT:
1276 case SHADER_OPCODE_EXP2:
1277 case SHADER_OPCODE_LOG2:
1278 case SHADER_OPCODE_SIN:
1279 case SHADER_OPCODE_COS:
1280 if (brw->gen >= 7) {
1281 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1282 brw_null_reg());
1283 } else if (brw->gen == 6) {
1284 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1285 } else {
1286 generate_math1_gen4(inst, dst, src[0]);
1287 }
1288 break;
1289
1290 case SHADER_OPCODE_POW:
1291 case SHADER_OPCODE_INT_QUOTIENT:
1292 case SHADER_OPCODE_INT_REMAINDER:
1293 if (brw->gen >= 7) {
1294 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1295 } else if (brw->gen == 6) {
1296 generate_math_gen6(inst, dst, src[0], src[1]);
1297 } else {
1298 generate_math2_gen4(inst, dst, src[0], src[1]);
1299 }
1300 break;
1301
1302 case SHADER_OPCODE_TEX:
1303 case SHADER_OPCODE_TXD:
1304 case SHADER_OPCODE_TXF:
1305 case SHADER_OPCODE_TXF_CMS:
1306 case SHADER_OPCODE_TXF_MCS:
1307 case SHADER_OPCODE_TXL:
1308 case SHADER_OPCODE_TXS:
1309 case SHADER_OPCODE_TG4:
1310 case SHADER_OPCODE_TG4_OFFSET:
1311 generate_tex(inst, dst, src[0], src[1]);
1312 break;
1313
1314 case VS_OPCODE_URB_WRITE:
1315 generate_vs_urb_write(inst);
1316 break;
1317
1318 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1319 generate_scratch_read(inst, dst, src[0]);
1320 break;
1321
1322 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1323 generate_scratch_write(inst, dst, src[0], src[1]);
1324 break;
1325
1326 case VS_OPCODE_PULL_CONSTANT_LOAD:
1327 generate_pull_constant_load(inst, dst, src[0], src[1]);
1328 break;
1329
1330 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1331 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1332 break;
1333
1334 case GS_OPCODE_URB_WRITE:
1335 generate_gs_urb_write(inst);
1336 break;
1337
1338 case GS_OPCODE_URB_WRITE_ALLOCATE:
1339 generate_gs_urb_write_allocate(inst);
1340 break;
1341
1342 case GS_OPCODE_THREAD_END:
1343 generate_gs_thread_end(inst);
1344 break;
1345
1346 case GS_OPCODE_SET_WRITE_OFFSET:
1347 generate_gs_set_write_offset(dst, src[0], src[1]);
1348 break;
1349
1350 case GS_OPCODE_SET_VERTEX_COUNT:
1351 generate_gs_set_vertex_count(dst, src[0]);
1352 break;
1353
1354 case GS_OPCODE_FF_SYNC:
1355 generate_gs_ff_sync(inst, dst, src[0]);
1356 break;
1357
1358 case GS_OPCODE_SET_DWORD_2_IMMED:
1359 generate_gs_set_dword_2_immed(dst, src[0]);
1360 break;
1361
1362 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1363 generate_gs_prepare_channel_masks(dst);
1364 break;
1365
1366 case GS_OPCODE_SET_CHANNEL_MASKS:
1367 generate_gs_set_channel_masks(dst, src[0]);
1368 break;
1369
1370 case GS_OPCODE_GET_INSTANCE_ID:
1371 generate_gs_get_instance_id(dst);
1372 break;
1373
1374 case SHADER_OPCODE_SHADER_TIME_ADD:
1375 brw_shader_time_add(p, src[0],
1376 prog_data->base.binding_table.shader_time_start);
1377 brw_mark_surface_used(&prog_data->base,
1378 prog_data->base.binding_table.shader_time_start);
1379 break;
1380
1381 case SHADER_OPCODE_UNTYPED_ATOMIC:
1382 generate_untyped_atomic(inst, dst, src[0], src[1]);
1383 break;
1384
1385 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1386 generate_untyped_surface_read(inst, dst, src[0]);
1387 break;
1388
1389 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1390 generate_unpack_flags(inst, dst);
1391 break;
1392
1393 default:
1394 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1395 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1396 opcode_descs[inst->opcode].name);
1397 } else {
1398 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1399 }
1400 abort();
1401 }
1402
1403 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1404 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1405 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1406 "emitting more than 1 instruction");
1407
1408 brw_inst *last = &p->store[pre_emit_nr_insn];
1409
1410 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1411 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1412 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1413 }
1414 }
1415
1416 brw_set_uip_jip(p);
1417 annotation_finalize(&annotation, p->next_insn_offset);
1418
1419 int before_size = p->next_insn_offset;
1420 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1421 int after_size = p->next_insn_offset;
1422
1423 if (unlikely(debug_flag)) {
1424 if (shader_prog) {
1425 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1426 shader_prog->Label ? shader_prog->Label : "unnamed",
1427 shader_prog->Name);
1428 } else {
1429 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1430 }
1431 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1432 " bytes (%.0f%%)\n",
1433 before_size / 16, loop_count, before_size, after_size,
1434 100.0f * (before_size - after_size) / before_size);
1435
1436 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1437 ralloc_free(annotation.ann);
1438 }
1439 }
1440
1441 const unsigned *
1442 vec4_generator::generate_assembly(const cfg_t *cfg,
1443 unsigned *assembly_size)
1444 {
1445 brw_set_default_access_mode(p, BRW_ALIGN_16);
1446 generate_code(cfg);
1447
1448 return brw_get_program(p, assembly_size);
1449 }
1450
1451 } /* namespace brw */