1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 unreachable("not reached");
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 unreachable("not reached");
101 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
102 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
103 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
105 brw_reg
= retype(brw_reg
, src
[i
].type
);
106 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
108 brw_reg
= brw_abs(brw_reg
);
110 brw_reg
= negate(brw_reg
);
112 /* This should have been moved to pull constants. */
113 assert(!src
[i
].reladdr
);
117 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 unreachable("not reached");
133 vec4_generator::vec4_generator(struct brw_context
*brw
,
134 struct gl_shader_program
*shader_prog
,
135 struct gl_program
*prog
,
136 struct brw_vec4_prog_data
*prog_data
,
139 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
140 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
142 p
= rzalloc(mem_ctx
, struct brw_compile
);
143 brw_init_compile(brw
, p
, mem_ctx
);
146 vec4_generator::~vec4_generator()
151 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
157 brw_math_function(inst
->opcode
),
160 BRW_MATH_DATA_VECTOR
,
161 BRW_MATH_PRECISION_FULL
);
165 check_gen6_math_src_arg(struct brw_reg src
)
167 /* Source swizzles are ignored. */
170 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
174 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
179 /* Can't do writemask because math can't be align16. */
180 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0
);
183 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
184 check_gen6_math_src_arg(src1
);
186 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
187 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
188 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
192 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * "Operand1[7]. For the INT DIV functions, this operand is the
206 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
207 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
208 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
210 brw_push_insn_state(p
);
211 brw_set_default_saturate(p
, false);
212 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
213 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
214 brw_pop_insn_state(p
);
218 brw_math_function(inst
->opcode
),
221 BRW_MATH_DATA_VECTOR
,
222 BRW_MATH_PRECISION_FULL
);
226 vec4_generator::generate_tex(vec4_instruction
*inst
,
233 switch (inst
->opcode
) {
234 case SHADER_OPCODE_TEX
:
235 case SHADER_OPCODE_TXL
:
236 if (inst
->shadow_compare
) {
237 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
239 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
242 case SHADER_OPCODE_TXD
:
243 if (inst
->shadow_compare
) {
244 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
245 assert(brw
->gen
>= 8 || brw
->is_haswell
);
246 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
248 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
251 case SHADER_OPCODE_TXF
:
252 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
254 case SHADER_OPCODE_TXF_CMS
:
256 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
258 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
260 case SHADER_OPCODE_TXF_MCS
:
261 assert(brw
->gen
>= 7);
262 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
264 case SHADER_OPCODE_TXS
:
265 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
267 case SHADER_OPCODE_TG4
:
268 if (inst
->shadow_compare
) {
269 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
271 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
274 case SHADER_OPCODE_TG4_OFFSET
:
275 if (inst
->shadow_compare
) {
276 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
278 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
282 unreachable("should not get here: invalid vec4 texture opcode");
285 switch (inst
->opcode
) {
286 case SHADER_OPCODE_TEX
:
287 case SHADER_OPCODE_TXL
:
288 if (inst
->shadow_compare
) {
289 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
290 assert(inst
->mlen
== 3);
292 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
293 assert(inst
->mlen
== 2);
296 case SHADER_OPCODE_TXD
:
297 /* There is no sample_d_c message; comparisons are done manually. */
298 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
299 assert(inst
->mlen
== 4);
301 case SHADER_OPCODE_TXF
:
302 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
303 assert(inst
->mlen
== 2);
305 case SHADER_OPCODE_TXS
:
306 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
307 assert(inst
->mlen
== 2);
310 unreachable("should not get here: invalid vec4 texture opcode");
314 assert(msg_type
!= -1);
316 /* Load the message header if present. If there's a texture offset, we need
317 * to set it up explicitly and load the offset bitfield. Otherwise, we can
318 * use an implied move from g0 to the first message register.
320 if (inst
->header_present
) {
321 if (brw
->gen
< 6 && !inst
->texture_offset
) {
322 /* Set up an implied move from g0 to the MRF. */
323 src
= brw_vec8_grf(0, 0);
325 struct brw_reg header
=
326 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
328 /* Explicitly set up the message header by copying g0 to the MRF. */
329 brw_push_insn_state(p
);
330 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
331 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
333 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
335 if (inst
->texture_offset
) {
336 /* Set the texel offset bits in DWord 2. */
337 brw_MOV(p
, get_element_ud(header
, 2),
338 brw_imm_ud(inst
->texture_offset
));
341 if (inst
->sampler
>= 16) {
342 /* The "Sampler Index" field can only store values between 0 and 15.
343 * However, we can add an offset to the "Sampler State Pointer"
344 * field, effectively selecting a different set of 16 samplers.
346 * The "Sampler State Pointer" needs to be aligned to a 32-byte
347 * offset, and each sampler state is only 16-bytes, so we can't
348 * exclusively use the offset - we have to use both.
350 assert(brw
->gen
>= 8 || brw
->is_haswell
);
352 get_element_ud(header
, 3),
353 get_element_ud(brw_vec8_grf(0, 0), 3),
354 brw_imm_ud(16 * (inst
->sampler
/ 16) *
355 sizeof(gen7_sampler_state
)));
357 brw_pop_insn_state(p
);
361 uint32_t return_format
;
364 case BRW_REGISTER_TYPE_D
:
365 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
367 case BRW_REGISTER_TYPE_UD
:
368 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
371 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
375 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
376 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
377 ? prog_data
->base
.binding_table
.gather_texture_start
378 : prog_data
->base
.binding_table
.texture_start
) + inst
->sampler
;
387 1, /* response length */
389 inst
->header_present
,
390 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
393 brw_mark_surface_used(&prog_data
->base
, surface_index
);
397 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
400 brw_null_reg(), /* dest */
401 inst
->base_mrf
, /* starting mrf reg nr */
402 brw_vec8_grf(0, 0), /* src */
403 inst
->urb_write_flags
,
405 0, /* response len */
406 inst
->offset
, /* urb destination offset */
407 BRW_URB_SWIZZLE_INTERLEAVE
);
411 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
413 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
415 brw_null_reg(), /* dest */
416 inst
->base_mrf
, /* starting mrf reg nr */
418 inst
->urb_write_flags
,
420 0, /* response len */
421 inst
->offset
, /* urb destination offset */
422 BRW_URB_SWIZZLE_INTERLEAVE
);
426 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
428 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
430 brw_null_reg(), /* dest */
431 inst
->base_mrf
, /* starting mrf reg nr */
435 0, /* response len */
436 0, /* urb destination offset */
437 BRW_URB_SWIZZLE_INTERLEAVE
);
441 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
445 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
448 * Slot 0 Offset. This field, after adding to the Global Offset field
449 * in the message descriptor, specifies the offset (in 256-bit units)
450 * from the start of the URB entry, as referenced by URB Handle 0, at
451 * which the data will be accessed.
453 * Similar text describes DWORD M0.4, which is slot 1 offset.
455 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
456 * of the register for geometry shader invocations 0 and 1) by the
457 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
459 * We can do this with the following EU instruction:
461 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
463 brw_push_insn_state(p
);
464 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
465 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
466 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
468 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
469 brw_pop_insn_state(p
);
473 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
476 brw_push_insn_state(p
);
477 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
478 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
480 /* If we think of the src and dst registers as composed of 8 DWORDs each,
481 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
482 * them to WORDs, and then pack them into DWORD 2 of dst.
484 * It's easier to get the EU to do this if we think of the src and dst
485 * registers as composed of 16 WORDS each; then, we want to pick up the
486 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
489 * We can do that by the following EU instruction:
491 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
493 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
494 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
495 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
496 brw_pop_insn_state(p
);
500 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
503 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
505 brw_push_insn_state(p
);
506 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
507 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
508 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
509 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
510 brw_pop_insn_state(p
);
514 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
516 /* We want to left shift just DWORD 4 (the x component belonging to the
517 * second geometry shader invocation) by 4 bits. So generate the
520 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
522 dst
= suboffset(vec1(dst
), 4);
523 brw_push_insn_state(p
);
524 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
525 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
526 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
527 brw_pop_insn_state(p
);
531 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
534 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
537 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
539 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
540 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
541 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
542 * channel enable to determine the final channel enable. For the
543 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
544 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
545 * in the writeback message. For the URB_WRITE_OWORD &
546 * URB_WRITE_HWORD messages, when final channel enable is 1 it
547 * indicates that Vertex 1 DATA [3] will be written to the surface.
549 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
550 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
552 * 14 Vertex 1 DATA [2] Channel Mask
553 * 13 Vertex 1 DATA [1] Channel Mask
554 * 12 Vertex 1 DATA [0] Channel Mask
555 * 11 Vertex 0 DATA [3] Channel Mask
556 * 10 Vertex 0 DATA [2] Channel Mask
557 * 9 Vertex 0 DATA [1] Channel Mask
558 * 8 Vertex 0 DATA [0] Channel Mask
560 * (This is from a section of the PRM that is agnostic to the particular
561 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
562 * geometry shader invocations 0 and 1, respectively). Since we have the
563 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
564 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
565 * DWORD 4, we just need to OR them together and store the result in bits
568 * It's easier to get the EU to do this if we think of the src and dst
569 * registers as composed of 32 bytes each; then, we want to pick up the
570 * contents of bytes 0 and 16 from src, OR them together, and store them in
573 * We can do that by the following EU instruction:
575 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
577 * Note: this relies on the source register having zeros in (a) bits 7:4 of
578 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
579 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
580 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
581 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
582 * contain valid channel mask values (which are in the range 0x0-0xf).
584 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
585 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
586 brw_push_insn_state(p
);
587 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
588 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
589 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
590 brw_pop_insn_state(p
);
594 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
596 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
597 * and store into dst.0 & dst.4. So generate the instruction:
599 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
601 brw_push_insn_state(p
);
602 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
603 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
604 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
605 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
606 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
607 brw_pop_insn_state(p
);
611 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
612 struct brw_reg index
)
614 int second_vertex_offset
;
617 second_vertex_offset
= 1;
619 second_vertex_offset
= 16;
621 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
623 /* Set up M1 (message payload). Only the block offsets in M1.0 and
624 * M1.4 are used, and the rest are ignored.
626 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
627 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
628 struct brw_reg index_0
= suboffset(vec1(index
), 0);
629 struct brw_reg index_4
= suboffset(vec1(index
), 4);
631 brw_push_insn_state(p
);
632 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
633 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
635 brw_MOV(p
, m1_0
, index_0
);
637 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
638 index_4
.dw1
.ud
+= second_vertex_offset
;
639 brw_MOV(p
, m1_4
, index_4
);
641 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
644 brw_pop_insn_state(p
);
648 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
651 brw_push_insn_state(p
);
652 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
653 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
655 struct brw_reg flags
= brw_flag_reg(0, 0);
656 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
657 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
659 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
660 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
661 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
663 brw_pop_insn_state(p
);
667 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
669 struct brw_reg index
)
671 struct brw_reg header
= brw_vec8_grf(0, 0);
673 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
675 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
681 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
682 else if (brw
->gen
== 5 || brw
->is_g4x
)
683 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
685 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
687 /* Each of the 8 channel enables is considered for whether each
690 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
691 brw_set_dest(p
, send
, dst
);
692 brw_set_src0(p
, send
, header
);
694 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
695 brw_set_dp_read_message(p
, send
,
696 255, /* binding table index: stateless access */
697 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
699 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
701 true, /* header_present */
706 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
709 struct brw_reg index
)
711 struct brw_reg header
= brw_vec8_grf(0, 0);
714 /* If the instruction is predicated, we'll predicate the send, not
717 brw_set_default_predicate_control(p
, false);
719 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
721 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
725 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
726 retype(src
, BRW_REGISTER_TYPE_D
));
731 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
732 else if (brw
->gen
== 6)
733 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
735 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
737 brw_set_default_predicate_control(p
, inst
->predicate
);
739 /* Pre-gen6, we have to specify write commits to ensure ordering
740 * between reads and writes within a thread. Afterwards, that's
741 * guaranteed and write commits only matter for inter-thread
745 write_commit
= false;
747 /* The visitor set up our destination register to be g0. This
748 * means that when the next read comes along, we will end up
749 * reading from g0 and causing a block on the write commit. For
750 * write-after-read, we are relying on the value of the previous
751 * read being used (and thus blocking on completion) before our
752 * write is executed. This means we have to be careful in
753 * instruction scheduling to not violate this assumption.
758 /* Each of the 8 channel enables is considered for whether each
761 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
762 brw_set_dest(p
, send
, dst
);
763 brw_set_src0(p
, send
, header
);
765 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
766 brw_set_dp_write_message(p
, send
,
767 255, /* binding table index: stateless access */
768 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
771 true, /* header present */
772 false, /* not a render target write */
773 write_commit
, /* rlen */
779 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
781 struct brw_reg index
,
782 struct brw_reg offset
)
784 assert(brw
->gen
<= 7);
785 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
786 index
.type
== BRW_REGISTER_TYPE_UD
);
787 uint32_t surf_index
= index
.dw1
.ud
;
789 struct brw_reg header
= brw_vec8_grf(0, 0);
791 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
793 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
799 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
800 else if (brw
->gen
== 5 || brw
->is_g4x
)
801 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
803 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
805 /* Each of the 8 channel enables is considered for whether each
808 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
809 brw_set_dest(p
, send
, dst
);
810 brw_set_src0(p
, send
, header
);
812 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
813 brw_set_dp_read_message(p
, send
,
815 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
817 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
819 true, /* header_present */
822 brw_mark_surface_used(&prog_data
->base
, surf_index
);
826 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
828 struct brw_reg surf_index
,
829 struct brw_reg offset
)
831 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
832 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
834 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
835 brw_set_dest(p
, insn
, dst
);
836 brw_set_src0(p
, insn
, offset
);
837 brw_set_sampler_message(p
, insn
,
839 0, /* LD message ignores sampler unit */
840 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
843 false, /* no header */
844 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
847 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
851 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
853 struct brw_reg atomic_op
,
854 struct brw_reg surf_index
)
856 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
857 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
858 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
859 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
861 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
862 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
865 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
869 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
871 struct brw_reg surf_index
)
873 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
874 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
876 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
880 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
884 * Generate assembly for a Vec4 IR instruction.
886 * \param instruction The Vec4 IR instruction to generate code for.
887 * \param dst The destination register.
888 * \param src An array of up to three source registers.
891 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
895 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
897 if (dst
.width
== BRW_WIDTH_4
) {
898 /* This happens in attribute fixups for "dual instanced" geometry
899 * shaders, since they use attributes that are vec4's. Since the exec
900 * width is only 4, it's essential that the caller set
901 * force_writemask_all in order to make sure the instruction is executed
902 * regardless of which channels are enabled.
904 assert(inst
->force_writemask_all
);
906 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
907 * the following register region restrictions (from Graphics BSpec:
908 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
909 * > Register Region Restrictions)
911 * 1. ExecSize must be greater than or equal to Width.
913 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
914 * to Width * HorzStride."
916 for (int i
= 0; i
< 3; i
++) {
917 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
918 src
[i
] = stride(src
[i
], 4, 4, 1);
922 switch (inst
->opcode
) {
924 brw_MOV(p
, dst
, src
[0]);
927 brw_ADD(p
, dst
, src
[0], src
[1]);
930 brw_MUL(p
, dst
, src
[0], src
[1]);
932 case BRW_OPCODE_MACH
:
933 brw_MACH(p
, dst
, src
[0], src
[1]);
937 assert(brw
->gen
>= 6);
938 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
942 brw_FRC(p
, dst
, src
[0]);
944 case BRW_OPCODE_RNDD
:
945 brw_RNDD(p
, dst
, src
[0]);
947 case BRW_OPCODE_RNDE
:
948 brw_RNDE(p
, dst
, src
[0]);
950 case BRW_OPCODE_RNDZ
:
951 brw_RNDZ(p
, dst
, src
[0]);
955 brw_AND(p
, dst
, src
[0], src
[1]);
958 brw_OR(p
, dst
, src
[0], src
[1]);
961 brw_XOR(p
, dst
, src
[0], src
[1]);
964 brw_NOT(p
, dst
, src
[0]);
967 brw_ASR(p
, dst
, src
[0], src
[1]);
970 brw_SHR(p
, dst
, src
[0], src
[1]);
973 brw_SHL(p
, dst
, src
[0], src
[1]);
977 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
980 brw_SEL(p
, dst
, src
[0], src
[1]);
984 brw_DPH(p
, dst
, src
[0], src
[1]);
988 brw_DP4(p
, dst
, src
[0], src
[1]);
992 brw_DP3(p
, dst
, src
[0], src
[1]);
996 brw_DP2(p
, dst
, src
[0], src
[1]);
999 case BRW_OPCODE_F32TO16
:
1000 assert(brw
->gen
>= 7);
1001 brw_F32TO16(p
, dst
, src
[0]);
1004 case BRW_OPCODE_F16TO32
:
1005 assert(brw
->gen
>= 7);
1006 brw_F16TO32(p
, dst
, src
[0]);
1009 case BRW_OPCODE_LRP
:
1010 assert(brw
->gen
>= 6);
1011 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1014 case BRW_OPCODE_BFREV
:
1015 assert(brw
->gen
>= 7);
1016 /* BFREV only supports UD type for src and dst. */
1017 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1018 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1020 case BRW_OPCODE_FBH
:
1021 assert(brw
->gen
>= 7);
1022 /* FBH only supports UD type for dst. */
1023 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1025 case BRW_OPCODE_FBL
:
1026 assert(brw
->gen
>= 7);
1027 /* FBL only supports UD type for dst. */
1028 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1030 case BRW_OPCODE_CBIT
:
1031 assert(brw
->gen
>= 7);
1032 /* CBIT only supports UD type for dst. */
1033 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1035 case BRW_OPCODE_ADDC
:
1036 assert(brw
->gen
>= 7);
1037 brw_ADDC(p
, dst
, src
[0], src
[1]);
1039 case BRW_OPCODE_SUBB
:
1040 assert(brw
->gen
>= 7);
1041 brw_SUBB(p
, dst
, src
[0], src
[1]);
1043 case BRW_OPCODE_MAC
:
1044 brw_MAC(p
, dst
, src
[0], src
[1]);
1047 case BRW_OPCODE_BFE
:
1048 assert(brw
->gen
>= 7);
1049 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1052 case BRW_OPCODE_BFI1
:
1053 assert(brw
->gen
>= 7);
1054 brw_BFI1(p
, dst
, src
[0], src
[1]);
1056 case BRW_OPCODE_BFI2
:
1057 assert(brw
->gen
>= 7);
1058 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1062 if (inst
->src
[0].file
!= BAD_FILE
) {
1063 /* The instruction has an embedded compare (only allowed on gen6) */
1064 assert(brw
->gen
== 6);
1065 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1067 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1068 brw_inst_set_pred_control(brw
, if_inst
, inst
->predicate
);
1072 case BRW_OPCODE_ELSE
:
1075 case BRW_OPCODE_ENDIF
:
1080 brw_DO(p
, BRW_EXECUTE_8
);
1083 case BRW_OPCODE_BREAK
:
1085 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1087 case BRW_OPCODE_CONTINUE
:
1088 /* FINISHME: We need to write the loop instruction support still. */
1093 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1096 case BRW_OPCODE_WHILE
:
1100 case SHADER_OPCODE_RCP
:
1101 case SHADER_OPCODE_RSQ
:
1102 case SHADER_OPCODE_SQRT
:
1103 case SHADER_OPCODE_EXP2
:
1104 case SHADER_OPCODE_LOG2
:
1105 case SHADER_OPCODE_SIN
:
1106 case SHADER_OPCODE_COS
:
1107 if (brw
->gen
>= 7) {
1108 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1110 } else if (brw
->gen
== 6) {
1111 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1113 generate_math1_gen4(inst
, dst
, src
[0]);
1117 case SHADER_OPCODE_POW
:
1118 case SHADER_OPCODE_INT_QUOTIENT
:
1119 case SHADER_OPCODE_INT_REMAINDER
:
1120 if (brw
->gen
>= 7) {
1121 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1122 } else if (brw
->gen
== 6) {
1123 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1125 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1129 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TXL
:
1135 case SHADER_OPCODE_TXS
:
1136 case SHADER_OPCODE_TG4
:
1137 case SHADER_OPCODE_TG4_OFFSET
:
1138 generate_tex(inst
, dst
, src
[0]);
1141 case VS_OPCODE_URB_WRITE
:
1142 generate_vs_urb_write(inst
);
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1146 generate_scratch_read(inst
, dst
, src
[0]);
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1150 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1153 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1154 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1157 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1158 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1161 case GS_OPCODE_URB_WRITE
:
1162 generate_gs_urb_write(inst
);
1165 case GS_OPCODE_THREAD_END
:
1166 generate_gs_thread_end(inst
);
1169 case GS_OPCODE_SET_WRITE_OFFSET
:
1170 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1173 case GS_OPCODE_SET_VERTEX_COUNT
:
1174 generate_gs_set_vertex_count(dst
, src
[0]);
1177 case GS_OPCODE_SET_DWORD_2_IMMED
:
1178 generate_gs_set_dword_2_immed(dst
, src
[0]);
1181 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1182 generate_gs_prepare_channel_masks(dst
);
1185 case GS_OPCODE_SET_CHANNEL_MASKS
:
1186 generate_gs_set_channel_masks(dst
, src
[0]);
1189 case GS_OPCODE_GET_INSTANCE_ID
:
1190 generate_gs_get_instance_id(dst
);
1193 case SHADER_OPCODE_SHADER_TIME_ADD
:
1194 brw_shader_time_add(p
, src
[0],
1195 prog_data
->base
.binding_table
.shader_time_start
);
1196 brw_mark_surface_used(&prog_data
->base
,
1197 prog_data
->base
.binding_table
.shader_time_start
);
1200 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1201 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1204 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1205 generate_untyped_surface_read(inst
, dst
, src
[0]);
1208 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1209 generate_unpack_flags(inst
, dst
);
1213 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1214 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1215 opcode_descs
[inst
->opcode
].name
);
1217 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1224 vec4_generator::generate_code(exec_list
*instructions
)
1226 struct annotation_info annotation
;
1227 memset(&annotation
, 0, sizeof(annotation
));
1230 if (unlikely(debug_flag
))
1231 cfg
= new(mem_ctx
) cfg_t(instructions
);
1233 foreach_in_list(vec4_instruction
, inst
, instructions
) {
1234 struct brw_reg src
[3], dst
;
1236 if (unlikely(debug_flag
))
1237 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1239 for (unsigned int i
= 0; i
< 3; i
++) {
1240 src
[i
] = inst
->get_src(this->prog_data
, i
);
1242 dst
= inst
->get_dst();
1244 brw_set_default_predicate_control(p
, inst
->predicate
);
1245 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1246 brw_set_default_saturate(p
, inst
->saturate
);
1247 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1248 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1250 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1252 generate_vec4_instruction(inst
, dst
, src
);
1254 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1255 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1256 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1257 "emitting more than 1 instruction");
1259 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1261 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1262 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1263 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1268 annotation_finalize(&annotation
, p
->next_insn_offset
);
1270 int before_size
= p
->next_insn_offset
;
1271 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1272 int after_size
= p
->next_insn_offset
;
1274 if (unlikely(debug_flag
)) {
1276 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1277 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1280 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1282 fprintf(stderr
, "vec4 shader: %d instructions. Compacted %d to %d"
1283 " bytes (%.0f%%)\n",
1284 before_size
/ 16, before_size
, after_size
,
1285 100.0f
* (before_size
- after_size
) / before_size
);
1287 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
1288 ralloc_free(annotation
.ann
);
1293 vec4_generator::generate_assembly(exec_list
*instructions
,
1294 unsigned *assembly_size
)
1296 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1297 generate_code(instructions
);
1299 return brw_get_program(p
, assembly_size
);
1302 } /* namespace brw */