1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 unreachable("not reached");
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].fixed_hw_reg
.dw1
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].fixed_hw_reg
.dw1
.d
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].fixed_hw_reg
.dw1
.ud
);
96 unreachable("not reached");
101 brw_reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
102 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
103 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
105 brw_reg
= retype(brw_reg
, src
[i
].type
);
106 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
108 brw_reg
= brw_abs(brw_reg
);
110 brw_reg
= negate(brw_reg
);
112 /* This should have been moved to pull constants. */
113 assert(!src
[i
].reladdr
);
117 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 unreachable("not reached");
133 vec4_generator::vec4_generator(struct brw_context
*brw
,
134 struct gl_shader_program
*shader_prog
,
135 struct gl_program
*prog
,
136 struct brw_vec4_prog_data
*prog_data
,
139 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
140 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
142 p
= rzalloc(mem_ctx
, struct brw_compile
);
143 brw_init_compile(brw
, p
, mem_ctx
);
146 vec4_generator::~vec4_generator()
151 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
157 brw_math_function(inst
->opcode
),
160 BRW_MATH_DATA_VECTOR
,
161 BRW_MATH_PRECISION_FULL
);
165 check_gen6_math_src_arg(struct brw_reg src
)
167 /* Source swizzles are ignored. */
170 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
174 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
179 /* Can't do writemask because math can't be align16. */
180 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0
);
183 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
184 check_gen6_math_src_arg(src1
);
186 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
187 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
188 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
192 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * "Operand1[7]. For the INT DIV functions, this operand is the
206 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
207 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
208 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
210 brw_push_insn_state(p
);
211 brw_set_default_saturate(p
, false);
212 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
213 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
214 brw_pop_insn_state(p
);
218 brw_math_function(inst
->opcode
),
221 BRW_MATH_DATA_VECTOR
,
222 BRW_MATH_PRECISION_FULL
);
226 vec4_generator::generate_tex(vec4_instruction
*inst
,
229 struct brw_reg sampler_index
)
234 switch (inst
->opcode
) {
235 case SHADER_OPCODE_TEX
:
236 case SHADER_OPCODE_TXL
:
237 if (inst
->shadow_compare
) {
238 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
240 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
243 case SHADER_OPCODE_TXD
:
244 if (inst
->shadow_compare
) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw
->gen
>= 8 || brw
->is_haswell
);
247 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
249 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
252 case SHADER_OPCODE_TXF
:
253 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
255 case SHADER_OPCODE_TXF_CMS
:
257 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
259 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
261 case SHADER_OPCODE_TXF_MCS
:
262 assert(brw
->gen
>= 7);
263 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
265 case SHADER_OPCODE_TXS
:
266 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
268 case SHADER_OPCODE_TG4
:
269 if (inst
->shadow_compare
) {
270 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
272 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
275 case SHADER_OPCODE_TG4_OFFSET
:
276 if (inst
->shadow_compare
) {
277 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
279 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
283 unreachable("should not get here: invalid vec4 texture opcode");
286 switch (inst
->opcode
) {
287 case SHADER_OPCODE_TEX
:
288 case SHADER_OPCODE_TXL
:
289 if (inst
->shadow_compare
) {
290 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
291 assert(inst
->mlen
== 3);
293 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
294 assert(inst
->mlen
== 2);
297 case SHADER_OPCODE_TXD
:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
300 assert(inst
->mlen
== 4);
302 case SHADER_OPCODE_TXF
:
303 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
304 assert(inst
->mlen
== 2);
306 case SHADER_OPCODE_TXS
:
307 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
308 assert(inst
->mlen
== 2);
311 unreachable("should not get here: invalid vec4 texture opcode");
315 assert(msg_type
!= -1);
317 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
319 /* Load the message header if present. If there's a texture offset, we need
320 * to set it up explicitly and load the offset bitfield. Otherwise, we can
321 * use an implied move from g0 to the first message register.
323 if (inst
->header_present
) {
324 if (brw
->gen
< 6 && !inst
->texture_offset
) {
325 /* Set up an implied move from g0 to the MRF. */
326 src
= brw_vec8_grf(0, 0);
328 struct brw_reg header
=
329 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
331 /* Explicitly set up the message header by copying g0 to the MRF. */
332 brw_push_insn_state(p
);
333 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
334 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
336 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
338 if (inst
->texture_offset
) {
339 /* Set the texel offset bits in DWord 2. */
340 brw_MOV(p
, get_element_ud(header
, 2),
341 brw_imm_ud(inst
->texture_offset
));
344 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
, dst
);
345 brw_pop_insn_state(p
);
349 uint32_t return_format
;
352 case BRW_REGISTER_TYPE_D
:
353 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
355 case BRW_REGISTER_TYPE_UD
:
356 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
359 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
363 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
364 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
365 ? prog_data
->base
.binding_table
.gather_texture_start
366 : prog_data
->base
.binding_table
.texture_start
;
368 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
369 uint32_t sampler
= sampler_index
.dw1
.ud
;
375 sampler
+ base_binding_table_index
,
378 1, /* response length */
380 inst
->header_present
,
381 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
384 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
386 /* Non-constant sampler index. */
387 /* Note: this clobbers `dst` as a temporary before emitting the send */
389 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
390 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
392 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
394 brw_push_insn_state(p
);
395 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
396 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
398 /* Some care required: `sampler` and `temp` may alias:
399 * addr = sampler & 0xff
400 * temp = (sampler << 8) & 0xf00
403 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
404 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
405 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
406 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
407 brw_OR(p
, addr
, addr
, temp
);
409 /* a0.0 |= <descriptor> */
410 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
411 brw_set_sampler_message(p
, insn_or
,
416 inst
->mlen
/* mlen */,
417 inst
->header_present
/* header */,
418 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
420 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
421 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
422 brw_set_src0(p
, insn_or
, addr
);
423 brw_set_dest(p
, insn_or
, addr
);
426 /* dst = send(offset, a0.0) */
427 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
428 brw_set_dest(p
, insn_send
, dst
);
429 brw_set_src0(p
, insn_send
, src
);
430 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
432 brw_pop_insn_state(p
);
434 /* visitor knows more than we do about the surface limit required,
435 * so has already done marking.
441 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
444 brw_null_reg(), /* dest */
445 inst
->base_mrf
, /* starting mrf reg nr */
446 brw_vec8_grf(0, 0), /* src */
447 inst
->urb_write_flags
,
449 0, /* response len */
450 inst
->offset
, /* urb destination offset */
451 BRW_URB_SWIZZLE_INTERLEAVE
);
455 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
457 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
459 brw_null_reg(), /* dest */
460 inst
->base_mrf
, /* starting mrf reg nr */
462 inst
->urb_write_flags
,
464 0, /* response len */
465 inst
->offset
, /* urb destination offset */
466 BRW_URB_SWIZZLE_INTERLEAVE
);
470 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction
*inst
)
472 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
474 /* We pass the temporary passed in src0 as the writeback register */
476 inst
->get_src(this->prog_data
, 0), /* dest */
477 inst
->base_mrf
, /* starting mrf reg nr */
479 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
481 1, /* response len */
482 inst
->offset
, /* urb destination offset */
483 BRW_URB_SWIZZLE_INTERLEAVE
);
485 /* Now put allocated urb handle in dst.0 */
486 brw_push_insn_state(p
);
487 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
488 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
489 brw_MOV(p
, get_element_ud(inst
->get_dst(), 0),
490 get_element_ud(inst
->get_src(this->prog_data
, 0), 0));
491 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
492 brw_pop_insn_state(p
);
496 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
498 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
500 brw_null_reg(), /* dest */
501 inst
->base_mrf
, /* starting mrf reg nr */
503 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
504 brw
->gen
>= 8 ? 2 : 1,/* message len */
505 0, /* response len */
506 0, /* urb destination offset */
507 BRW_URB_SWIZZLE_INTERLEAVE
);
511 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
515 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
518 * Slot 0 Offset. This field, after adding to the Global Offset field
519 * in the message descriptor, specifies the offset (in 256-bit units)
520 * from the start of the URB entry, as referenced by URB Handle 0, at
521 * which the data will be accessed.
523 * Similar text describes DWORD M0.4, which is slot 1 offset.
525 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
526 * of the register for geometry shader invocations 0 and 1) by the
527 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
529 * We can do this with the following EU instruction:
531 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
533 brw_push_insn_state(p
);
534 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
535 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
536 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
538 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
539 brw_pop_insn_state(p
);
543 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
546 brw_push_insn_state(p
);
547 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
550 /* Move the vertex count into the second MRF for the EOT write. */
551 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
554 /* If we think of the src and dst registers as composed of 8 DWORDs each,
555 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
556 * them to WORDs, and then pack them into DWORD 2 of dst.
558 * It's easier to get the EU to do this if we think of the src and dst
559 * registers as composed of 16 WORDS each; then, we want to pick up the
560 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
563 * We can do that by the following EU instruction:
565 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
567 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
569 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
570 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
571 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
573 brw_pop_insn_state(p
);
577 vec4_generator::generate_gs_svb_write(vec4_instruction
*inst
,
582 int binding
= inst
->sol_binding
;
583 bool final_write
= inst
->sol_final_write
;
585 brw_push_insn_state(p
);
586 /* Copy Vertex data into M0.x */
587 brw_MOV(p
, stride(dst
, 4, 4, 1),
588 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
592 final_write
? src1
: brw_null_reg(), /* dest == src1 */
594 dst
, /* src0 == previous dst */
595 SURF_INDEX_GEN6_SOL_BINDING(binding
), /* binding_table_index */
596 final_write
); /* send_commit_msg */
598 /* Finally, wait for the write commit to occur so that we can proceed to
599 * other things safely.
601 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
603 * The write commit does not modify the destination register, but
604 * merely clears the dependency associated with the destination
605 * register. Thus, a simple “mov” instruction using the register as a
606 * source is sufficient to wait for the write commit to occur.
609 brw_MOV(p
, src1
, src1
);
611 brw_pop_insn_state(p
);
615 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction
*inst
,
620 int vertex
= inst
->sol_vertex
;
621 brw_push_insn_state(p
);
622 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
623 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
624 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
625 brw_pop_insn_state(p
);
629 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst
, struct brw_reg src
)
631 brw_push_insn_state(p
);
632 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
633 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
634 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
635 brw_pop_insn_state(p
);
639 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
641 /* We want to left shift just DWORD 4 (the x component belonging to the
642 * second geometry shader invocation) by 4 bits. So generate the
645 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
647 dst
= suboffset(vec1(dst
), 4);
648 brw_push_insn_state(p
);
649 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
650 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
651 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
652 brw_pop_insn_state(p
);
656 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
659 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
662 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
664 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
665 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
666 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
667 * channel enable to determine the final channel enable. For the
668 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
669 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
670 * in the writeback message. For the URB_WRITE_OWORD &
671 * URB_WRITE_HWORD messages, when final channel enable is 1 it
672 * indicates that Vertex 1 DATA [3] will be written to the surface.
674 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
675 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
677 * 14 Vertex 1 DATA [2] Channel Mask
678 * 13 Vertex 1 DATA [1] Channel Mask
679 * 12 Vertex 1 DATA [0] Channel Mask
680 * 11 Vertex 0 DATA [3] Channel Mask
681 * 10 Vertex 0 DATA [2] Channel Mask
682 * 9 Vertex 0 DATA [1] Channel Mask
683 * 8 Vertex 0 DATA [0] Channel Mask
685 * (This is from a section of the PRM that is agnostic to the particular
686 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
687 * geometry shader invocations 0 and 1, respectively). Since we have the
688 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
689 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
690 * DWORD 4, we just need to OR them together and store the result in bits
693 * It's easier to get the EU to do this if we think of the src and dst
694 * registers as composed of 32 bytes each; then, we want to pick up the
695 * contents of bytes 0 and 16 from src, OR them together, and store them in
698 * We can do that by the following EU instruction:
700 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
702 * Note: this relies on the source register having zeros in (a) bits 7:4 of
703 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
704 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
705 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
706 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
707 * contain valid channel mask values (which are in the range 0x0-0xf).
709 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
710 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
711 brw_push_insn_state(p
);
712 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
713 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
714 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
715 brw_pop_insn_state(p
);
719 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
721 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
722 * and store into dst.0 & dst.4. So generate the instruction:
724 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
726 brw_push_insn_state(p
);
727 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
728 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
729 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
730 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
731 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
732 brw_pop_insn_state(p
);
736 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst
,
741 brw_push_insn_state(p
);
742 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
743 /* Save src0 data in 16:31 bits of dst.0 */
744 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
745 brw_imm_ud(0xffffu
));
746 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
747 /* Save src1 data in 0:15 bits of dst.0 */
748 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
749 brw_imm_ud(0xffffu
));
750 brw_OR(p
, suboffset(vec1(dst
), 0),
751 suboffset(vec1(dst
), 0),
752 suboffset(vec1(src2
), 0));
753 brw_pop_insn_state(p
);
757 vec4_generator::generate_gs_ff_sync(vec4_instruction
*inst
,
761 /* This opcode uses an implied MRF register for:
762 * - the header of the ff_sync message. And as such it is expected to be
763 * initialized to r0 before calling here.
764 * - the destination where we will write the allocated URB handle.
766 struct brw_reg header
=
767 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
769 /* Overwrite dword 0 of the header (cleared for now since we are not doing
770 * transform feedback) and dword 1 (to hold the number of primitives
773 brw_push_insn_state(p
);
774 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
775 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
776 brw_MOV(p
, get_element_ud(header
, 0), brw_imm_ud(0));
777 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
778 brw_pop_insn_state(p
);
780 /* Allocate URB handle in dst */
786 1, /* response length */
789 /* Now put allocated urb handle in header.0 */
790 brw_push_insn_state(p
);
791 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
792 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
793 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
794 brw_pop_insn_state(p
);
798 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst
)
800 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
801 struct brw_reg src
= brw_vec8_grf(0, 0);
802 brw_push_insn_state(p
);
803 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
804 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
805 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
806 brw_pop_insn_state(p
);
810 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
811 struct brw_reg index
)
813 int second_vertex_offset
;
816 second_vertex_offset
= 1;
818 second_vertex_offset
= 16;
820 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
822 /* Set up M1 (message payload). Only the block offsets in M1.0 and
823 * M1.4 are used, and the rest are ignored.
825 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
826 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
827 struct brw_reg index_0
= suboffset(vec1(index
), 0);
828 struct brw_reg index_4
= suboffset(vec1(index
), 4);
830 brw_push_insn_state(p
);
831 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
832 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
834 brw_MOV(p
, m1_0
, index_0
);
836 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
837 index_4
.dw1
.ud
+= second_vertex_offset
;
838 brw_MOV(p
, m1_4
, index_4
);
840 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
843 brw_pop_insn_state(p
);
847 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
850 brw_push_insn_state(p
);
851 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
852 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
854 struct brw_reg flags
= brw_flag_reg(0, 0);
855 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
856 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
858 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
859 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
860 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
862 brw_pop_insn_state(p
);
866 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
868 struct brw_reg index
)
870 struct brw_reg header
= brw_vec8_grf(0, 0);
872 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
874 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
880 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
881 else if (brw
->gen
== 5 || brw
->is_g4x
)
882 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
884 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
886 /* Each of the 8 channel enables is considered for whether each
889 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
890 brw_set_dest(p
, send
, dst
);
891 brw_set_src0(p
, send
, header
);
893 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
894 brw_set_dp_read_message(p
, send
,
895 255, /* binding table index: stateless access */
896 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
898 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
900 true, /* header_present */
905 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
908 struct brw_reg index
)
910 struct brw_reg header
= brw_vec8_grf(0, 0);
913 /* If the instruction is predicated, we'll predicate the send, not
916 brw_set_default_predicate_control(p
, false);
918 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
920 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
924 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
925 retype(src
, BRW_REGISTER_TYPE_D
));
930 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
931 else if (brw
->gen
== 6)
932 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
934 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
936 brw_set_default_predicate_control(p
, inst
->predicate
);
938 /* Pre-gen6, we have to specify write commits to ensure ordering
939 * between reads and writes within a thread. Afterwards, that's
940 * guaranteed and write commits only matter for inter-thread
944 write_commit
= false;
946 /* The visitor set up our destination register to be g0. This
947 * means that when the next read comes along, we will end up
948 * reading from g0 and causing a block on the write commit. For
949 * write-after-read, we are relying on the value of the previous
950 * read being used (and thus blocking on completion) before our
951 * write is executed. This means we have to be careful in
952 * instruction scheduling to not violate this assumption.
957 /* Each of the 8 channel enables is considered for whether each
960 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
961 brw_set_dest(p
, send
, dst
);
962 brw_set_src0(p
, send
, header
);
964 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
965 brw_set_dp_write_message(p
, send
,
966 255, /* binding table index: stateless access */
967 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
970 true, /* header present */
971 false, /* not a render target write */
972 write_commit
, /* rlen */
978 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
980 struct brw_reg index
,
981 struct brw_reg offset
)
983 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
984 index
.type
== BRW_REGISTER_TYPE_UD
);
985 uint32_t surf_index
= index
.dw1
.ud
;
987 struct brw_reg header
= brw_vec8_grf(0, 0);
989 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
991 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
997 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
998 else if (brw
->gen
== 5 || brw
->is_g4x
)
999 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1001 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1003 /* Each of the 8 channel enables is considered for whether each
1006 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1007 brw_set_dest(p
, send
, dst
);
1008 brw_set_src0(p
, send
, header
);
1010 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
1011 brw_set_dp_read_message(p
, send
,
1013 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1015 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
1017 true, /* header_present */
1020 brw_mark_surface_used(&prog_data
->base
, surf_index
);
1024 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
1026 struct brw_reg surf_index
,
1027 struct brw_reg offset
)
1029 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1031 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
1033 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1034 brw_set_dest(p
, insn
, dst
);
1035 brw_set_src0(p
, insn
, offset
);
1036 brw_set_sampler_message(p
, insn
,
1038 0, /* LD message ignores sampler unit */
1039 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1042 false, /* no header */
1043 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1046 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
1050 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1052 brw_push_insn_state(p
);
1053 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1054 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1056 /* a0.0 = surf_index & 0xff */
1057 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1058 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
1059 brw_set_dest(p
, insn_and
, addr
);
1060 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1061 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1064 /* a0.0 |= <descriptor> */
1065 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
1066 brw_set_sampler_message(p
, insn_or
,
1069 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1073 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1075 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
1076 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
1077 brw_set_src0(p
, insn_or
, addr
);
1078 brw_set_dest(p
, insn_or
, addr
);
1081 /* dst = send(offset, a0.0) */
1082 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1083 brw_set_dest(p
, insn_send
, dst
);
1084 brw_set_src0(p
, insn_send
, offset
);
1085 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
1087 brw_pop_insn_state(p
);
1089 /* visitor knows more than we do about the surface limit required,
1090 * so has already done marking.
1096 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
1098 struct brw_reg atomic_op
,
1099 struct brw_reg surf_index
)
1101 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
1102 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
1103 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1104 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1106 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
1107 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
1110 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
1114 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
1116 struct brw_reg surf_index
)
1118 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1119 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1121 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1125 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
1129 vec4_generator::generate_code(const cfg_t
*cfg
)
1131 struct annotation_info annotation
;
1132 memset(&annotation
, 0, sizeof(annotation
));
1135 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1136 struct brw_reg src
[3], dst
;
1138 if (unlikely(debug_flag
))
1139 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1141 for (unsigned int i
= 0; i
< 3; i
++) {
1142 src
[i
] = inst
->get_src(this->prog_data
, i
);
1144 dst
= inst
->get_dst();
1146 brw_set_default_predicate_control(p
, inst
->predicate
);
1147 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1148 brw_set_default_saturate(p
, inst
->saturate
);
1149 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1150 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1152 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1154 if (dst
.width
== BRW_WIDTH_4
) {
1155 /* This happens in attribute fixups for "dual instanced" geometry
1156 * shaders, since they use attributes that are vec4's. Since the exec
1157 * width is only 4, it's essential that the caller set
1158 * force_writemask_all in order to make sure the instruction is executed
1159 * regardless of which channels are enabled.
1161 assert(inst
->force_writemask_all
);
1163 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1164 * the following register region restrictions (from Graphics BSpec:
1165 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1166 * > Register Region Restrictions)
1168 * 1. ExecSize must be greater than or equal to Width.
1170 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1171 * to Width * HorzStride."
1173 for (int i
= 0; i
< 3; i
++) {
1174 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
1175 src
[i
] = stride(src
[i
], 4, 4, 1);
1179 switch (inst
->opcode
) {
1180 case BRW_OPCODE_MOV
:
1181 brw_MOV(p
, dst
, src
[0]);
1183 case BRW_OPCODE_ADD
:
1184 brw_ADD(p
, dst
, src
[0], src
[1]);
1186 case BRW_OPCODE_MUL
:
1187 brw_MUL(p
, dst
, src
[0], src
[1]);
1189 case BRW_OPCODE_MACH
:
1190 brw_MACH(p
, dst
, src
[0], src
[1]);
1193 case BRW_OPCODE_MAD
:
1194 assert(brw
->gen
>= 6);
1195 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1198 case BRW_OPCODE_FRC
:
1199 brw_FRC(p
, dst
, src
[0]);
1201 case BRW_OPCODE_RNDD
:
1202 brw_RNDD(p
, dst
, src
[0]);
1204 case BRW_OPCODE_RNDE
:
1205 brw_RNDE(p
, dst
, src
[0]);
1207 case BRW_OPCODE_RNDZ
:
1208 brw_RNDZ(p
, dst
, src
[0]);
1211 case BRW_OPCODE_AND
:
1212 brw_AND(p
, dst
, src
[0], src
[1]);
1215 brw_OR(p
, dst
, src
[0], src
[1]);
1217 case BRW_OPCODE_XOR
:
1218 brw_XOR(p
, dst
, src
[0], src
[1]);
1220 case BRW_OPCODE_NOT
:
1221 brw_NOT(p
, dst
, src
[0]);
1223 case BRW_OPCODE_ASR
:
1224 brw_ASR(p
, dst
, src
[0], src
[1]);
1226 case BRW_OPCODE_SHR
:
1227 brw_SHR(p
, dst
, src
[0], src
[1]);
1229 case BRW_OPCODE_SHL
:
1230 brw_SHL(p
, dst
, src
[0], src
[1]);
1233 case BRW_OPCODE_CMP
:
1234 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1236 case BRW_OPCODE_SEL
:
1237 brw_SEL(p
, dst
, src
[0], src
[1]);
1240 case BRW_OPCODE_DPH
:
1241 brw_DPH(p
, dst
, src
[0], src
[1]);
1244 case BRW_OPCODE_DP4
:
1245 brw_DP4(p
, dst
, src
[0], src
[1]);
1248 case BRW_OPCODE_DP3
:
1249 brw_DP3(p
, dst
, src
[0], src
[1]);
1252 case BRW_OPCODE_DP2
:
1253 brw_DP2(p
, dst
, src
[0], src
[1]);
1256 case BRW_OPCODE_F32TO16
:
1257 assert(brw
->gen
>= 7);
1258 brw_F32TO16(p
, dst
, src
[0]);
1261 case BRW_OPCODE_F16TO32
:
1262 assert(brw
->gen
>= 7);
1263 brw_F16TO32(p
, dst
, src
[0]);
1266 case BRW_OPCODE_LRP
:
1267 assert(brw
->gen
>= 6);
1268 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1271 case BRW_OPCODE_BFREV
:
1272 assert(brw
->gen
>= 7);
1273 /* BFREV only supports UD type for src and dst. */
1274 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1275 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1277 case BRW_OPCODE_FBH
:
1278 assert(brw
->gen
>= 7);
1279 /* FBH only supports UD type for dst. */
1280 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1282 case BRW_OPCODE_FBL
:
1283 assert(brw
->gen
>= 7);
1284 /* FBL only supports UD type for dst. */
1285 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1287 case BRW_OPCODE_CBIT
:
1288 assert(brw
->gen
>= 7);
1289 /* CBIT only supports UD type for dst. */
1290 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1292 case BRW_OPCODE_ADDC
:
1293 assert(brw
->gen
>= 7);
1294 brw_ADDC(p
, dst
, src
[0], src
[1]);
1296 case BRW_OPCODE_SUBB
:
1297 assert(brw
->gen
>= 7);
1298 brw_SUBB(p
, dst
, src
[0], src
[1]);
1300 case BRW_OPCODE_MAC
:
1301 brw_MAC(p
, dst
, src
[0], src
[1]);
1304 case BRW_OPCODE_BFE
:
1305 assert(brw
->gen
>= 7);
1306 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1309 case BRW_OPCODE_BFI1
:
1310 assert(brw
->gen
>= 7);
1311 brw_BFI1(p
, dst
, src
[0], src
[1]);
1313 case BRW_OPCODE_BFI2
:
1314 assert(brw
->gen
>= 7);
1315 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1319 if (inst
->src
[0].file
!= BAD_FILE
) {
1320 /* The instruction has an embedded compare (only allowed on gen6) */
1321 assert(brw
->gen
== 6);
1322 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1324 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1325 brw_inst_set_pred_control(brw
, if_inst
, inst
->predicate
);
1329 case BRW_OPCODE_ELSE
:
1332 case BRW_OPCODE_ENDIF
:
1337 brw_DO(p
, BRW_EXECUTE_8
);
1340 case BRW_OPCODE_BREAK
:
1342 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1344 case BRW_OPCODE_CONTINUE
:
1346 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1349 case BRW_OPCODE_WHILE
:
1354 case SHADER_OPCODE_RCP
:
1355 case SHADER_OPCODE_RSQ
:
1356 case SHADER_OPCODE_SQRT
:
1357 case SHADER_OPCODE_EXP2
:
1358 case SHADER_OPCODE_LOG2
:
1359 case SHADER_OPCODE_SIN
:
1360 case SHADER_OPCODE_COS
:
1361 if (brw
->gen
>= 7) {
1362 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1364 } else if (brw
->gen
== 6) {
1365 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1367 generate_math1_gen4(inst
, dst
, src
[0]);
1371 case SHADER_OPCODE_POW
:
1372 case SHADER_OPCODE_INT_QUOTIENT
:
1373 case SHADER_OPCODE_INT_REMAINDER
:
1374 if (brw
->gen
>= 7) {
1375 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1376 } else if (brw
->gen
== 6) {
1377 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1379 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1383 case SHADER_OPCODE_TEX
:
1384 case SHADER_OPCODE_TXD
:
1385 case SHADER_OPCODE_TXF
:
1386 case SHADER_OPCODE_TXF_CMS
:
1387 case SHADER_OPCODE_TXF_MCS
:
1388 case SHADER_OPCODE_TXL
:
1389 case SHADER_OPCODE_TXS
:
1390 case SHADER_OPCODE_TG4
:
1391 case SHADER_OPCODE_TG4_OFFSET
:
1392 generate_tex(inst
, dst
, src
[0], src
[1]);
1395 case VS_OPCODE_URB_WRITE
:
1396 generate_vs_urb_write(inst
);
1399 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1400 generate_scratch_read(inst
, dst
, src
[0]);
1403 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1404 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1407 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1408 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1411 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1412 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1415 case GS_OPCODE_URB_WRITE
:
1416 generate_gs_urb_write(inst
);
1419 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1420 generate_gs_urb_write_allocate(inst
);
1423 case GS_OPCODE_SVB_WRITE
:
1424 generate_gs_svb_write(inst
, dst
, src
[0], src
[1]);
1427 case GS_OPCODE_SVB_SET_DST_INDEX
:
1428 generate_gs_svb_set_destination_index(inst
, dst
, src
[0]);
1431 case GS_OPCODE_THREAD_END
:
1432 generate_gs_thread_end(inst
);
1435 case GS_OPCODE_SET_WRITE_OFFSET
:
1436 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1439 case GS_OPCODE_SET_VERTEX_COUNT
:
1440 generate_gs_set_vertex_count(dst
, src
[0]);
1443 case GS_OPCODE_FF_SYNC
:
1444 generate_gs_ff_sync(inst
, dst
, src
[0]);
1447 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1448 generate_gs_ff_sync_set_primitives(dst
, src
[0], src
[1], src
[2]);
1451 case GS_OPCODE_SET_PRIMITIVE_ID
:
1452 generate_gs_set_primitive_id(dst
);
1455 case GS_OPCODE_SET_DWORD_2
:
1456 generate_gs_set_dword_2(dst
, src
[0]);
1459 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1460 generate_gs_prepare_channel_masks(dst
);
1463 case GS_OPCODE_SET_CHANNEL_MASKS
:
1464 generate_gs_set_channel_masks(dst
, src
[0]);
1467 case GS_OPCODE_GET_INSTANCE_ID
:
1468 generate_gs_get_instance_id(dst
);
1471 case SHADER_OPCODE_SHADER_TIME_ADD
:
1472 brw_shader_time_add(p
, src
[0],
1473 prog_data
->base
.binding_table
.shader_time_start
);
1474 brw_mark_surface_used(&prog_data
->base
,
1475 prog_data
->base
.binding_table
.shader_time_start
);
1478 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1479 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1482 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1483 generate_untyped_surface_read(inst
, dst
, src
[0]);
1486 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1487 generate_unpack_flags(inst
, dst
);
1491 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1492 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1493 opcode_descs
[inst
->opcode
].name
);
1495 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1500 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1501 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1502 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1503 "emitting more than 1 instruction");
1505 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1507 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1508 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1509 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1514 annotation_finalize(&annotation
, p
->next_insn_offset
);
1516 int before_size
= p
->next_insn_offset
;
1517 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1518 int after_size
= p
->next_insn_offset
;
1520 if (unlikely(debug_flag
)) {
1522 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1523 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1526 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1528 fprintf(stderr
, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1529 " bytes (%.0f%%)\n",
1530 before_size
/ 16, loop_count
, before_size
, after_size
,
1531 100.0f
* (before_size
- after_size
) / before_size
);
1533 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
1534 ralloc_free(annotation
.ann
);
1539 vec4_generator::generate_assembly(const cfg_t
*cfg
,
1540 unsigned *assembly_size
)
1542 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1545 return brw_get_program(p
, assembly_size
);
1548 } /* namespace brw */