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i965/vec4: Silence unused parameter warnings
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include <ctype.h>
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26
27 extern "C" {
28 #include "brw_eu.h"
29 #include "main/macros.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
32 };
33
34 namespace brw {
35
36 struct brw_reg
37 vec4_instruction::get_dst(void)
38 {
39 struct brw_reg brw_reg;
40
41 switch (dst.file) {
42 case GRF:
43 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
44 brw_reg = retype(brw_reg, dst.type);
45 brw_reg.dw1.bits.writemask = dst.writemask;
46 break;
47
48 case MRF:
49 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
50 brw_reg = retype(brw_reg, dst.type);
51 brw_reg.dw1.bits.writemask = dst.writemask;
52 break;
53
54 case HW_REG:
55 assert(dst.type == dst.fixed_hw_reg.type);
56 brw_reg = dst.fixed_hw_reg;
57 break;
58
59 case BAD_FILE:
60 brw_reg = brw_null_reg();
61 break;
62
63 default:
64 unreachable("not reached");
65 }
66 return brw_reg;
67 }
68
69 struct brw_reg
70 vec4_instruction::get_src(const struct brw_vue_prog_data *prog_data, int i)
71 {
72 struct brw_reg brw_reg;
73
74 switch (src[i].file) {
75 case GRF:
76 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
77 brw_reg = retype(brw_reg, src[i].type);
78 brw_reg.dw1.bits.swizzle = src[i].swizzle;
79 if (src[i].abs)
80 brw_reg = brw_abs(brw_reg);
81 if (src[i].negate)
82 brw_reg = negate(brw_reg);
83 break;
84
85 case IMM:
86 switch (src[i].type) {
87 case BRW_REGISTER_TYPE_F:
88 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
89 break;
90 case BRW_REGISTER_TYPE_D:
91 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
92 break;
93 case BRW_REGISTER_TYPE_UD:
94 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
95 break;
96 case BRW_REGISTER_TYPE_VF:
97 brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
98 break;
99 default:
100 unreachable("not reached");
101 }
102 break;
103
104 case UNIFORM:
105 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
106 (src[i].reg + src[i].reg_offset) / 2,
107 ((src[i].reg + src[i].reg_offset) % 2) * 4),
108 0, 4, 1);
109 brw_reg = retype(brw_reg, src[i].type);
110 brw_reg.dw1.bits.swizzle = src[i].swizzle;
111 if (src[i].abs)
112 brw_reg = brw_abs(brw_reg);
113 if (src[i].negate)
114 brw_reg = negate(brw_reg);
115
116 /* This should have been moved to pull constants. */
117 assert(!src[i].reladdr);
118 break;
119
120 case HW_REG:
121 assert(src[i].type == src[i].fixed_hw_reg.type);
122 brw_reg = src[i].fixed_hw_reg;
123 break;
124
125 case BAD_FILE:
126 /* Probably unused. */
127 brw_reg = brw_null_reg();
128 break;
129 case ATTR:
130 default:
131 unreachable("not reached");
132 }
133
134 return brw_reg;
135 }
136
137 vec4_generator::vec4_generator(struct brw_context *brw,
138 struct gl_shader_program *shader_prog,
139 struct gl_program *prog,
140 struct brw_vue_prog_data *prog_data,
141 void *mem_ctx,
142 bool debug_flag,
143 const char *stage_name,
144 const char *stage_abbrev)
145 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
146 mem_ctx(mem_ctx), stage_name(stage_name), stage_abbrev(stage_abbrev),
147 debug_flag(debug_flag)
148 {
149 p = rzalloc(mem_ctx, struct brw_compile);
150 brw_init_compile(brw, p, mem_ctx);
151 }
152
153 vec4_generator::~vec4_generator()
154 {
155 }
156
157 void
158 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
159 struct brw_reg dst,
160 struct brw_reg src)
161 {
162 gen4_math(p,
163 dst,
164 brw_math_function(inst->opcode),
165 inst->base_mrf,
166 src,
167 BRW_MATH_PRECISION_FULL);
168 }
169
170 static void
171 check_gen6_math_src_arg(struct brw_reg src)
172 {
173 /* Source swizzles are ignored. */
174 assert(!src.abs);
175 assert(!src.negate);
176 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
177 }
178
179 void
180 vec4_generator::generate_math_gen6(vec4_instruction *inst,
181 struct brw_reg dst,
182 struct brw_reg src0,
183 struct brw_reg src1)
184 {
185 /* Can't do writemask because math can't be align16. */
186 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
187 /* Source swizzles are ignored. */
188 check_gen6_math_src_arg(src0);
189 if (src1.file == BRW_GENERAL_REGISTER_FILE)
190 check_gen6_math_src_arg(src1);
191
192 brw_set_default_access_mode(p, BRW_ALIGN_1);
193 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
194 brw_set_default_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
204 * "Message Payload":
205 *
206 * "Operand0[7]. For the INT DIV functions, this operand is the
207 * denominator."
208 * ...
209 * "Operand1[7]. For the INT DIV functions, this operand is the
210 * numerator."
211 */
212 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
213 struct brw_reg &op0 = is_int_div ? src1 : src0;
214 struct brw_reg &op1 = is_int_div ? src0 : src1;
215
216 brw_push_insn_state(p);
217 brw_set_default_saturate(p, false);
218 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
219 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
220 brw_pop_insn_state(p);
221
222 gen4_math(p,
223 dst,
224 brw_math_function(inst->opcode),
225 inst->base_mrf,
226 op0,
227 BRW_MATH_PRECISION_FULL);
228 }
229
230 void
231 vec4_generator::generate_tex(vec4_instruction *inst,
232 struct brw_reg dst,
233 struct brw_reg src,
234 struct brw_reg sampler_index)
235 {
236 int msg_type = -1;
237
238 if (brw->gen >= 5) {
239 switch (inst->opcode) {
240 case SHADER_OPCODE_TEX:
241 case SHADER_OPCODE_TXL:
242 if (inst->shadow_compare) {
243 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
244 } else {
245 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
246 }
247 break;
248 case SHADER_OPCODE_TXD:
249 if (inst->shadow_compare) {
250 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
251 assert(brw->gen >= 8 || brw->is_haswell);
252 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
253 } else {
254 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
255 }
256 break;
257 case SHADER_OPCODE_TXF:
258 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
259 break;
260 case SHADER_OPCODE_TXF_CMS:
261 if (brw->gen >= 7)
262 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
263 else
264 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
265 break;
266 case SHADER_OPCODE_TXF_MCS:
267 assert(brw->gen >= 7);
268 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
269 break;
270 case SHADER_OPCODE_TXS:
271 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
272 break;
273 case SHADER_OPCODE_TG4:
274 if (inst->shadow_compare) {
275 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
276 } else {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
278 }
279 break;
280 case SHADER_OPCODE_TG4_OFFSET:
281 if (inst->shadow_compare) {
282 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
283 } else {
284 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
285 }
286 break;
287 default:
288 unreachable("should not get here: invalid vec4 texture opcode");
289 }
290 } else {
291 switch (inst->opcode) {
292 case SHADER_OPCODE_TEX:
293 case SHADER_OPCODE_TXL:
294 if (inst->shadow_compare) {
295 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
296 assert(inst->mlen == 3);
297 } else {
298 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
299 assert(inst->mlen == 2);
300 }
301 break;
302 case SHADER_OPCODE_TXD:
303 /* There is no sample_d_c message; comparisons are done manually. */
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
305 assert(inst->mlen == 4);
306 break;
307 case SHADER_OPCODE_TXF:
308 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
309 assert(inst->mlen == 2);
310 break;
311 case SHADER_OPCODE_TXS:
312 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
313 assert(inst->mlen == 2);
314 break;
315 default:
316 unreachable("should not get here: invalid vec4 texture opcode");
317 }
318 }
319
320 assert(msg_type != -1);
321
322 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
323
324 /* Load the message header if present. If there's a texture offset, we need
325 * to set it up explicitly and load the offset bitfield. Otherwise, we can
326 * use an implied move from g0 to the first message register.
327 */
328 if (inst->header_present) {
329 if (brw->gen < 6 && !inst->offset) {
330 /* Set up an implied move from g0 to the MRF. */
331 src = brw_vec8_grf(0, 0);
332 } else {
333 struct brw_reg header =
334 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
335 uint32_t dw2 = 0;
336
337 /* Explicitly set up the message header by copying g0 to the MRF. */
338 brw_push_insn_state(p);
339 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
340 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
341
342 brw_set_default_access_mode(p, BRW_ALIGN_1);
343
344 if (inst->offset)
345 /* Set the texel offset bits in DWord 2. */
346 dw2 = inst->offset;
347
348 if (brw->gen >= 9)
349 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
350 * based on bit 22 in the header.
351 */
352 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
353
354 if (dw2)
355 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
356
357 brw_adjust_sampler_state_pointer(p, header, sampler_index);
358 brw_pop_insn_state(p);
359 }
360 }
361
362 uint32_t return_format;
363
364 switch (dst.type) {
365 case BRW_REGISTER_TYPE_D:
366 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
367 break;
368 case BRW_REGISTER_TYPE_UD:
369 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
370 break;
371 default:
372 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
373 break;
374 }
375
376 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
377 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
378 ? prog_data->base.binding_table.gather_texture_start
379 : prog_data->base.binding_table.texture_start;
380
381 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
382 uint32_t sampler = sampler_index.dw1.ud;
383
384 brw_SAMPLE(p,
385 dst,
386 inst->base_mrf,
387 src,
388 sampler + base_binding_table_index,
389 sampler % 16,
390 msg_type,
391 1, /* response length */
392 inst->mlen,
393 inst->header_present,
394 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
395 return_format);
396
397 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
398 } else {
399 /* Non-constant sampler index. */
400 /* Note: this clobbers `dst` as a temporary before emitting the send */
401
402 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
403 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
404
405 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
406
407 brw_push_insn_state(p);
408 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
409 brw_set_default_access_mode(p, BRW_ALIGN_1);
410
411 /* Some care required: `sampler` and `temp` may alias:
412 * addr = sampler & 0xff
413 * temp = (sampler << 8) & 0xf00
414 * addr = addr | temp
415 */
416 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
417 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
418 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
419 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
420 brw_OR(p, addr, addr, temp);
421
422 /* a0.0 |= <descriptor> */
423 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
424 brw_set_sampler_message(p, insn_or,
425 0 /* surface */,
426 0 /* sampler */,
427 msg_type,
428 1 /* rlen */,
429 inst->mlen /* mlen */,
430 inst->header_present /* header */,
431 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
432 return_format);
433 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
434 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
435 brw_set_src0(p, insn_or, addr);
436 brw_set_dest(p, insn_or, addr);
437
438
439 /* dst = send(offset, a0.0) */
440 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
441 brw_set_dest(p, insn_send, dst);
442 brw_set_src0(p, insn_send, src);
443 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
444
445 brw_pop_insn_state(p);
446
447 /* visitor knows more than we do about the surface limit required,
448 * so has already done marking.
449 */
450 }
451 }
452
453 void
454 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
455 {
456 brw_urb_WRITE(p,
457 brw_null_reg(), /* dest */
458 inst->base_mrf, /* starting mrf reg nr */
459 brw_vec8_grf(0, 0), /* src */
460 inst->urb_write_flags,
461 inst->mlen,
462 0, /* response len */
463 inst->offset, /* urb destination offset */
464 BRW_URB_SWIZZLE_INTERLEAVE);
465 }
466
467 void
468 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
469 {
470 struct brw_reg src = brw_message_reg(inst->base_mrf);
471 brw_urb_WRITE(p,
472 brw_null_reg(), /* dest */
473 inst->base_mrf, /* starting mrf reg nr */
474 src,
475 inst->urb_write_flags,
476 inst->mlen,
477 0, /* response len */
478 inst->offset, /* urb destination offset */
479 BRW_URB_SWIZZLE_INTERLEAVE);
480 }
481
482 void
483 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
484 {
485 struct brw_reg src = brw_message_reg(inst->base_mrf);
486
487 /* We pass the temporary passed in src0 as the writeback register */
488 brw_urb_WRITE(p,
489 inst->get_src(this->prog_data, 0), /* dest */
490 inst->base_mrf, /* starting mrf reg nr */
491 src,
492 BRW_URB_WRITE_ALLOCATE_COMPLETE,
493 inst->mlen,
494 1, /* response len */
495 inst->offset, /* urb destination offset */
496 BRW_URB_SWIZZLE_INTERLEAVE);
497
498 /* Now put allocated urb handle in dst.0 */
499 brw_push_insn_state(p);
500 brw_set_default_access_mode(p, BRW_ALIGN_1);
501 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
502 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
503 get_element_ud(inst->get_src(this->prog_data, 0), 0));
504 brw_set_default_access_mode(p, BRW_ALIGN_16);
505 brw_pop_insn_state(p);
506 }
507
508 void
509 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
510 {
511 struct brw_reg src = brw_message_reg(inst->base_mrf);
512 brw_urb_WRITE(p,
513 brw_null_reg(), /* dest */
514 inst->base_mrf, /* starting mrf reg nr */
515 src,
516 BRW_URB_WRITE_EOT | inst->urb_write_flags,
517 brw->gen >= 8 ? 2 : 1,/* message len */
518 0, /* response len */
519 0, /* urb destination offset */
520 BRW_URB_SWIZZLE_INTERLEAVE);
521 }
522
523 void
524 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
525 struct brw_reg src0,
526 struct brw_reg src1)
527 {
528 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
529 * Header: M0.3):
530 *
531 * Slot 0 Offset. This field, after adding to the Global Offset field
532 * in the message descriptor, specifies the offset (in 256-bit units)
533 * from the start of the URB entry, as referenced by URB Handle 0, at
534 * which the data will be accessed.
535 *
536 * Similar text describes DWORD M0.4, which is slot 1 offset.
537 *
538 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
539 * of the register for geometry shader invocations 0 and 1) by the
540 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
541 *
542 * We can do this with the following EU instruction:
543 *
544 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
545 */
546 brw_push_insn_state(p);
547 brw_set_default_access_mode(p, BRW_ALIGN_1);
548 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
549 assert(brw->gen >= 7 &&
550 src1.file == BRW_IMMEDIATE_VALUE &&
551 src1.type == BRW_REGISTER_TYPE_UD &&
552 src1.dw1.ud <= USHRT_MAX);
553 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
554 retype(src1, BRW_REGISTER_TYPE_UW));
555 brw_set_default_access_mode(p, BRW_ALIGN_16);
556 brw_pop_insn_state(p);
557 }
558
559 void
560 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
561 struct brw_reg src)
562 {
563 brw_push_insn_state(p);
564 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
565
566 if (brw->gen >= 8) {
567 /* Move the vertex count into the second MRF for the EOT write. */
568 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
569 src);
570 } else {
571 /* If we think of the src and dst registers as composed of 8 DWORDs each,
572 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
573 * them to WORDs, and then pack them into DWORD 2 of dst.
574 *
575 * It's easier to get the EU to do this if we think of the src and dst
576 * registers as composed of 16 WORDS each; then, we want to pick up the
577 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
578 * of dst.
579 *
580 * We can do that by the following EU instruction:
581 *
582 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
583 */
584 brw_set_default_access_mode(p, BRW_ALIGN_1);
585 brw_MOV(p,
586 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
587 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
588 brw_set_default_access_mode(p, BRW_ALIGN_16);
589 }
590 brw_pop_insn_state(p);
591 }
592
593 void
594 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
595 struct brw_reg dst,
596 struct brw_reg src0,
597 struct brw_reg src1)
598 {
599 int binding = inst->sol_binding;
600 bool final_write = inst->sol_final_write;
601
602 brw_push_insn_state(p);
603 /* Copy Vertex data into M0.x */
604 brw_MOV(p, stride(dst, 4, 4, 1),
605 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
606
607 /* Send SVB Write */
608 brw_svb_write(p,
609 final_write ? src1 : brw_null_reg(), /* dest == src1 */
610 1, /* msg_reg_nr */
611 dst, /* src0 == previous dst */
612 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
613 final_write); /* send_commit_msg */
614
615 /* Finally, wait for the write commit to occur so that we can proceed to
616 * other things safely.
617 *
618 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
619 *
620 * The write commit does not modify the destination register, but
621 * merely clears the dependency associated with the destination
622 * register. Thus, a simple “mov” instruction using the register as a
623 * source is sufficient to wait for the write commit to occur.
624 */
625 if (final_write) {
626 brw_MOV(p, src1, src1);
627 }
628 brw_pop_insn_state(p);
629 }
630
631 void
632 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
633 struct brw_reg dst,
634 struct brw_reg src)
635 {
636
637 int vertex = inst->sol_vertex;
638 brw_push_insn_state(p);
639 brw_set_default_access_mode(p, BRW_ALIGN_1);
640 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
641 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
642 brw_pop_insn_state(p);
643 }
644
645 void
646 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
647 {
648 brw_push_insn_state(p);
649 brw_set_default_access_mode(p, BRW_ALIGN_1);
650 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
651 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
652 brw_pop_insn_state(p);
653 }
654
655 void
656 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
657 {
658 /* We want to left shift just DWORD 4 (the x component belonging to the
659 * second geometry shader invocation) by 4 bits. So generate the
660 * instruction:
661 *
662 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
663 */
664 dst = suboffset(vec1(dst), 4);
665 brw_push_insn_state(p);
666 brw_set_default_access_mode(p, BRW_ALIGN_1);
667 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
668 brw_SHL(p, dst, dst, brw_imm_ud(4));
669 brw_pop_insn_state(p);
670 }
671
672 void
673 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
674 struct brw_reg src)
675 {
676 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
677 * Header: M0.5):
678 *
679 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
680 *
681 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
682 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
683 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
684 * channel enable to determine the final channel enable. For the
685 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
686 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
687 * in the writeback message. For the URB_WRITE_OWORD &
688 * URB_WRITE_HWORD messages, when final channel enable is 1 it
689 * indicates that Vertex 1 DATA [3] will be written to the surface.
690 *
691 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
692 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
693 *
694 * 14 Vertex 1 DATA [2] Channel Mask
695 * 13 Vertex 1 DATA [1] Channel Mask
696 * 12 Vertex 1 DATA [0] Channel Mask
697 * 11 Vertex 0 DATA [3] Channel Mask
698 * 10 Vertex 0 DATA [2] Channel Mask
699 * 9 Vertex 0 DATA [1] Channel Mask
700 * 8 Vertex 0 DATA [0] Channel Mask
701 *
702 * (This is from a section of the PRM that is agnostic to the particular
703 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
704 * geometry shader invocations 0 and 1, respectively). Since we have the
705 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
706 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
707 * DWORD 4, we just need to OR them together and store the result in bits
708 * 15:8 of DWORD 5.
709 *
710 * It's easier to get the EU to do this if we think of the src and dst
711 * registers as composed of 32 bytes each; then, we want to pick up the
712 * contents of bytes 0 and 16 from src, OR them together, and store them in
713 * byte 21.
714 *
715 * We can do that by the following EU instruction:
716 *
717 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
718 *
719 * Note: this relies on the source register having zeros in (a) bits 7:4 of
720 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
721 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
722 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
723 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
724 * contain valid channel mask values (which are in the range 0x0-0xf).
725 */
726 dst = retype(dst, BRW_REGISTER_TYPE_UB);
727 src = retype(src, BRW_REGISTER_TYPE_UB);
728 brw_push_insn_state(p);
729 brw_set_default_access_mode(p, BRW_ALIGN_1);
730 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
731 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
732 brw_pop_insn_state(p);
733 }
734
735 void
736 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
737 {
738 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
739 * and store into dst.0 & dst.4. So generate the instruction:
740 *
741 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
742 */
743 brw_push_insn_state(p);
744 brw_set_default_access_mode(p, BRW_ALIGN_1);
745 dst = retype(dst, BRW_REGISTER_TYPE_UD);
746 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
747 brw_SHR(p, dst, stride(r0, 1, 4, 0),
748 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
749 brw_pop_insn_state(p);
750 }
751
752 void
753 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
754 struct brw_reg src0,
755 struct brw_reg src1,
756 struct brw_reg src2)
757 {
758 brw_push_insn_state(p);
759 brw_set_default_access_mode(p, BRW_ALIGN_1);
760 /* Save src0 data in 16:31 bits of dst.0 */
761 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
762 brw_imm_ud(0xffffu));
763 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
764 /* Save src1 data in 0:15 bits of dst.0 */
765 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
766 brw_imm_ud(0xffffu));
767 brw_OR(p, suboffset(vec1(dst), 0),
768 suboffset(vec1(dst), 0),
769 suboffset(vec1(src2), 0));
770 brw_pop_insn_state(p);
771 }
772
773 void
774 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
775 struct brw_reg dst,
776 struct brw_reg src0,
777 struct brw_reg src1)
778 {
779 /* This opcode uses an implied MRF register for:
780 * - the header of the ff_sync message. And as such it is expected to be
781 * initialized to r0 before calling here.
782 * - the destination where we will write the allocated URB handle.
783 */
784 struct brw_reg header =
785 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
786
787 /* Overwrite dword 0 of the header (SO vertices to write) and
788 * dword 1 (number of primitives written).
789 */
790 brw_push_insn_state(p);
791 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
792 brw_set_default_access_mode(p, BRW_ALIGN_1);
793 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
794 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
795 brw_pop_insn_state(p);
796
797 /* Allocate URB handle in dst */
798 brw_ff_sync(p,
799 dst,
800 0,
801 header,
802 1, /* allocate */
803 1, /* response length */
804 0 /* eot */);
805
806 /* Now put allocated urb handle in header.0 */
807 brw_push_insn_state(p);
808 brw_set_default_access_mode(p, BRW_ALIGN_1);
809 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
810 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
811
812 /* src1 is not an immediate when we use transform feedback */
813 if (src1.file != BRW_IMMEDIATE_VALUE)
814 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
815
816 brw_pop_insn_state(p);
817 }
818
819 void
820 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
821 {
822 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
823 struct brw_reg src = brw_vec8_grf(0, 0);
824 brw_push_insn_state(p);
825 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
826 brw_set_default_access_mode(p, BRW_ALIGN_1);
827 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
828 brw_pop_insn_state(p);
829 }
830
831 void
832 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
833 struct brw_reg index)
834 {
835 int second_vertex_offset;
836
837 if (brw->gen >= 6)
838 second_vertex_offset = 1;
839 else
840 second_vertex_offset = 16;
841
842 m1 = retype(m1, BRW_REGISTER_TYPE_D);
843
844 /* Set up M1 (message payload). Only the block offsets in M1.0 and
845 * M1.4 are used, and the rest are ignored.
846 */
847 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
848 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
849 struct brw_reg index_0 = suboffset(vec1(index), 0);
850 struct brw_reg index_4 = suboffset(vec1(index), 4);
851
852 brw_push_insn_state(p);
853 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
854 brw_set_default_access_mode(p, BRW_ALIGN_1);
855
856 brw_MOV(p, m1_0, index_0);
857
858 if (index.file == BRW_IMMEDIATE_VALUE) {
859 index_4.dw1.ud += second_vertex_offset;
860 brw_MOV(p, m1_4, index_4);
861 } else {
862 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
863 }
864
865 brw_pop_insn_state(p);
866 }
867
868 void
869 vec4_generator::generate_unpack_flags(struct brw_reg dst)
870 {
871 brw_push_insn_state(p);
872 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
873 brw_set_default_access_mode(p, BRW_ALIGN_1);
874
875 struct brw_reg flags = brw_flag_reg(0, 0);
876 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
877 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
878
879 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
880 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
881 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
882
883 brw_pop_insn_state(p);
884 }
885
886 void
887 vec4_generator::generate_scratch_read(vec4_instruction *inst,
888 struct brw_reg dst,
889 struct brw_reg index)
890 {
891 struct brw_reg header = brw_vec8_grf(0, 0);
892
893 gen6_resolve_implied_move(p, &header, inst->base_mrf);
894
895 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
896 index);
897
898 uint32_t msg_type;
899
900 if (brw->gen >= 6)
901 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
902 else if (brw->gen == 5 || brw->is_g4x)
903 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
904 else
905 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
906
907 /* Each of the 8 channel enables is considered for whether each
908 * dword is written.
909 */
910 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
911 brw_set_dest(p, send, dst);
912 brw_set_src0(p, send, header);
913 if (brw->gen < 6)
914 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
915 brw_set_dp_read_message(p, send,
916 255, /* binding table index: stateless access */
917 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
918 msg_type,
919 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
920 2, /* mlen */
921 true, /* header_present */
922 1 /* rlen */);
923 }
924
925 void
926 vec4_generator::generate_scratch_write(vec4_instruction *inst,
927 struct brw_reg dst,
928 struct brw_reg src,
929 struct brw_reg index)
930 {
931 struct brw_reg header = brw_vec8_grf(0, 0);
932 bool write_commit;
933
934 /* If the instruction is predicated, we'll predicate the send, not
935 * the header setup.
936 */
937 brw_set_default_predicate_control(p, false);
938
939 gen6_resolve_implied_move(p, &header, inst->base_mrf);
940
941 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
942 index);
943
944 brw_MOV(p,
945 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
946 retype(src, BRW_REGISTER_TYPE_D));
947
948 uint32_t msg_type;
949
950 if (brw->gen >= 7)
951 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
952 else if (brw->gen == 6)
953 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
954 else
955 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
956
957 brw_set_default_predicate_control(p, inst->predicate);
958
959 /* Pre-gen6, we have to specify write commits to ensure ordering
960 * between reads and writes within a thread. Afterwards, that's
961 * guaranteed and write commits only matter for inter-thread
962 * synchronization.
963 */
964 if (brw->gen >= 6) {
965 write_commit = false;
966 } else {
967 /* The visitor set up our destination register to be g0. This
968 * means that when the next read comes along, we will end up
969 * reading from g0 and causing a block on the write commit. For
970 * write-after-read, we are relying on the value of the previous
971 * read being used (and thus blocking on completion) before our
972 * write is executed. This means we have to be careful in
973 * instruction scheduling to not violate this assumption.
974 */
975 write_commit = true;
976 }
977
978 /* Each of the 8 channel enables is considered for whether each
979 * dword is written.
980 */
981 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
982 brw_set_dest(p, send, dst);
983 brw_set_src0(p, send, header);
984 if (brw->gen < 6)
985 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
986 brw_set_dp_write_message(p, send,
987 255, /* binding table index: stateless access */
988 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
989 msg_type,
990 3, /* mlen */
991 true, /* header present */
992 false, /* not a render target write */
993 write_commit, /* rlen */
994 false, /* eot */
995 write_commit);
996 }
997
998 void
999 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
1000 struct brw_reg dst,
1001 struct brw_reg index,
1002 struct brw_reg offset)
1003 {
1004 assert(index.file == BRW_IMMEDIATE_VALUE &&
1005 index.type == BRW_REGISTER_TYPE_UD);
1006 uint32_t surf_index = index.dw1.ud;
1007
1008 struct brw_reg header = brw_vec8_grf(0, 0);
1009
1010 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1011
1012 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
1013 offset);
1014
1015 uint32_t msg_type;
1016
1017 if (brw->gen >= 6)
1018 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1019 else if (brw->gen == 5 || brw->is_g4x)
1020 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1021 else
1022 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1023
1024 /* Each of the 8 channel enables is considered for whether each
1025 * dword is written.
1026 */
1027 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1028 brw_set_dest(p, send, dst);
1029 brw_set_src0(p, send, header);
1030 if (brw->gen < 6)
1031 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
1032 brw_set_dp_read_message(p, send,
1033 surf_index,
1034 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1035 msg_type,
1036 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1037 2, /* mlen */
1038 true, /* header_present */
1039 1 /* rlen */);
1040
1041 brw_mark_surface_used(&prog_data->base, surf_index);
1042 }
1043
1044 void
1045 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1046 struct brw_reg dst,
1047 struct brw_reg surf_index,
1048 struct brw_reg offset)
1049 {
1050 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1051
1052 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1053
1054 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1055 brw_set_dest(p, insn, dst);
1056 brw_set_src0(p, insn, offset);
1057 brw_set_sampler_message(p, insn,
1058 surf_index.dw1.ud,
1059 0, /* LD message ignores sampler unit */
1060 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1061 1, /* rlen */
1062 1, /* mlen */
1063 false, /* no header */
1064 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1065 0);
1066
1067 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1068
1069 } else {
1070
1071 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1072
1073 brw_push_insn_state(p);
1074 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1075 brw_set_default_access_mode(p, BRW_ALIGN_1);
1076
1077 /* a0.0 = surf_index & 0xff */
1078 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1079 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1080 brw_set_dest(p, insn_and, addr);
1081 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1082 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1083
1084
1085 /* a0.0 |= <descriptor> */
1086 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1087 brw_set_sampler_message(p, insn_or,
1088 0 /* surface */,
1089 0 /* sampler */,
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1091 1 /* rlen */,
1092 1 /* mlen */,
1093 false /* header */,
1094 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1095 0);
1096 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1097 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1098 brw_set_src0(p, insn_or, addr);
1099 brw_set_dest(p, insn_or, addr);
1100
1101
1102 /* dst = send(offset, a0.0) */
1103 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1104 brw_set_dest(p, insn_send, dst);
1105 brw_set_src0(p, insn_send, offset);
1106 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1107
1108 brw_pop_insn_state(p);
1109
1110 /* visitor knows more than we do about the surface limit required,
1111 * so has already done marking.
1112 */
1113 }
1114 }
1115
1116 void
1117 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1118 struct brw_reg dst,
1119 struct brw_reg atomic_op,
1120 struct brw_reg surf_index)
1121 {
1122 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1123 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1124 surf_index.file == BRW_IMMEDIATE_VALUE &&
1125 surf_index.type == BRW_REGISTER_TYPE_UD);
1126
1127 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1128 atomic_op.dw1.ud, surf_index.dw1.ud,
1129 inst->mlen, 1);
1130
1131 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1132 }
1133
1134 void
1135 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1136 struct brw_reg dst,
1137 struct brw_reg surf_index)
1138 {
1139 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1140 surf_index.type == BRW_REGISTER_TYPE_UD);
1141
1142 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1143 surf_index.dw1.ud,
1144 inst->mlen, 1);
1145
1146 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1147 }
1148
1149 void
1150 vec4_generator::generate_code(const cfg_t *cfg)
1151 {
1152 struct annotation_info annotation;
1153 memset(&annotation, 0, sizeof(annotation));
1154 int loop_count = 0;
1155
1156 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1157 struct brw_reg src[3], dst;
1158
1159 if (unlikely(debug_flag))
1160 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1161
1162 for (unsigned int i = 0; i < 3; i++) {
1163 src[i] = inst->get_src(this->prog_data, i);
1164 }
1165 dst = inst->get_dst();
1166
1167 brw_set_default_predicate_control(p, inst->predicate);
1168 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1169 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1170 brw_set_default_saturate(p, inst->saturate);
1171 brw_set_default_mask_control(p, inst->force_writemask_all);
1172 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1173
1174 unsigned pre_emit_nr_insn = p->nr_insn;
1175
1176 if (dst.width == BRW_WIDTH_4) {
1177 /* This happens in attribute fixups for "dual instanced" geometry
1178 * shaders, since they use attributes that are vec4's. Since the exec
1179 * width is only 4, it's essential that the caller set
1180 * force_writemask_all in order to make sure the instruction is executed
1181 * regardless of which channels are enabled.
1182 */
1183 assert(inst->force_writemask_all);
1184
1185 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1186 * the following register region restrictions (from Graphics BSpec:
1187 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1188 * > Register Region Restrictions)
1189 *
1190 * 1. ExecSize must be greater than or equal to Width.
1191 *
1192 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1193 * to Width * HorzStride."
1194 */
1195 for (int i = 0; i < 3; i++) {
1196 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1197 src[i] = stride(src[i], 4, 4, 1);
1198 }
1199 }
1200
1201 switch (inst->opcode) {
1202 case VEC4_OPCODE_UNPACK_UNIFORM:
1203 case BRW_OPCODE_MOV:
1204 brw_MOV(p, dst, src[0]);
1205 break;
1206 case BRW_OPCODE_ADD:
1207 brw_ADD(p, dst, src[0], src[1]);
1208 break;
1209 case BRW_OPCODE_MUL:
1210 brw_MUL(p, dst, src[0], src[1]);
1211 break;
1212 case BRW_OPCODE_MACH:
1213 brw_MACH(p, dst, src[0], src[1]);
1214 break;
1215
1216 case BRW_OPCODE_MAD:
1217 assert(brw->gen >= 6);
1218 brw_MAD(p, dst, src[0], src[1], src[2]);
1219 break;
1220
1221 case BRW_OPCODE_FRC:
1222 brw_FRC(p, dst, src[0]);
1223 break;
1224 case BRW_OPCODE_RNDD:
1225 brw_RNDD(p, dst, src[0]);
1226 break;
1227 case BRW_OPCODE_RNDE:
1228 brw_RNDE(p, dst, src[0]);
1229 break;
1230 case BRW_OPCODE_RNDZ:
1231 brw_RNDZ(p, dst, src[0]);
1232 break;
1233
1234 case BRW_OPCODE_AND:
1235 brw_AND(p, dst, src[0], src[1]);
1236 break;
1237 case BRW_OPCODE_OR:
1238 brw_OR(p, dst, src[0], src[1]);
1239 break;
1240 case BRW_OPCODE_XOR:
1241 brw_XOR(p, dst, src[0], src[1]);
1242 break;
1243 case BRW_OPCODE_NOT:
1244 brw_NOT(p, dst, src[0]);
1245 break;
1246 case BRW_OPCODE_ASR:
1247 brw_ASR(p, dst, src[0], src[1]);
1248 break;
1249 case BRW_OPCODE_SHR:
1250 brw_SHR(p, dst, src[0], src[1]);
1251 break;
1252 case BRW_OPCODE_SHL:
1253 brw_SHL(p, dst, src[0], src[1]);
1254 break;
1255
1256 case BRW_OPCODE_CMP:
1257 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1258 break;
1259 case BRW_OPCODE_SEL:
1260 brw_SEL(p, dst, src[0], src[1]);
1261 break;
1262
1263 case BRW_OPCODE_DPH:
1264 brw_DPH(p, dst, src[0], src[1]);
1265 break;
1266
1267 case BRW_OPCODE_DP4:
1268 brw_DP4(p, dst, src[0], src[1]);
1269 break;
1270
1271 case BRW_OPCODE_DP3:
1272 brw_DP3(p, dst, src[0], src[1]);
1273 break;
1274
1275 case BRW_OPCODE_DP2:
1276 brw_DP2(p, dst, src[0], src[1]);
1277 break;
1278
1279 case BRW_OPCODE_F32TO16:
1280 assert(brw->gen >= 7);
1281 brw_F32TO16(p, dst, src[0]);
1282 break;
1283
1284 case BRW_OPCODE_F16TO32:
1285 assert(brw->gen >= 7);
1286 brw_F16TO32(p, dst, src[0]);
1287 break;
1288
1289 case BRW_OPCODE_LRP:
1290 assert(brw->gen >= 6);
1291 brw_LRP(p, dst, src[0], src[1], src[2]);
1292 break;
1293
1294 case BRW_OPCODE_BFREV:
1295 assert(brw->gen >= 7);
1296 /* BFREV only supports UD type for src and dst. */
1297 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1298 retype(src[0], BRW_REGISTER_TYPE_UD));
1299 break;
1300 case BRW_OPCODE_FBH:
1301 assert(brw->gen >= 7);
1302 /* FBH only supports UD type for dst. */
1303 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1304 break;
1305 case BRW_OPCODE_FBL:
1306 assert(brw->gen >= 7);
1307 /* FBL only supports UD type for dst. */
1308 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1309 break;
1310 case BRW_OPCODE_CBIT:
1311 assert(brw->gen >= 7);
1312 /* CBIT only supports UD type for dst. */
1313 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1314 break;
1315 case BRW_OPCODE_ADDC:
1316 assert(brw->gen >= 7);
1317 brw_ADDC(p, dst, src[0], src[1]);
1318 break;
1319 case BRW_OPCODE_SUBB:
1320 assert(brw->gen >= 7);
1321 brw_SUBB(p, dst, src[0], src[1]);
1322 break;
1323 case BRW_OPCODE_MAC:
1324 brw_MAC(p, dst, src[0], src[1]);
1325 break;
1326
1327 case BRW_OPCODE_BFE:
1328 assert(brw->gen >= 7);
1329 brw_BFE(p, dst, src[0], src[1], src[2]);
1330 break;
1331
1332 case BRW_OPCODE_BFI1:
1333 assert(brw->gen >= 7);
1334 brw_BFI1(p, dst, src[0], src[1]);
1335 break;
1336 case BRW_OPCODE_BFI2:
1337 assert(brw->gen >= 7);
1338 brw_BFI2(p, dst, src[0], src[1], src[2]);
1339 break;
1340
1341 case BRW_OPCODE_IF:
1342 if (inst->src[0].file != BAD_FILE) {
1343 /* The instruction has an embedded compare (only allowed on gen6) */
1344 assert(brw->gen == 6);
1345 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1346 } else {
1347 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1348 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1349 }
1350 break;
1351
1352 case BRW_OPCODE_ELSE:
1353 brw_ELSE(p);
1354 break;
1355 case BRW_OPCODE_ENDIF:
1356 brw_ENDIF(p);
1357 break;
1358
1359 case BRW_OPCODE_DO:
1360 brw_DO(p, BRW_EXECUTE_8);
1361 break;
1362
1363 case BRW_OPCODE_BREAK:
1364 brw_BREAK(p);
1365 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1366 break;
1367 case BRW_OPCODE_CONTINUE:
1368 brw_CONT(p);
1369 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1370 break;
1371
1372 case BRW_OPCODE_WHILE:
1373 brw_WHILE(p);
1374 loop_count++;
1375 break;
1376
1377 case SHADER_OPCODE_RCP:
1378 case SHADER_OPCODE_RSQ:
1379 case SHADER_OPCODE_SQRT:
1380 case SHADER_OPCODE_EXP2:
1381 case SHADER_OPCODE_LOG2:
1382 case SHADER_OPCODE_SIN:
1383 case SHADER_OPCODE_COS:
1384 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1385 if (brw->gen >= 7) {
1386 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1387 brw_null_reg());
1388 } else if (brw->gen == 6) {
1389 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1390 } else {
1391 generate_math1_gen4(inst, dst, src[0]);
1392 }
1393 break;
1394
1395 case SHADER_OPCODE_POW:
1396 case SHADER_OPCODE_INT_QUOTIENT:
1397 case SHADER_OPCODE_INT_REMAINDER:
1398 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1399 if (brw->gen >= 7) {
1400 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1401 } else if (brw->gen == 6) {
1402 generate_math_gen6(inst, dst, src[0], src[1]);
1403 } else {
1404 generate_math2_gen4(inst, dst, src[0], src[1]);
1405 }
1406 break;
1407
1408 case SHADER_OPCODE_TEX:
1409 case SHADER_OPCODE_TXD:
1410 case SHADER_OPCODE_TXF:
1411 case SHADER_OPCODE_TXF_CMS:
1412 case SHADER_OPCODE_TXF_MCS:
1413 case SHADER_OPCODE_TXL:
1414 case SHADER_OPCODE_TXS:
1415 case SHADER_OPCODE_TG4:
1416 case SHADER_OPCODE_TG4_OFFSET:
1417 generate_tex(inst, dst, src[0], src[1]);
1418 break;
1419
1420 case VS_OPCODE_URB_WRITE:
1421 generate_vs_urb_write(inst);
1422 break;
1423
1424 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1425 generate_scratch_read(inst, dst, src[0]);
1426 break;
1427
1428 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1429 generate_scratch_write(inst, dst, src[0], src[1]);
1430 break;
1431
1432 case VS_OPCODE_PULL_CONSTANT_LOAD:
1433 generate_pull_constant_load(inst, dst, src[0], src[1]);
1434 break;
1435
1436 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1437 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1438 break;
1439
1440 case GS_OPCODE_URB_WRITE:
1441 generate_gs_urb_write(inst);
1442 break;
1443
1444 case GS_OPCODE_URB_WRITE_ALLOCATE:
1445 generate_gs_urb_write_allocate(inst);
1446 break;
1447
1448 case GS_OPCODE_SVB_WRITE:
1449 generate_gs_svb_write(inst, dst, src[0], src[1]);
1450 break;
1451
1452 case GS_OPCODE_SVB_SET_DST_INDEX:
1453 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1454 break;
1455
1456 case GS_OPCODE_THREAD_END:
1457 generate_gs_thread_end(inst);
1458 break;
1459
1460 case GS_OPCODE_SET_WRITE_OFFSET:
1461 generate_gs_set_write_offset(dst, src[0], src[1]);
1462 break;
1463
1464 case GS_OPCODE_SET_VERTEX_COUNT:
1465 generate_gs_set_vertex_count(dst, src[0]);
1466 break;
1467
1468 case GS_OPCODE_FF_SYNC:
1469 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1470 break;
1471
1472 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1473 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1474 break;
1475
1476 case GS_OPCODE_SET_PRIMITIVE_ID:
1477 generate_gs_set_primitive_id(dst);
1478 break;
1479
1480 case GS_OPCODE_SET_DWORD_2:
1481 generate_gs_set_dword_2(dst, src[0]);
1482 break;
1483
1484 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1485 generate_gs_prepare_channel_masks(dst);
1486 break;
1487
1488 case GS_OPCODE_SET_CHANNEL_MASKS:
1489 generate_gs_set_channel_masks(dst, src[0]);
1490 break;
1491
1492 case GS_OPCODE_GET_INSTANCE_ID:
1493 generate_gs_get_instance_id(dst);
1494 break;
1495
1496 case SHADER_OPCODE_SHADER_TIME_ADD:
1497 brw_shader_time_add(p, src[0],
1498 prog_data->base.binding_table.shader_time_start);
1499 brw_mark_surface_used(&prog_data->base,
1500 prog_data->base.binding_table.shader_time_start);
1501 break;
1502
1503 case SHADER_OPCODE_UNTYPED_ATOMIC:
1504 generate_untyped_atomic(inst, dst, src[0], src[1]);
1505 break;
1506
1507 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1508 generate_untyped_surface_read(inst, dst, src[0]);
1509 break;
1510
1511 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1512 generate_unpack_flags(dst);
1513 break;
1514
1515 case VEC4_OPCODE_PACK_BYTES: {
1516 /* Is effectively:
1517 *
1518 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1519 *
1520 * but destinations' only regioning is horizontal stride, so instead we
1521 * have to use two instructions:
1522 *
1523 * mov(4) dst<1>:UB src<4,1,0>:UB
1524 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1525 *
1526 * where they pack the four bytes from the low and high four DW.
1527 */
1528 assert(is_power_of_two(dst.dw1.bits.writemask) &&
1529 dst.dw1.bits.writemask != 0);
1530 unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
1531
1532 dst.type = BRW_REGISTER_TYPE_UB;
1533
1534 brw_set_default_access_mode(p, BRW_ALIGN_1);
1535
1536 src[0].type = BRW_REGISTER_TYPE_UB;
1537 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1538 src[0].width = BRW_WIDTH_1;
1539 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1540 dst.subnr = offset * 4;
1541 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1542 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1543 brw_inst_set_no_dd_clear(brw, insn, true);
1544 brw_inst_set_no_dd_check(brw, insn, inst->no_dd_check);
1545
1546 src[0].subnr = 16;
1547 dst.subnr = 16 + offset * 4;
1548 insn = brw_MOV(p, dst, src[0]);
1549 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1550 brw_inst_set_no_dd_clear(brw, insn, inst->no_dd_clear);
1551 brw_inst_set_no_dd_check(brw, insn, true);
1552
1553 brw_set_default_access_mode(p, BRW_ALIGN_16);
1554 break;
1555 }
1556
1557 default:
1558 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1559 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1560 opcode_descs[inst->opcode].name);
1561 } else {
1562 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1563 }
1564 abort();
1565 }
1566
1567 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1568 /* Handled dependency hints in the generator. */
1569
1570 assert(!inst->conditional_mod);
1571 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1572 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1573 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1574 "emitting more than 1 instruction");
1575
1576 brw_inst *last = &p->store[pre_emit_nr_insn];
1577
1578 if (inst->conditional_mod)
1579 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1580 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1581 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1582 }
1583 }
1584
1585 brw_set_uip_jip(p);
1586 annotation_finalize(&annotation, p->next_insn_offset);
1587
1588 int before_size = p->next_insn_offset;
1589 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1590 int after_size = p->next_insn_offset;
1591
1592 if (unlikely(debug_flag)) {
1593 if (shader_prog) {
1594 fprintf(stderr, "Native code for %s %s shader %d:\n",
1595 shader_prog->Label ? shader_prog->Label : "unnamed",
1596 stage_name, shader_prog->Name);
1597 } else {
1598 fprintf(stderr, "Native code for %s program %d:\n", stage_name,
1599 prog->Id);
1600 }
1601 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1602 " bytes (%.0f%%)\n",
1603 stage_abbrev,
1604 before_size / 16, loop_count, before_size, after_size,
1605 100.0f * (before_size - after_size) / before_size);
1606
1607 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1608 ralloc_free(annotation.ann);
1609 }
1610
1611 static GLuint msg_id = 0;
1612 _mesa_gl_debug(&brw->ctx, &msg_id,
1613 MESA_DEBUG_SOURCE_SHADER_COMPILER,
1614 MESA_DEBUG_TYPE_OTHER,
1615 MESA_DEBUG_SEVERITY_NOTIFICATION,
1616 "%s vec4 shader: %d inst, %d loops, "
1617 "compacted %d to %d bytes.\n",
1618 stage_abbrev,
1619 before_size / 16, loop_count,
1620 before_size, after_size);
1621 }
1622
1623 const unsigned *
1624 vec4_generator::generate_assembly(const cfg_t *cfg,
1625 unsigned *assembly_size)
1626 {
1627 brw_set_default_access_mode(p, BRW_ALIGN_16);
1628 generate_code(cfg);
1629
1630 return brw_get_program(p, assembly_size);
1631 }
1632
1633 } /* namespace brw */