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i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 default:
96 unreachable("not reached");
97 }
98 break;
99
100 case UNIFORM:
101 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
102 (src[i].reg + src[i].reg_offset) / 2,
103 ((src[i].reg + src[i].reg_offset) % 2) * 4),
104 0, 4, 1);
105 brw_reg = retype(brw_reg, src[i].type);
106 brw_reg.dw1.bits.swizzle = src[i].swizzle;
107 if (src[i].abs)
108 brw_reg = brw_abs(brw_reg);
109 if (src[i].negate)
110 brw_reg = negate(brw_reg);
111
112 /* This should have been moved to pull constants. */
113 assert(!src[i].reladdr);
114 break;
115
116 case HW_REG:
117 assert(src[i].type == src[i].fixed_hw_reg.type);
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 unreachable("not reached");
128 }
129
130 return brw_reg;
131 }
132
133 vec4_generator::vec4_generator(struct brw_context *brw,
134 struct gl_shader_program *shader_prog,
135 struct gl_program *prog,
136 struct brw_vec4_prog_data *prog_data,
137 void *mem_ctx,
138 bool debug_flag)
139 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
140 mem_ctx(mem_ctx), debug_flag(debug_flag)
141 {
142 p = rzalloc(mem_ctx, struct brw_compile);
143 brw_init_compile(brw, p, mem_ctx);
144 }
145
146 vec4_generator::~vec4_generator()
147 {
148 }
149
150 void
151 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
152 struct brw_reg dst,
153 struct brw_reg src)
154 {
155 gen4_math(p,
156 dst,
157 brw_math_function(inst->opcode),
158 inst->base_mrf,
159 src,
160 BRW_MATH_DATA_VECTOR,
161 BRW_MATH_PRECISION_FULL);
162 }
163
164 static void
165 check_gen6_math_src_arg(struct brw_reg src)
166 {
167 /* Source swizzles are ignored. */
168 assert(!src.abs);
169 assert(!src.negate);
170 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
171 }
172
173 void
174 vec4_generator::generate_math_gen6(vec4_instruction *inst,
175 struct brw_reg dst,
176 struct brw_reg src0,
177 struct brw_reg src1)
178 {
179 /* Can't do writemask because math can't be align16. */
180 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0);
183 if (src1.file == BRW_GENERAL_REGISTER_FILE)
184 check_gen6_math_src_arg(src1);
185
186 brw_set_default_access_mode(p, BRW_ALIGN_1);
187 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
188 brw_set_default_access_mode(p, BRW_ALIGN_16);
189 }
190
191 void
192 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
193 struct brw_reg dst,
194 struct brw_reg src0,
195 struct brw_reg src1)
196 {
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
198 * "Message Payload":
199 *
200 * "Operand0[7]. For the INT DIV functions, this operand is the
201 * denominator."
202 * ...
203 * "Operand1[7]. For the INT DIV functions, this operand is the
204 * numerator."
205 */
206 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
207 struct brw_reg &op0 = is_int_div ? src1 : src0;
208 struct brw_reg &op1 = is_int_div ? src0 : src1;
209
210 brw_push_insn_state(p);
211 brw_set_default_saturate(p, false);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
214 brw_pop_insn_state(p);
215
216 gen4_math(p,
217 dst,
218 brw_math_function(inst->opcode),
219 inst->base_mrf,
220 op0,
221 BRW_MATH_DATA_VECTOR,
222 BRW_MATH_PRECISION_FULL);
223 }
224
225 void
226 vec4_generator::generate_tex(vec4_instruction *inst,
227 struct brw_reg dst,
228 struct brw_reg src,
229 struct brw_reg sampler_index)
230 {
231 int msg_type = -1;
232
233 if (brw->gen >= 5) {
234 switch (inst->opcode) {
235 case SHADER_OPCODE_TEX:
236 case SHADER_OPCODE_TXL:
237 if (inst->shadow_compare) {
238 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
239 } else {
240 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
241 }
242 break;
243 case SHADER_OPCODE_TXD:
244 if (inst->shadow_compare) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw->gen >= 8 || brw->is_haswell);
247 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
248 } else {
249 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
250 }
251 break;
252 case SHADER_OPCODE_TXF:
253 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
254 break;
255 case SHADER_OPCODE_TXF_CMS:
256 if (brw->gen >= 7)
257 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
258 else
259 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
260 break;
261 case SHADER_OPCODE_TXF_MCS:
262 assert(brw->gen >= 7);
263 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
264 break;
265 case SHADER_OPCODE_TXS:
266 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
267 break;
268 case SHADER_OPCODE_TG4:
269 if (inst->shadow_compare) {
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
271 } else {
272 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
273 }
274 break;
275 case SHADER_OPCODE_TG4_OFFSET:
276 if (inst->shadow_compare) {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
278 } else {
279 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
280 }
281 break;
282 default:
283 unreachable("should not get here: invalid vec4 texture opcode");
284 }
285 } else {
286 switch (inst->opcode) {
287 case SHADER_OPCODE_TEX:
288 case SHADER_OPCODE_TXL:
289 if (inst->shadow_compare) {
290 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
291 assert(inst->mlen == 3);
292 } else {
293 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
294 assert(inst->mlen == 2);
295 }
296 break;
297 case SHADER_OPCODE_TXD:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
300 assert(inst->mlen == 4);
301 break;
302 case SHADER_OPCODE_TXF:
303 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
304 assert(inst->mlen == 2);
305 break;
306 case SHADER_OPCODE_TXS:
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
308 assert(inst->mlen == 2);
309 break;
310 default:
311 unreachable("should not get here: invalid vec4 texture opcode");
312 }
313 }
314
315 assert(msg_type != -1);
316
317 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
318
319 /* Load the message header if present. If there's a texture offset, we need
320 * to set it up explicitly and load the offset bitfield. Otherwise, we can
321 * use an implied move from g0 to the first message register.
322 */
323 if (inst->header_present) {
324 if (brw->gen < 6 && !inst->texture_offset) {
325 /* Set up an implied move from g0 to the MRF. */
326 src = brw_vec8_grf(0, 0);
327 } else {
328 struct brw_reg header =
329 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
330
331 /* Explicitly set up the message header by copying g0 to the MRF. */
332 brw_push_insn_state(p);
333 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
334 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
335
336 brw_set_default_access_mode(p, BRW_ALIGN_1);
337
338 if (inst->texture_offset) {
339 /* Set the texel offset bits in DWord 2. */
340 brw_MOV(p, get_element_ud(header, 2),
341 brw_imm_ud(inst->texture_offset));
342 }
343
344 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
345 brw_pop_insn_state(p);
346 }
347 }
348
349 uint32_t return_format;
350
351 switch (dst.type) {
352 case BRW_REGISTER_TYPE_D:
353 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
354 break;
355 case BRW_REGISTER_TYPE_UD:
356 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
357 break;
358 default:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
360 break;
361 }
362
363 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
364 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
365 ? prog_data->base.binding_table.gather_texture_start
366 : prog_data->base.binding_table.texture_start;
367
368 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
369 uint32_t sampler = sampler_index.dw1.ud;
370
371 brw_SAMPLE(p,
372 dst,
373 inst->base_mrf,
374 src,
375 sampler + base_binding_table_index,
376 sampler % 16,
377 msg_type,
378 1, /* response length */
379 inst->mlen,
380 inst->header_present,
381 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
382 return_format);
383
384 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
385 } else {
386 /* Non-constant sampler index. */
387 /* Note: this clobbers `dst` as a temporary before emitting the send */
388
389 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
390 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
391
392 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
393
394 brw_push_insn_state(p);
395 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
396 brw_set_default_access_mode(p, BRW_ALIGN_1);
397
398 /* Some care required: `sampler` and `temp` may alias:
399 * addr = sampler & 0xff
400 * temp = (sampler << 8) & 0xf00
401 * addr = addr | temp
402 */
403 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
404 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
405 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
406 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
407 brw_OR(p, addr, addr, temp);
408
409 /* a0.0 |= <descriptor> */
410 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
411 brw_set_sampler_message(p, insn_or,
412 0 /* surface */,
413 0 /* sampler */,
414 msg_type,
415 1 /* rlen */,
416 inst->mlen /* mlen */,
417 inst->header_present /* header */,
418 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
419 return_format);
420 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
421 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
422 brw_set_src0(p, insn_or, addr);
423 brw_set_dest(p, insn_or, addr);
424
425
426 /* dst = send(offset, a0.0) */
427 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
428 brw_set_dest(p, insn_send, dst);
429 brw_set_src0(p, insn_send, src);
430 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
431
432 brw_pop_insn_state(p);
433
434 /* visitor knows more than we do about the surface limit required,
435 * so has already done marking.
436 */
437 }
438 }
439
440 void
441 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
442 {
443 brw_urb_WRITE(p,
444 brw_null_reg(), /* dest */
445 inst->base_mrf, /* starting mrf reg nr */
446 brw_vec8_grf(0, 0), /* src */
447 inst->urb_write_flags,
448 inst->mlen,
449 0, /* response len */
450 inst->offset, /* urb destination offset */
451 BRW_URB_SWIZZLE_INTERLEAVE);
452 }
453
454 void
455 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
456 {
457 struct brw_reg src = brw_message_reg(inst->base_mrf);
458 brw_urb_WRITE(p,
459 brw_null_reg(), /* dest */
460 inst->base_mrf, /* starting mrf reg nr */
461 src,
462 inst->urb_write_flags,
463 inst->mlen,
464 0, /* response len */
465 inst->offset, /* urb destination offset */
466 BRW_URB_SWIZZLE_INTERLEAVE);
467 }
468
469 void
470 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
471 {
472 struct brw_reg src = brw_message_reg(inst->base_mrf);
473
474 /* We pass the temporary passed in src0 as the writeback register */
475 brw_urb_WRITE(p,
476 inst->get_src(this->prog_data, 0), /* dest */
477 inst->base_mrf, /* starting mrf reg nr */
478 src,
479 BRW_URB_WRITE_ALLOCATE_COMPLETE,
480 inst->mlen,
481 1, /* response len */
482 inst->offset, /* urb destination offset */
483 BRW_URB_SWIZZLE_INTERLEAVE);
484
485 /* Now put allocated urb handle in dst.0 */
486 brw_push_insn_state(p);
487 brw_set_default_access_mode(p, BRW_ALIGN_1);
488 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
489 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
490 get_element_ud(inst->get_src(this->prog_data, 0), 0));
491 brw_set_default_access_mode(p, BRW_ALIGN_16);
492 brw_pop_insn_state(p);
493 }
494
495 void
496 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
497 {
498 struct brw_reg src = brw_message_reg(inst->base_mrf);
499 brw_urb_WRITE(p,
500 brw_null_reg(), /* dest */
501 inst->base_mrf, /* starting mrf reg nr */
502 src,
503 BRW_URB_WRITE_EOT | inst->urb_write_flags,
504 brw->gen >= 8 ? 2 : 1,/* message len */
505 0, /* response len */
506 0, /* urb destination offset */
507 BRW_URB_SWIZZLE_INTERLEAVE);
508 }
509
510 void
511 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
512 struct brw_reg src0,
513 struct brw_reg src1)
514 {
515 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
516 * Header: M0.3):
517 *
518 * Slot 0 Offset. This field, after adding to the Global Offset field
519 * in the message descriptor, specifies the offset (in 256-bit units)
520 * from the start of the URB entry, as referenced by URB Handle 0, at
521 * which the data will be accessed.
522 *
523 * Similar text describes DWORD M0.4, which is slot 1 offset.
524 *
525 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
526 * of the register for geometry shader invocations 0 and 1) by the
527 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
528 *
529 * We can do this with the following EU instruction:
530 *
531 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
532 */
533 brw_push_insn_state(p);
534 brw_set_default_access_mode(p, BRW_ALIGN_1);
535 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
536 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
537 src1);
538 brw_set_default_access_mode(p, BRW_ALIGN_16);
539 brw_pop_insn_state(p);
540 }
541
542 void
543 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
544 struct brw_reg src)
545 {
546 brw_push_insn_state(p);
547 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
548
549 if (brw->gen >= 8) {
550 /* Move the vertex count into the second MRF for the EOT write. */
551 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
552 src);
553 } else {
554 /* If we think of the src and dst registers as composed of 8 DWORDs each,
555 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
556 * them to WORDs, and then pack them into DWORD 2 of dst.
557 *
558 * It's easier to get the EU to do this if we think of the src and dst
559 * registers as composed of 16 WORDS each; then, we want to pick up the
560 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
561 * of dst.
562 *
563 * We can do that by the following EU instruction:
564 *
565 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
566 */
567 brw_set_default_access_mode(p, BRW_ALIGN_1);
568 brw_MOV(p,
569 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
570 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
571 brw_set_default_access_mode(p, BRW_ALIGN_16);
572 }
573 brw_pop_insn_state(p);
574 }
575
576 void
577 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
578 struct brw_reg dst,
579 struct brw_reg src0,
580 struct brw_reg src1)
581 {
582 int binding = inst->sol_binding;
583 bool final_write = inst->sol_final_write;
584
585 brw_push_insn_state(p);
586 /* Copy Vertex data into M0.x */
587 brw_MOV(p, stride(dst, 4, 4, 1),
588 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
589
590 /* Send SVB Write */
591 brw_svb_write(p,
592 final_write ? src1 : brw_null_reg(), /* dest == src1 */
593 1, /* msg_reg_nr */
594 dst, /* src0 == previous dst */
595 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
596 final_write); /* send_commit_msg */
597
598 /* Finally, wait for the write commit to occur so that we can proceed to
599 * other things safely.
600 *
601 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
602 *
603 * The write commit does not modify the destination register, but
604 * merely clears the dependency associated with the destination
605 * register. Thus, a simple “mov” instruction using the register as a
606 * source is sufficient to wait for the write commit to occur.
607 */
608 if (final_write) {
609 brw_MOV(p, src1, src1);
610 }
611 brw_pop_insn_state(p);
612 }
613
614 void
615 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
616 struct brw_reg dst,
617 struct brw_reg src)
618 {
619
620 int vertex = inst->sol_vertex;
621 brw_push_insn_state(p);
622 brw_set_default_access_mode(p, BRW_ALIGN_1);
623 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
624 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
625 brw_pop_insn_state(p);
626 }
627
628 void
629 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
630 {
631 brw_push_insn_state(p);
632 brw_set_default_access_mode(p, BRW_ALIGN_1);
633 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
634 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
635 brw_pop_insn_state(p);
636 }
637
638 void
639 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
640 {
641 /* We want to left shift just DWORD 4 (the x component belonging to the
642 * second geometry shader invocation) by 4 bits. So generate the
643 * instruction:
644 *
645 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
646 */
647 dst = suboffset(vec1(dst), 4);
648 brw_push_insn_state(p);
649 brw_set_default_access_mode(p, BRW_ALIGN_1);
650 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
651 brw_SHL(p, dst, dst, brw_imm_ud(4));
652 brw_pop_insn_state(p);
653 }
654
655 void
656 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
657 struct brw_reg src)
658 {
659 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
660 * Header: M0.5):
661 *
662 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
663 *
664 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
665 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
666 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
667 * channel enable to determine the final channel enable. For the
668 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
669 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
670 * in the writeback message. For the URB_WRITE_OWORD &
671 * URB_WRITE_HWORD messages, when final channel enable is 1 it
672 * indicates that Vertex 1 DATA [3] will be written to the surface.
673 *
674 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
675 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
676 *
677 * 14 Vertex 1 DATA [2] Channel Mask
678 * 13 Vertex 1 DATA [1] Channel Mask
679 * 12 Vertex 1 DATA [0] Channel Mask
680 * 11 Vertex 0 DATA [3] Channel Mask
681 * 10 Vertex 0 DATA [2] Channel Mask
682 * 9 Vertex 0 DATA [1] Channel Mask
683 * 8 Vertex 0 DATA [0] Channel Mask
684 *
685 * (This is from a section of the PRM that is agnostic to the particular
686 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
687 * geometry shader invocations 0 and 1, respectively). Since we have the
688 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
689 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
690 * DWORD 4, we just need to OR them together and store the result in bits
691 * 15:8 of DWORD 5.
692 *
693 * It's easier to get the EU to do this if we think of the src and dst
694 * registers as composed of 32 bytes each; then, we want to pick up the
695 * contents of bytes 0 and 16 from src, OR them together, and store them in
696 * byte 21.
697 *
698 * We can do that by the following EU instruction:
699 *
700 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
701 *
702 * Note: this relies on the source register having zeros in (a) bits 7:4 of
703 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
704 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
705 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
706 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
707 * contain valid channel mask values (which are in the range 0x0-0xf).
708 */
709 dst = retype(dst, BRW_REGISTER_TYPE_UB);
710 src = retype(src, BRW_REGISTER_TYPE_UB);
711 brw_push_insn_state(p);
712 brw_set_default_access_mode(p, BRW_ALIGN_1);
713 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
714 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
715 brw_pop_insn_state(p);
716 }
717
718 void
719 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
720 {
721 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
722 * and store into dst.0 & dst.4. So generate the instruction:
723 *
724 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
725 */
726 brw_push_insn_state(p);
727 brw_set_default_access_mode(p, BRW_ALIGN_1);
728 dst = retype(dst, BRW_REGISTER_TYPE_UD);
729 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
730 brw_SHR(p, dst, stride(r0, 1, 4, 0),
731 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
732 brw_pop_insn_state(p);
733 }
734
735 void
736 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
737 struct brw_reg dst,
738 struct brw_reg src0)
739 {
740 /* This opcode uses an implied MRF register for:
741 * - the header of the ff_sync message. And as such it is expected to be
742 * initialized to r0 before calling here.
743 * - the destination where we will write the allocated URB handle.
744 */
745 struct brw_reg header =
746 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
747
748 /* Overwrite dword 0 of the header (cleared for now since we are not doing
749 * transform feedback) and dword 1 (to hold the number of primitives
750 * written).
751 */
752 brw_push_insn_state(p);
753 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
754 brw_set_default_access_mode(p, BRW_ALIGN_1);
755 brw_MOV(p, get_element_ud(header, 0), brw_imm_ud(0));
756 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
757 brw_pop_insn_state(p);
758
759 /* Allocate URB handle in dst */
760 brw_ff_sync(p,
761 dst,
762 0,
763 header,
764 1, /* allocate */
765 1, /* response length */
766 0 /* eot */);
767
768 /* Now put allocated urb handle in header.0 */
769 brw_push_insn_state(p);
770 brw_set_default_access_mode(p, BRW_ALIGN_1);
771 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
772 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
773 brw_pop_insn_state(p);
774 }
775
776 void
777 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
778 {
779 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
780 struct brw_reg src = brw_vec8_grf(0, 0);
781 brw_push_insn_state(p);
782 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
783 brw_set_default_access_mode(p, BRW_ALIGN_1);
784 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
785 brw_pop_insn_state(p);
786 }
787
788 void
789 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
790 struct brw_reg index)
791 {
792 int second_vertex_offset;
793
794 if (brw->gen >= 6)
795 second_vertex_offset = 1;
796 else
797 second_vertex_offset = 16;
798
799 m1 = retype(m1, BRW_REGISTER_TYPE_D);
800
801 /* Set up M1 (message payload). Only the block offsets in M1.0 and
802 * M1.4 are used, and the rest are ignored.
803 */
804 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
805 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
806 struct brw_reg index_0 = suboffset(vec1(index), 0);
807 struct brw_reg index_4 = suboffset(vec1(index), 4);
808
809 brw_push_insn_state(p);
810 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
811 brw_set_default_access_mode(p, BRW_ALIGN_1);
812
813 brw_MOV(p, m1_0, index_0);
814
815 if (index.file == BRW_IMMEDIATE_VALUE) {
816 index_4.dw1.ud += second_vertex_offset;
817 brw_MOV(p, m1_4, index_4);
818 } else {
819 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
820 }
821
822 brw_pop_insn_state(p);
823 }
824
825 void
826 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
827 struct brw_reg dst)
828 {
829 brw_push_insn_state(p);
830 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
831 brw_set_default_access_mode(p, BRW_ALIGN_1);
832
833 struct brw_reg flags = brw_flag_reg(0, 0);
834 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
835 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
836
837 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
838 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
839 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
840
841 brw_pop_insn_state(p);
842 }
843
844 void
845 vec4_generator::generate_scratch_read(vec4_instruction *inst,
846 struct brw_reg dst,
847 struct brw_reg index)
848 {
849 struct brw_reg header = brw_vec8_grf(0, 0);
850
851 gen6_resolve_implied_move(p, &header, inst->base_mrf);
852
853 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
854 index);
855
856 uint32_t msg_type;
857
858 if (brw->gen >= 6)
859 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
860 else if (brw->gen == 5 || brw->is_g4x)
861 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
862 else
863 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
864
865 /* Each of the 8 channel enables is considered for whether each
866 * dword is written.
867 */
868 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
869 brw_set_dest(p, send, dst);
870 brw_set_src0(p, send, header);
871 if (brw->gen < 6)
872 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
873 brw_set_dp_read_message(p, send,
874 255, /* binding table index: stateless access */
875 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
876 msg_type,
877 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
878 2, /* mlen */
879 true, /* header_present */
880 1 /* rlen */);
881 }
882
883 void
884 vec4_generator::generate_scratch_write(vec4_instruction *inst,
885 struct brw_reg dst,
886 struct brw_reg src,
887 struct brw_reg index)
888 {
889 struct brw_reg header = brw_vec8_grf(0, 0);
890 bool write_commit;
891
892 /* If the instruction is predicated, we'll predicate the send, not
893 * the header setup.
894 */
895 brw_set_default_predicate_control(p, false);
896
897 gen6_resolve_implied_move(p, &header, inst->base_mrf);
898
899 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
900 index);
901
902 brw_MOV(p,
903 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
904 retype(src, BRW_REGISTER_TYPE_D));
905
906 uint32_t msg_type;
907
908 if (brw->gen >= 7)
909 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
910 else if (brw->gen == 6)
911 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
912 else
913 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
914
915 brw_set_default_predicate_control(p, inst->predicate);
916
917 /* Pre-gen6, we have to specify write commits to ensure ordering
918 * between reads and writes within a thread. Afterwards, that's
919 * guaranteed and write commits only matter for inter-thread
920 * synchronization.
921 */
922 if (brw->gen >= 6) {
923 write_commit = false;
924 } else {
925 /* The visitor set up our destination register to be g0. This
926 * means that when the next read comes along, we will end up
927 * reading from g0 and causing a block on the write commit. For
928 * write-after-read, we are relying on the value of the previous
929 * read being used (and thus blocking on completion) before our
930 * write is executed. This means we have to be careful in
931 * instruction scheduling to not violate this assumption.
932 */
933 write_commit = true;
934 }
935
936 /* Each of the 8 channel enables is considered for whether each
937 * dword is written.
938 */
939 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
940 brw_set_dest(p, send, dst);
941 brw_set_src0(p, send, header);
942 if (brw->gen < 6)
943 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
944 brw_set_dp_write_message(p, send,
945 255, /* binding table index: stateless access */
946 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
947 msg_type,
948 3, /* mlen */
949 true, /* header present */
950 false, /* not a render target write */
951 write_commit, /* rlen */
952 false, /* eot */
953 write_commit);
954 }
955
956 void
957 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
958 struct brw_reg dst,
959 struct brw_reg index,
960 struct brw_reg offset)
961 {
962 assert(index.file == BRW_IMMEDIATE_VALUE &&
963 index.type == BRW_REGISTER_TYPE_UD);
964 uint32_t surf_index = index.dw1.ud;
965
966 struct brw_reg header = brw_vec8_grf(0, 0);
967
968 gen6_resolve_implied_move(p, &header, inst->base_mrf);
969
970 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
971 offset);
972
973 uint32_t msg_type;
974
975 if (brw->gen >= 6)
976 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
977 else if (brw->gen == 5 || brw->is_g4x)
978 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
979 else
980 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
981
982 /* Each of the 8 channel enables is considered for whether each
983 * dword is written.
984 */
985 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
986 brw_set_dest(p, send, dst);
987 brw_set_src0(p, send, header);
988 if (brw->gen < 6)
989 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
990 brw_set_dp_read_message(p, send,
991 surf_index,
992 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
993 msg_type,
994 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
995 2, /* mlen */
996 true, /* header_present */
997 1 /* rlen */);
998
999 brw_mark_surface_used(&prog_data->base, surf_index);
1000 }
1001
1002 void
1003 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1004 struct brw_reg dst,
1005 struct brw_reg surf_index,
1006 struct brw_reg offset)
1007 {
1008 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1009
1010 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1011
1012 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1013 brw_set_dest(p, insn, dst);
1014 brw_set_src0(p, insn, offset);
1015 brw_set_sampler_message(p, insn,
1016 surf_index.dw1.ud,
1017 0, /* LD message ignores sampler unit */
1018 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1019 1, /* rlen */
1020 1, /* mlen */
1021 false, /* no header */
1022 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1023 0);
1024
1025 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1026
1027 } else {
1028
1029 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1030
1031 brw_push_insn_state(p);
1032 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1033 brw_set_default_access_mode(p, BRW_ALIGN_1);
1034
1035 /* a0.0 = surf_index & 0xff */
1036 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1037 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1038 brw_set_dest(p, insn_and, addr);
1039 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1040 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1041
1042
1043 /* a0.0 |= <descriptor> */
1044 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1045 brw_set_sampler_message(p, insn_or,
1046 0 /* surface */,
1047 0 /* sampler */,
1048 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1049 1 /* rlen */,
1050 1 /* mlen */,
1051 false /* header */,
1052 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1053 0);
1054 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1055 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1056 brw_set_src0(p, insn_or, addr);
1057 brw_set_dest(p, insn_or, addr);
1058
1059
1060 /* dst = send(offset, a0.0) */
1061 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1062 brw_set_dest(p, insn_send, dst);
1063 brw_set_src0(p, insn_send, offset);
1064 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1065
1066 brw_pop_insn_state(p);
1067
1068 /* visitor knows more than we do about the surface limit required,
1069 * so has already done marking.
1070 */
1071 }
1072 }
1073
1074 void
1075 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1076 struct brw_reg dst,
1077 struct brw_reg atomic_op,
1078 struct brw_reg surf_index)
1079 {
1080 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1081 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1082 surf_index.file == BRW_IMMEDIATE_VALUE &&
1083 surf_index.type == BRW_REGISTER_TYPE_UD);
1084
1085 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1086 atomic_op.dw1.ud, surf_index.dw1.ud,
1087 inst->mlen, 1);
1088
1089 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1090 }
1091
1092 void
1093 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1094 struct brw_reg dst,
1095 struct brw_reg surf_index)
1096 {
1097 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1098 surf_index.type == BRW_REGISTER_TYPE_UD);
1099
1100 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1101 surf_index.dw1.ud,
1102 inst->mlen, 1);
1103
1104 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1105 }
1106
1107 void
1108 vec4_generator::generate_code(const cfg_t *cfg)
1109 {
1110 struct annotation_info annotation;
1111 memset(&annotation, 0, sizeof(annotation));
1112 int loop_count = 0;
1113
1114 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1115 struct brw_reg src[3], dst;
1116
1117 if (unlikely(debug_flag))
1118 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1119
1120 for (unsigned int i = 0; i < 3; i++) {
1121 src[i] = inst->get_src(this->prog_data, i);
1122 }
1123 dst = inst->get_dst();
1124
1125 brw_set_default_predicate_control(p, inst->predicate);
1126 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1127 brw_set_default_saturate(p, inst->saturate);
1128 brw_set_default_mask_control(p, inst->force_writemask_all);
1129 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1130
1131 unsigned pre_emit_nr_insn = p->nr_insn;
1132
1133 if (dst.width == BRW_WIDTH_4) {
1134 /* This happens in attribute fixups for "dual instanced" geometry
1135 * shaders, since they use attributes that are vec4's. Since the exec
1136 * width is only 4, it's essential that the caller set
1137 * force_writemask_all in order to make sure the instruction is executed
1138 * regardless of which channels are enabled.
1139 */
1140 assert(inst->force_writemask_all);
1141
1142 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1143 * the following register region restrictions (from Graphics BSpec:
1144 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1145 * > Register Region Restrictions)
1146 *
1147 * 1. ExecSize must be greater than or equal to Width.
1148 *
1149 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1150 * to Width * HorzStride."
1151 */
1152 for (int i = 0; i < 3; i++) {
1153 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1154 src[i] = stride(src[i], 4, 4, 1);
1155 }
1156 }
1157
1158 switch (inst->opcode) {
1159 case BRW_OPCODE_MOV:
1160 brw_MOV(p, dst, src[0]);
1161 break;
1162 case BRW_OPCODE_ADD:
1163 brw_ADD(p, dst, src[0], src[1]);
1164 break;
1165 case BRW_OPCODE_MUL:
1166 brw_MUL(p, dst, src[0], src[1]);
1167 break;
1168 case BRW_OPCODE_MACH:
1169 brw_MACH(p, dst, src[0], src[1]);
1170 break;
1171
1172 case BRW_OPCODE_MAD:
1173 assert(brw->gen >= 6);
1174 brw_MAD(p, dst, src[0], src[1], src[2]);
1175 break;
1176
1177 case BRW_OPCODE_FRC:
1178 brw_FRC(p, dst, src[0]);
1179 break;
1180 case BRW_OPCODE_RNDD:
1181 brw_RNDD(p, dst, src[0]);
1182 break;
1183 case BRW_OPCODE_RNDE:
1184 brw_RNDE(p, dst, src[0]);
1185 break;
1186 case BRW_OPCODE_RNDZ:
1187 brw_RNDZ(p, dst, src[0]);
1188 break;
1189
1190 case BRW_OPCODE_AND:
1191 brw_AND(p, dst, src[0], src[1]);
1192 break;
1193 case BRW_OPCODE_OR:
1194 brw_OR(p, dst, src[0], src[1]);
1195 break;
1196 case BRW_OPCODE_XOR:
1197 brw_XOR(p, dst, src[0], src[1]);
1198 break;
1199 case BRW_OPCODE_NOT:
1200 brw_NOT(p, dst, src[0]);
1201 break;
1202 case BRW_OPCODE_ASR:
1203 brw_ASR(p, dst, src[0], src[1]);
1204 break;
1205 case BRW_OPCODE_SHR:
1206 brw_SHR(p, dst, src[0], src[1]);
1207 break;
1208 case BRW_OPCODE_SHL:
1209 brw_SHL(p, dst, src[0], src[1]);
1210 break;
1211
1212 case BRW_OPCODE_CMP:
1213 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1214 break;
1215 case BRW_OPCODE_SEL:
1216 brw_SEL(p, dst, src[0], src[1]);
1217 break;
1218
1219 case BRW_OPCODE_DPH:
1220 brw_DPH(p, dst, src[0], src[1]);
1221 break;
1222
1223 case BRW_OPCODE_DP4:
1224 brw_DP4(p, dst, src[0], src[1]);
1225 break;
1226
1227 case BRW_OPCODE_DP3:
1228 brw_DP3(p, dst, src[0], src[1]);
1229 break;
1230
1231 case BRW_OPCODE_DP2:
1232 brw_DP2(p, dst, src[0], src[1]);
1233 break;
1234
1235 case BRW_OPCODE_F32TO16:
1236 assert(brw->gen >= 7);
1237 brw_F32TO16(p, dst, src[0]);
1238 break;
1239
1240 case BRW_OPCODE_F16TO32:
1241 assert(brw->gen >= 7);
1242 brw_F16TO32(p, dst, src[0]);
1243 break;
1244
1245 case BRW_OPCODE_LRP:
1246 assert(brw->gen >= 6);
1247 brw_LRP(p, dst, src[0], src[1], src[2]);
1248 break;
1249
1250 case BRW_OPCODE_BFREV:
1251 assert(brw->gen >= 7);
1252 /* BFREV only supports UD type for src and dst. */
1253 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1254 retype(src[0], BRW_REGISTER_TYPE_UD));
1255 break;
1256 case BRW_OPCODE_FBH:
1257 assert(brw->gen >= 7);
1258 /* FBH only supports UD type for dst. */
1259 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1260 break;
1261 case BRW_OPCODE_FBL:
1262 assert(brw->gen >= 7);
1263 /* FBL only supports UD type for dst. */
1264 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1265 break;
1266 case BRW_OPCODE_CBIT:
1267 assert(brw->gen >= 7);
1268 /* CBIT only supports UD type for dst. */
1269 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1270 break;
1271 case BRW_OPCODE_ADDC:
1272 assert(brw->gen >= 7);
1273 brw_ADDC(p, dst, src[0], src[1]);
1274 break;
1275 case BRW_OPCODE_SUBB:
1276 assert(brw->gen >= 7);
1277 brw_SUBB(p, dst, src[0], src[1]);
1278 break;
1279 case BRW_OPCODE_MAC:
1280 brw_MAC(p, dst, src[0], src[1]);
1281 break;
1282
1283 case BRW_OPCODE_BFE:
1284 assert(brw->gen >= 7);
1285 brw_BFE(p, dst, src[0], src[1], src[2]);
1286 break;
1287
1288 case BRW_OPCODE_BFI1:
1289 assert(brw->gen >= 7);
1290 brw_BFI1(p, dst, src[0], src[1]);
1291 break;
1292 case BRW_OPCODE_BFI2:
1293 assert(brw->gen >= 7);
1294 brw_BFI2(p, dst, src[0], src[1], src[2]);
1295 break;
1296
1297 case BRW_OPCODE_IF:
1298 if (inst->src[0].file != BAD_FILE) {
1299 /* The instruction has an embedded compare (only allowed on gen6) */
1300 assert(brw->gen == 6);
1301 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1302 } else {
1303 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1304 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1305 }
1306 break;
1307
1308 case BRW_OPCODE_ELSE:
1309 brw_ELSE(p);
1310 break;
1311 case BRW_OPCODE_ENDIF:
1312 brw_ENDIF(p);
1313 break;
1314
1315 case BRW_OPCODE_DO:
1316 brw_DO(p, BRW_EXECUTE_8);
1317 break;
1318
1319 case BRW_OPCODE_BREAK:
1320 brw_BREAK(p);
1321 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1322 break;
1323 case BRW_OPCODE_CONTINUE:
1324 brw_CONT(p);
1325 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1326 break;
1327
1328 case BRW_OPCODE_WHILE:
1329 brw_WHILE(p);
1330 loop_count++;
1331 break;
1332
1333 case SHADER_OPCODE_RCP:
1334 case SHADER_OPCODE_RSQ:
1335 case SHADER_OPCODE_SQRT:
1336 case SHADER_OPCODE_EXP2:
1337 case SHADER_OPCODE_LOG2:
1338 case SHADER_OPCODE_SIN:
1339 case SHADER_OPCODE_COS:
1340 if (brw->gen >= 7) {
1341 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1342 brw_null_reg());
1343 } else if (brw->gen == 6) {
1344 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1345 } else {
1346 generate_math1_gen4(inst, dst, src[0]);
1347 }
1348 break;
1349
1350 case SHADER_OPCODE_POW:
1351 case SHADER_OPCODE_INT_QUOTIENT:
1352 case SHADER_OPCODE_INT_REMAINDER:
1353 if (brw->gen >= 7) {
1354 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1355 } else if (brw->gen == 6) {
1356 generate_math_gen6(inst, dst, src[0], src[1]);
1357 } else {
1358 generate_math2_gen4(inst, dst, src[0], src[1]);
1359 }
1360 break;
1361
1362 case SHADER_OPCODE_TEX:
1363 case SHADER_OPCODE_TXD:
1364 case SHADER_OPCODE_TXF:
1365 case SHADER_OPCODE_TXF_CMS:
1366 case SHADER_OPCODE_TXF_MCS:
1367 case SHADER_OPCODE_TXL:
1368 case SHADER_OPCODE_TXS:
1369 case SHADER_OPCODE_TG4:
1370 case SHADER_OPCODE_TG4_OFFSET:
1371 generate_tex(inst, dst, src[0], src[1]);
1372 break;
1373
1374 case VS_OPCODE_URB_WRITE:
1375 generate_vs_urb_write(inst);
1376 break;
1377
1378 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1379 generate_scratch_read(inst, dst, src[0]);
1380 break;
1381
1382 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1383 generate_scratch_write(inst, dst, src[0], src[1]);
1384 break;
1385
1386 case VS_OPCODE_PULL_CONSTANT_LOAD:
1387 generate_pull_constant_load(inst, dst, src[0], src[1]);
1388 break;
1389
1390 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1391 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1392 break;
1393
1394 case GS_OPCODE_URB_WRITE:
1395 generate_gs_urb_write(inst);
1396 break;
1397
1398 case GS_OPCODE_URB_WRITE_ALLOCATE:
1399 generate_gs_urb_write_allocate(inst);
1400 break;
1401
1402 case GS_OPCODE_SVB_WRITE:
1403 generate_gs_svb_write(inst, dst, src[0], src[1]);
1404 break;
1405
1406 case GS_OPCODE_SVB_SET_DST_INDEX:
1407 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1408 break;
1409
1410 case GS_OPCODE_THREAD_END:
1411 generate_gs_thread_end(inst);
1412 break;
1413
1414 case GS_OPCODE_SET_WRITE_OFFSET:
1415 generate_gs_set_write_offset(dst, src[0], src[1]);
1416 break;
1417
1418 case GS_OPCODE_SET_VERTEX_COUNT:
1419 generate_gs_set_vertex_count(dst, src[0]);
1420 break;
1421
1422 case GS_OPCODE_FF_SYNC:
1423 generate_gs_ff_sync(inst, dst, src[0]);
1424 break;
1425
1426 case GS_OPCODE_SET_PRIMITIVE_ID:
1427 generate_gs_set_primitive_id(dst);
1428 break;
1429
1430 case GS_OPCODE_SET_DWORD_2:
1431 generate_gs_set_dword_2(dst, src[0]);
1432 break;
1433
1434 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1435 generate_gs_prepare_channel_masks(dst);
1436 break;
1437
1438 case GS_OPCODE_SET_CHANNEL_MASKS:
1439 generate_gs_set_channel_masks(dst, src[0]);
1440 break;
1441
1442 case GS_OPCODE_GET_INSTANCE_ID:
1443 generate_gs_get_instance_id(dst);
1444 break;
1445
1446 case SHADER_OPCODE_SHADER_TIME_ADD:
1447 brw_shader_time_add(p, src[0],
1448 prog_data->base.binding_table.shader_time_start);
1449 brw_mark_surface_used(&prog_data->base,
1450 prog_data->base.binding_table.shader_time_start);
1451 break;
1452
1453 case SHADER_OPCODE_UNTYPED_ATOMIC:
1454 generate_untyped_atomic(inst, dst, src[0], src[1]);
1455 break;
1456
1457 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1458 generate_untyped_surface_read(inst, dst, src[0]);
1459 break;
1460
1461 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1462 generate_unpack_flags(inst, dst);
1463 break;
1464
1465 default:
1466 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1467 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1468 opcode_descs[inst->opcode].name);
1469 } else {
1470 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1471 }
1472 abort();
1473 }
1474
1475 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1476 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1477 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1478 "emitting more than 1 instruction");
1479
1480 brw_inst *last = &p->store[pre_emit_nr_insn];
1481
1482 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1483 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1484 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1485 }
1486 }
1487
1488 brw_set_uip_jip(p);
1489 annotation_finalize(&annotation, p->next_insn_offset);
1490
1491 int before_size = p->next_insn_offset;
1492 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1493 int after_size = p->next_insn_offset;
1494
1495 if (unlikely(debug_flag)) {
1496 if (shader_prog) {
1497 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1498 shader_prog->Label ? shader_prog->Label : "unnamed",
1499 shader_prog->Name);
1500 } else {
1501 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1502 }
1503 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1504 " bytes (%.0f%%)\n",
1505 before_size / 16, loop_count, before_size, after_size,
1506 100.0f * (before_size - after_size) / before_size);
1507
1508 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1509 ralloc_free(annotation.ann);
1510 }
1511 }
1512
1513 const unsigned *
1514 vec4_generator::generate_assembly(const cfg_t *cfg,
1515 unsigned *assembly_size)
1516 {
1517 brw_set_default_access_mode(p, BRW_ALIGN_16);
1518 generate_code(cfg);
1519
1520 return brw_get_program(p, assembly_size);
1521 }
1522
1523 } /* namespace brw */