1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 brw_reg
= dst
.fixed_hw_reg
;
57 brw_reg
= brw_null_reg();
61 assert(!"not reached");
62 brw_reg
= brw_null_reg();
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 assert(!"not reached");
97 brw_reg
= brw_null_reg();
103 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
104 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
105 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
107 brw_reg
= retype(brw_reg
, src
[i
].type
);
108 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
110 brw_reg
= brw_abs(brw_reg
);
112 brw_reg
= negate(brw_reg
);
114 /* This should have been moved to pull constants. */
115 assert(!src
[i
].reladdr
);
119 brw_reg
= src
[i
].fixed_hw_reg
;
123 /* Probably unused. */
124 brw_reg
= brw_null_reg();
128 assert(!"not reached");
129 brw_reg
= brw_null_reg();
136 vec4_generator::vec4_generator(struct brw_context
*brw
,
137 struct gl_shader_program
*shader_prog
,
138 struct gl_program
*prog
,
139 struct brw_vec4_prog_data
*prog_data
,
142 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
143 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
145 shader
= shader_prog
? shader_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
] : NULL
;
147 p
= rzalloc(mem_ctx
, struct brw_compile
);
148 brw_init_compile(brw
, p
, mem_ctx
);
151 vec4_generator::~vec4_generator()
156 vec4_generator::mark_surface_used(unsigned surf_index
)
158 assert(surf_index
< BRW_MAX_SURFACES
);
160 prog_data
->base
.binding_table
.size_bytes
=
161 MAX2(prog_data
->base
.binding_table
.size_bytes
, (surf_index
+ 1) * 4);
165 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
171 brw_math_function(inst
->opcode
),
174 BRW_MATH_DATA_VECTOR
,
175 BRW_MATH_PRECISION_FULL
);
179 check_gen6_math_src_arg(struct brw_reg src
)
181 /* Source swizzles are ignored. */
184 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
188 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
192 /* Can't do writemask because math can't be align16. */
193 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
194 check_gen6_math_src_arg(src
);
196 brw_set_access_mode(p
, BRW_ALIGN_1
);
199 brw_math_function(inst
->opcode
),
202 BRW_MATH_DATA_SCALAR
,
203 BRW_MATH_PRECISION_FULL
);
204 brw_set_access_mode(p
, BRW_ALIGN_16
);
208 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
215 brw_math_function(inst
->opcode
),
220 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
225 /* Can't do writemask because math can't be align16. */
226 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0
);
229 check_gen6_math_src_arg(src1
);
231 brw_set_access_mode(p
, BRW_ALIGN_1
);
234 brw_math_function(inst
->opcode
),
236 brw_set_access_mode(p
, BRW_ALIGN_16
);
240 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
248 * "Operand0[7]. For the INT DIV functions, this operand is the
251 * "Operand1[7]. For the INT DIV functions, this operand is the
254 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
255 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
256 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
258 brw_push_insn_state(p
);
259 brw_set_saturate(p
, false);
260 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
262 brw_pop_insn_state(p
);
266 brw_math_function(inst
->opcode
),
269 BRW_MATH_DATA_VECTOR
,
270 BRW_MATH_PRECISION_FULL
);
274 vec4_generator::generate_tex(vec4_instruction
*inst
,
281 switch (inst
->opcode
) {
282 case SHADER_OPCODE_TEX
:
283 case SHADER_OPCODE_TXL
:
284 if (inst
->shadow_compare
) {
285 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
287 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
290 case SHADER_OPCODE_TXD
:
291 if (inst
->shadow_compare
) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw
->is_haswell
);
294 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
296 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
299 case SHADER_OPCODE_TXF
:
300 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
302 case SHADER_OPCODE_TXF_MS
:
304 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
306 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
308 case SHADER_OPCODE_TXS
:
309 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
311 case SHADER_OPCODE_TG4
:
312 if (inst
->shadow_compare
) {
313 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
315 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
318 case SHADER_OPCODE_TG4_OFFSET
:
319 if (inst
->shadow_compare
) {
320 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
322 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
326 assert(!"should not get here: invalid VS texture opcode");
330 switch (inst
->opcode
) {
331 case SHADER_OPCODE_TEX
:
332 case SHADER_OPCODE_TXL
:
333 if (inst
->shadow_compare
) {
334 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
335 assert(inst
->mlen
== 3);
337 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
338 assert(inst
->mlen
== 2);
341 case SHADER_OPCODE_TXD
:
342 /* There is no sample_d_c message; comparisons are done manually. */
343 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
344 assert(inst
->mlen
== 4);
346 case SHADER_OPCODE_TXF
:
347 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
348 assert(inst
->mlen
== 2);
350 case SHADER_OPCODE_TXS
:
351 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
352 assert(inst
->mlen
== 2);
355 assert(!"should not get here: invalid VS texture opcode");
360 assert(msg_type
!= -1);
362 /* Load the message header if present. If there's a texture offset, we need
363 * to set it up explicitly and load the offset bitfield. Otherwise, we can
364 * use an implied move from g0 to the first message register.
366 if (inst
->texture_offset
) {
367 /* Explicitly set up the message header by copying g0 to the MRF. */
368 brw_push_insn_state(p
);
369 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
370 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
371 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
373 /* Then set the offset bits in DWord 2. */
374 brw_set_access_mode(p
, BRW_ALIGN_1
);
376 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
377 BRW_REGISTER_TYPE_UD
),
378 brw_imm_ud(inst
->texture_offset
));
379 brw_pop_insn_state(p
);
380 } else if (inst
->header_present
) {
381 /* Set up an implied move from g0 to the MRF. */
382 src
= brw_vec8_grf(0, 0);
385 uint32_t return_format
;
388 case BRW_REGISTER_TYPE_D
:
389 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
391 case BRW_REGISTER_TYPE_UD
:
392 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
395 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
399 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
400 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
401 ? prog_data
->base
.binding_table
.gather_texture_start
402 : prog_data
->base
.binding_table
.texture_start
) + inst
->sampler
;
411 1, /* response length */
413 inst
->header_present
,
414 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
417 mark_surface_used(surface_index
);
421 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
424 brw_null_reg(), /* dest */
425 inst
->base_mrf
, /* starting mrf reg nr */
426 brw_vec8_grf(0, 0), /* src */
427 inst
->urb_write_flags
,
429 0, /* response len */
430 inst
->offset
, /* urb destination offset */
431 BRW_URB_SWIZZLE_INTERLEAVE
);
435 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
437 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
439 brw_null_reg(), /* dest */
440 inst
->base_mrf
, /* starting mrf reg nr */
442 inst
->urb_write_flags
,
444 0, /* response len */
445 inst
->offset
, /* urb destination offset */
446 BRW_URB_SWIZZLE_INTERLEAVE
);
450 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
452 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
454 brw_null_reg(), /* dest */
455 inst
->base_mrf
, /* starting mrf reg nr */
459 0, /* response len */
460 0, /* urb destination offset */
461 BRW_URB_SWIZZLE_INTERLEAVE
);
465 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
469 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
472 * Slot 0 Offset. This field, after adding to the Global Offset field
473 * in the message descriptor, specifies the offset (in 256-bit units)
474 * from the start of the URB entry, as referenced by URB Handle 0, at
475 * which the data will be accessed.
477 * Similar text describes DWORD M0.4, which is slot 1 offset.
479 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
480 * of the register for geometry shader invocations 0 and 1) by the
481 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
483 * We can do this with the following EU instruction:
485 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
487 brw_push_insn_state(p
);
488 brw_set_access_mode(p
, BRW_ALIGN_1
);
489 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
490 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
492 brw_set_access_mode(p
, BRW_ALIGN_16
);
493 brw_pop_insn_state(p
);
497 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
500 brw_push_insn_state(p
);
501 brw_set_access_mode(p
, BRW_ALIGN_1
);
502 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
504 /* If we think of the src and dst registers as composed of 8 DWORDs each,
505 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
506 * them to WORDs, and then pack them into DWORD 2 of dst.
508 * It's easier to get the EU to do this if we think of the src and dst
509 * registers as composed of 16 WORDS each; then, we want to pick up the
510 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
513 * We can do that by the following EU instruction:
515 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
517 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
518 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
519 brw_set_access_mode(p
, BRW_ALIGN_16
);
520 brw_pop_insn_state(p
);
524 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
527 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
529 brw_push_insn_state(p
);
530 brw_set_access_mode(p
, BRW_ALIGN_1
);
531 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
532 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
533 brw_set_access_mode(p
, BRW_ALIGN_16
);
534 brw_pop_insn_state(p
);
538 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
540 /* We want to left shift just DWORD 4 (the x component belonging to the
541 * second geometry shader invocation) by 4 bits. So generate the
544 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
546 dst
= suboffset(vec1(dst
), 4);
547 brw_push_insn_state(p
);
548 brw_set_access_mode(p
, BRW_ALIGN_1
);
549 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
550 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
551 brw_pop_insn_state(p
);
555 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
558 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
561 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
563 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
564 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
565 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
566 * channel enable to determine the final channel enable. For the
567 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
568 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
569 * in the writeback message. For the URB_WRITE_OWORD &
570 * URB_WRITE_HWORD messages, when final channel enable is 1 it
571 * indicates that Vertex 1 DATA [3] will be written to the surface.
573 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
574 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
576 * 14 Vertex 1 DATA [2] Channel Mask
577 * 13 Vertex 1 DATA [1] Channel Mask
578 * 12 Vertex 1 DATA [0] Channel Mask
579 * 11 Vertex 0 DATA [3] Channel Mask
580 * 10 Vertex 0 DATA [2] Channel Mask
581 * 9 Vertex 0 DATA [1] Channel Mask
582 * 8 Vertex 0 DATA [0] Channel Mask
584 * (This is from a section of the PRM that is agnostic to the particular
585 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
586 * geometry shader invocations 0 and 1, respectively). Since we have the
587 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
588 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
589 * DWORD 4, we just need to OR them together and store the result in bits
592 * It's easier to get the EU to do this if we think of the src and dst
593 * registers as composed of 32 bytes each; then, we want to pick up the
594 * contents of bytes 0 and 16 from src, OR them together, and store them in
597 * We can do that by the following EU instruction:
599 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
601 * Note: this relies on the source register having zeros in (a) bits 7:4 of
602 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
603 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
604 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
605 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
606 * contain valid channel mask values (which are in the range 0x0-0xf).
608 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
609 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
610 brw_push_insn_state(p
);
611 brw_set_access_mode(p
, BRW_ALIGN_1
);
612 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
613 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
614 brw_pop_insn_state(p
);
618 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
619 struct brw_reg index
)
621 int second_vertex_offset
;
624 second_vertex_offset
= 1;
626 second_vertex_offset
= 16;
628 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
630 /* Set up M1 (message payload). Only the block offsets in M1.0 and
631 * M1.4 are used, and the rest are ignored.
633 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
634 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
635 struct brw_reg index_0
= suboffset(vec1(index
), 0);
636 struct brw_reg index_4
= suboffset(vec1(index
), 4);
638 brw_push_insn_state(p
);
639 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
640 brw_set_access_mode(p
, BRW_ALIGN_1
);
642 brw_MOV(p
, m1_0
, index_0
);
644 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
645 index_4
.dw1
.ud
+= second_vertex_offset
;
646 brw_MOV(p
, m1_4
, index_4
);
648 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
651 brw_pop_insn_state(p
);
655 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
658 brw_push_insn_state(p
);
659 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
660 brw_set_access_mode(p
, BRW_ALIGN_1
);
662 struct brw_reg flags
= brw_flag_reg(0, 0);
663 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
664 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
666 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
667 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
668 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
670 brw_pop_insn_state(p
);
674 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
676 struct brw_reg index
)
678 struct brw_reg header
= brw_vec8_grf(0, 0);
680 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
682 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
688 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
689 else if (brw
->gen
== 5 || brw
->is_g4x
)
690 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
692 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
694 /* Each of the 8 channel enables is considered for whether each
697 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
698 brw_set_dest(p
, send
, dst
);
699 brw_set_src0(p
, send
, header
);
701 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
702 brw_set_dp_read_message(p
, send
,
703 255, /* binding table index: stateless access */
704 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
706 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
708 true, /* header_present */
713 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
716 struct brw_reg index
)
718 struct brw_reg header
= brw_vec8_grf(0, 0);
721 /* If the instruction is predicated, we'll predicate the send, not
724 brw_set_predicate_control(p
, false);
726 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
728 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
732 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
733 retype(src
, BRW_REGISTER_TYPE_D
));
738 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
739 else if (brw
->gen
== 6)
740 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
742 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
744 brw_set_predicate_control(p
, inst
->predicate
);
746 /* Pre-gen6, we have to specify write commits to ensure ordering
747 * between reads and writes within a thread. Afterwards, that's
748 * guaranteed and write commits only matter for inter-thread
752 write_commit
= false;
754 /* The visitor set up our destination register to be g0. This
755 * means that when the next read comes along, we will end up
756 * reading from g0 and causing a block on the write commit. For
757 * write-after-read, we are relying on the value of the previous
758 * read being used (and thus blocking on completion) before our
759 * write is executed. This means we have to be careful in
760 * instruction scheduling to not violate this assumption.
765 /* Each of the 8 channel enables is considered for whether each
768 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
769 brw_set_dest(p
, send
, dst
);
770 brw_set_src0(p
, send
, header
);
772 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
773 brw_set_dp_write_message(p
, send
,
774 255, /* binding table index: stateless access */
775 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
778 true, /* header present */
779 false, /* not a render target write */
780 write_commit
, /* rlen */
786 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
788 struct brw_reg index
,
789 struct brw_reg offset
)
791 assert(brw
->gen
<= 7);
792 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
793 index
.type
== BRW_REGISTER_TYPE_UD
);
794 uint32_t surf_index
= index
.dw1
.ud
;
796 struct brw_reg header
= brw_vec8_grf(0, 0);
798 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
800 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
806 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
807 else if (brw
->gen
== 5 || brw
->is_g4x
)
808 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
810 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
812 /* Each of the 8 channel enables is considered for whether each
815 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
816 brw_set_dest(p
, send
, dst
);
817 brw_set_src0(p
, send
, header
);
819 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
820 brw_set_dp_read_message(p
, send
,
822 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
824 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
826 true, /* header_present */
829 mark_surface_used(surf_index
);
833 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
835 struct brw_reg surf_index
,
836 struct brw_reg offset
)
838 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
839 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
841 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
842 brw_set_dest(p
, insn
, dst
);
843 brw_set_src0(p
, insn
, offset
);
844 brw_set_sampler_message(p
, insn
,
846 0, /* LD message ignores sampler unit */
847 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
850 false, /* no header */
851 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
854 mark_surface_used(surf_index
.dw1
.ud
);
858 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
860 struct brw_reg atomic_op
,
861 struct brw_reg surf_index
)
863 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
864 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
865 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
866 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
868 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
869 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
872 mark_surface_used(surf_index
.dw1
.ud
);
876 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
878 struct brw_reg surf_index
)
880 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
881 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
883 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
887 mark_surface_used(surf_index
.dw1
.ud
);
891 * Generate assembly for a Vec4 IR instruction.
893 * \param instruction The Vec4 IR instruction to generate code for.
894 * \param dst The destination register.
895 * \param src An array of up to three source registers.
898 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
902 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
904 if (dst
.width
== BRW_WIDTH_4
) {
905 /* This happens in attribute fixups for "dual instanced" geometry
906 * shaders, since they use attributes that are vec4's. Since the exec
907 * width is only 4, it's essential that the caller set
908 * force_writemask_all in order to make sure the instruction is executed
909 * regardless of which channels are enabled.
911 assert(inst
->force_writemask_all
);
913 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
914 * the following register region restrictions (from Graphics BSpec:
915 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
916 * > Register Region Restrictions)
918 * 1. ExecSize must be greater than or equal to Width.
920 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
921 * to Width * HorzStride."
923 for (int i
= 0; i
< 3; i
++) {
924 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
925 src
[i
] = stride(src
[i
], 4, 4, 1);
929 switch (inst
->opcode
) {
931 brw_MOV(p
, dst
, src
[0]);
934 brw_ADD(p
, dst
, src
[0], src
[1]);
937 brw_MUL(p
, dst
, src
[0], src
[1]);
939 case BRW_OPCODE_MACH
:
940 brw_set_acc_write_control(p
, 1);
941 brw_MACH(p
, dst
, src
[0], src
[1]);
942 brw_set_acc_write_control(p
, 0);
946 assert(brw
->gen
>= 6);
947 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
951 brw_FRC(p
, dst
, src
[0]);
953 case BRW_OPCODE_RNDD
:
954 brw_RNDD(p
, dst
, src
[0]);
956 case BRW_OPCODE_RNDE
:
957 brw_RNDE(p
, dst
, src
[0]);
959 case BRW_OPCODE_RNDZ
:
960 brw_RNDZ(p
, dst
, src
[0]);
964 brw_AND(p
, dst
, src
[0], src
[1]);
967 brw_OR(p
, dst
, src
[0], src
[1]);
970 brw_XOR(p
, dst
, src
[0], src
[1]);
973 brw_NOT(p
, dst
, src
[0]);
976 brw_ASR(p
, dst
, src
[0], src
[1]);
979 brw_SHR(p
, dst
, src
[0], src
[1]);
982 brw_SHL(p
, dst
, src
[0], src
[1]);
986 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
989 brw_SEL(p
, dst
, src
[0], src
[1]);
993 brw_DPH(p
, dst
, src
[0], src
[1]);
997 brw_DP4(p
, dst
, src
[0], src
[1]);
1000 case BRW_OPCODE_DP3
:
1001 brw_DP3(p
, dst
, src
[0], src
[1]);
1004 case BRW_OPCODE_DP2
:
1005 brw_DP2(p
, dst
, src
[0], src
[1]);
1008 case BRW_OPCODE_F32TO16
:
1009 assert(brw
->gen
>= 7);
1010 brw_F32TO16(p
, dst
, src
[0]);
1013 case BRW_OPCODE_F16TO32
:
1014 assert(brw
->gen
>= 7);
1015 brw_F16TO32(p
, dst
, src
[0]);
1018 case BRW_OPCODE_LRP
:
1019 assert(brw
->gen
>= 6);
1020 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1023 case BRW_OPCODE_BFREV
:
1024 assert(brw
->gen
>= 7);
1025 /* BFREV only supports UD type for src and dst. */
1026 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1027 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1029 case BRW_OPCODE_FBH
:
1030 assert(brw
->gen
>= 7);
1031 /* FBH only supports UD type for dst. */
1032 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1034 case BRW_OPCODE_FBL
:
1035 assert(brw
->gen
>= 7);
1036 /* FBL only supports UD type for dst. */
1037 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1039 case BRW_OPCODE_CBIT
:
1040 assert(brw
->gen
>= 7);
1041 /* CBIT only supports UD type for dst. */
1042 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1044 case BRW_OPCODE_ADDC
:
1045 assert(brw
->gen
>= 7);
1046 brw_set_acc_write_control(p
, 1);
1047 brw_ADDC(p
, dst
, src
[0], src
[1]);
1048 brw_set_acc_write_control(p
, 0);
1050 case BRW_OPCODE_SUBB
:
1051 assert(brw
->gen
>= 7);
1052 brw_set_acc_write_control(p
, 1);
1053 brw_SUBB(p
, dst
, src
[0], src
[1]);
1054 brw_set_acc_write_control(p
, 0);
1057 case BRW_OPCODE_BFE
:
1058 assert(brw
->gen
>= 7);
1059 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1062 case BRW_OPCODE_BFI1
:
1063 assert(brw
->gen
>= 7);
1064 brw_BFI1(p
, dst
, src
[0], src
[1]);
1066 case BRW_OPCODE_BFI2
:
1067 assert(brw
->gen
>= 7);
1068 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1072 if (inst
->src
[0].file
!= BAD_FILE
) {
1073 /* The instruction has an embedded compare (only allowed on gen6) */
1074 assert(brw
->gen
== 6);
1075 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1077 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1078 brw_inst
->header
.predicate_control
= inst
->predicate
;
1082 case BRW_OPCODE_ELSE
:
1085 case BRW_OPCODE_ENDIF
:
1090 brw_DO(p
, BRW_EXECUTE_8
);
1093 case BRW_OPCODE_BREAK
:
1095 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1097 case BRW_OPCODE_CONTINUE
:
1098 /* FINISHME: We need to write the loop instruction support still. */
1103 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1106 case BRW_OPCODE_WHILE
:
1110 case SHADER_OPCODE_RCP
:
1111 case SHADER_OPCODE_RSQ
:
1112 case SHADER_OPCODE_SQRT
:
1113 case SHADER_OPCODE_EXP2
:
1114 case SHADER_OPCODE_LOG2
:
1115 case SHADER_OPCODE_SIN
:
1116 case SHADER_OPCODE_COS
:
1117 if (brw
->gen
== 6) {
1118 generate_math1_gen6(inst
, dst
, src
[0]);
1120 /* Also works for Gen7. */
1121 generate_math1_gen4(inst
, dst
, src
[0]);
1125 case SHADER_OPCODE_POW
:
1126 case SHADER_OPCODE_INT_QUOTIENT
:
1127 case SHADER_OPCODE_INT_REMAINDER
:
1128 if (brw
->gen
>= 7) {
1129 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1130 } else if (brw
->gen
== 6) {
1131 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1133 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1137 case SHADER_OPCODE_TEX
:
1138 case SHADER_OPCODE_TXD
:
1139 case SHADER_OPCODE_TXF
:
1140 case SHADER_OPCODE_TXF_MS
:
1141 case SHADER_OPCODE_TXL
:
1142 case SHADER_OPCODE_TXS
:
1143 case SHADER_OPCODE_TG4
:
1144 case SHADER_OPCODE_TG4_OFFSET
:
1145 generate_tex(inst
, dst
, src
[0]);
1148 case VS_OPCODE_URB_WRITE
:
1149 generate_vs_urb_write(inst
);
1152 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1153 generate_scratch_read(inst
, dst
, src
[0]);
1156 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1157 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1160 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1161 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1164 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1165 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1168 case GS_OPCODE_URB_WRITE
:
1169 generate_gs_urb_write(inst
);
1172 case GS_OPCODE_THREAD_END
:
1173 generate_gs_thread_end(inst
);
1176 case GS_OPCODE_SET_WRITE_OFFSET
:
1177 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1180 case GS_OPCODE_SET_VERTEX_COUNT
:
1181 generate_gs_set_vertex_count(dst
, src
[0]);
1184 case GS_OPCODE_SET_DWORD_2_IMMED
:
1185 generate_gs_set_dword_2_immed(dst
, src
[0]);
1188 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1189 generate_gs_prepare_channel_masks(dst
);
1192 case GS_OPCODE_SET_CHANNEL_MASKS
:
1193 generate_gs_set_channel_masks(dst
, src
[0]);
1196 case SHADER_OPCODE_SHADER_TIME_ADD
:
1197 brw_shader_time_add(p
, src
[0],
1198 prog_data
->base
.binding_table
.shader_time_start
);
1199 mark_surface_used(prog_data
->base
.binding_table
.shader_time_start
);
1202 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1203 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1206 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1207 generate_untyped_surface_read(inst
, dst
, src
[0]);
1210 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1211 generate_unpack_flags(inst
, dst
);
1215 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1216 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in VS\n",
1217 opcode_descs
[inst
->opcode
].name
);
1219 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in VS", inst
->opcode
);
1226 vec4_generator::generate_code(exec_list
*instructions
)
1228 int last_native_insn_offset
= 0;
1229 const char *last_annotation_string
= NULL
;
1230 const void *last_annotation_ir
= NULL
;
1232 if (unlikely(debug_flag
)) {
1234 printf("Native code for vertex shader %d:\n", shader_prog
->Name
);
1236 printf("Native code for vertex program %d:\n", prog
->Id
);
1240 foreach_list(node
, instructions
) {
1241 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1242 struct brw_reg src
[3], dst
;
1244 if (unlikely(debug_flag
)) {
1245 if (last_annotation_ir
!= inst
->ir
) {
1246 last_annotation_ir
= inst
->ir
;
1247 if (last_annotation_ir
) {
1250 ((ir_instruction
*) last_annotation_ir
)->print();
1252 const prog_instruction
*vpi
;
1253 vpi
= (const prog_instruction
*) inst
->ir
;
1254 printf("%d: ", (int)(vpi
- prog
->Instructions
));
1255 _mesa_fprint_instruction_opt(stdout
, vpi
, 0,
1256 PROG_PRINT_DEBUG
, NULL
);
1261 if (last_annotation_string
!= inst
->annotation
) {
1262 last_annotation_string
= inst
->annotation
;
1263 if (last_annotation_string
)
1264 printf(" %s\n", last_annotation_string
);
1268 for (unsigned int i
= 0; i
< 3; i
++) {
1269 src
[i
] = inst
->get_src(this->prog_data
, i
);
1271 dst
= inst
->get_dst();
1273 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1274 brw_set_predicate_control(p
, inst
->predicate
);
1275 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1276 brw_set_saturate(p
, inst
->saturate
);
1277 brw_set_mask_control(p
, inst
->force_writemask_all
);
1279 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1281 generate_vec4_instruction(inst
, dst
, src
);
1283 if (inst
->no_dd_clear
|| inst
->no_dd_check
) {
1284 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1285 !"no_dd_check or no_dd_clear set for IR emitting more "
1286 "than 1 instruction");
1288 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
1290 if (inst
->no_dd_clear
)
1291 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
1292 if (inst
->no_dd_check
)
1293 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
1296 if (unlikely(debug_flag
)) {
1297 brw_dump_compile(p
, stdout
,
1298 last_native_insn_offset
, p
->next_insn_offset
);
1301 last_native_insn_offset
= p
->next_insn_offset
;
1304 if (unlikely(debug_flag
)) {
1310 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1311 * emit issues, it doesn't get the jump distances into the output,
1312 * which is often something we want to debug. So this is here in
1313 * case you're doing that.
1315 if (0 && unlikely(debug_flag
)) {
1316 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1321 vec4_generator::generate_assembly(exec_list
*instructions
,
1322 unsigned *assembly_size
)
1324 brw_set_access_mode(p
, BRW_ALIGN_16
);
1325 generate_code(instructions
);
1326 return brw_get_program(p
, assembly_size
);
1329 } /* namespace brw */