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i965/vec4: Do not mark used direct surfaces in VS_OPCODE_PULL_CONSTANT_LOAD
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "glsl/glsl_parser_extras.h"
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26
27 using namespace brw;
28
29 static void
30 generate_math1_gen4(struct brw_codegen *p,
31 vec4_instruction *inst,
32 struct brw_reg dst,
33 struct brw_reg src)
34 {
35 gen4_math(p,
36 dst,
37 brw_math_function(inst->opcode),
38 inst->base_mrf,
39 src,
40 BRW_MATH_PRECISION_FULL);
41 }
42
43 static void
44 check_gen6_math_src_arg(struct brw_reg src)
45 {
46 /* Source swizzles are ignored. */
47 assert(!src.abs);
48 assert(!src.negate);
49 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
50 }
51
52 static void
53 generate_math_gen6(struct brw_codegen *p,
54 vec4_instruction *inst,
55 struct brw_reg dst,
56 struct brw_reg src0,
57 struct brw_reg src1)
58 {
59 /* Can't do writemask because math can't be align16. */
60 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
61 /* Source swizzles are ignored. */
62 check_gen6_math_src_arg(src0);
63 if (src1.file == BRW_GENERAL_REGISTER_FILE)
64 check_gen6_math_src_arg(src1);
65
66 brw_set_default_access_mode(p, BRW_ALIGN_1);
67 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
68 brw_set_default_access_mode(p, BRW_ALIGN_16);
69 }
70
71 static void
72 generate_math2_gen4(struct brw_codegen *p,
73 vec4_instruction *inst,
74 struct brw_reg dst,
75 struct brw_reg src0,
76 struct brw_reg src1)
77 {
78 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
79 * "Message Payload":
80 *
81 * "Operand0[7]. For the INT DIV functions, this operand is the
82 * denominator."
83 * ...
84 * "Operand1[7]. For the INT DIV functions, this operand is the
85 * numerator."
86 */
87 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
88 struct brw_reg &op0 = is_int_div ? src1 : src0;
89 struct brw_reg &op1 = is_int_div ? src0 : src1;
90
91 brw_push_insn_state(p);
92 brw_set_default_saturate(p, false);
93 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
94 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
95 brw_pop_insn_state(p);
96
97 gen4_math(p,
98 dst,
99 brw_math_function(inst->opcode),
100 inst->base_mrf,
101 op0,
102 BRW_MATH_PRECISION_FULL);
103 }
104
105 static void
106 generate_tex(struct brw_codegen *p,
107 struct brw_vue_prog_data *prog_data,
108 vec4_instruction *inst,
109 struct brw_reg dst,
110 struct brw_reg src,
111 struct brw_reg sampler_index)
112 {
113 const struct brw_device_info *devinfo = p->devinfo;
114 int msg_type = -1;
115
116 if (devinfo->gen >= 5) {
117 switch (inst->opcode) {
118 case SHADER_OPCODE_TEX:
119 case SHADER_OPCODE_TXL:
120 if (inst->shadow_compare) {
121 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
122 } else {
123 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
124 }
125 break;
126 case SHADER_OPCODE_TXD:
127 if (inst->shadow_compare) {
128 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
129 assert(devinfo->gen >= 8 || devinfo->is_haswell);
130 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
131 } else {
132 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
133 }
134 break;
135 case SHADER_OPCODE_TXF:
136 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
137 break;
138 case SHADER_OPCODE_TXF_CMS_W:
139 assert(devinfo->gen >= 9);
140 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
141 break;
142 case SHADER_OPCODE_TXF_CMS:
143 if (devinfo->gen >= 7)
144 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
145 else
146 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
147 break;
148 case SHADER_OPCODE_TXF_MCS:
149 assert(devinfo->gen >= 7);
150 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
151 break;
152 case SHADER_OPCODE_TXS:
153 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
154 break;
155 case SHADER_OPCODE_TG4:
156 if (inst->shadow_compare) {
157 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
158 } else {
159 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
160 }
161 break;
162 case SHADER_OPCODE_TG4_OFFSET:
163 if (inst->shadow_compare) {
164 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
165 } else {
166 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
167 }
168 break;
169 case SHADER_OPCODE_SAMPLEINFO:
170 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
171 break;
172 default:
173 unreachable("should not get here: invalid vec4 texture opcode");
174 }
175 } else {
176 switch (inst->opcode) {
177 case SHADER_OPCODE_TEX:
178 case SHADER_OPCODE_TXL:
179 if (inst->shadow_compare) {
180 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
181 assert(inst->mlen == 3);
182 } else {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
184 assert(inst->mlen == 2);
185 }
186 break;
187 case SHADER_OPCODE_TXD:
188 /* There is no sample_d_c message; comparisons are done manually. */
189 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
190 assert(inst->mlen == 4);
191 break;
192 case SHADER_OPCODE_TXF:
193 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
194 assert(inst->mlen == 2);
195 break;
196 case SHADER_OPCODE_TXS:
197 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
198 assert(inst->mlen == 2);
199 break;
200 default:
201 unreachable("should not get here: invalid vec4 texture opcode");
202 }
203 }
204
205 assert(msg_type != -1);
206
207 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
208
209 /* Load the message header if present. If there's a texture offset, we need
210 * to set it up explicitly and load the offset bitfield. Otherwise, we can
211 * use an implied move from g0 to the first message register.
212 */
213 if (inst->header_size != 0) {
214 if (devinfo->gen < 6 && !inst->offset) {
215 /* Set up an implied move from g0 to the MRF. */
216 src = brw_vec8_grf(0, 0);
217 } else {
218 struct brw_reg header =
219 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
220 uint32_t dw2 = 0;
221
222 /* Explicitly set up the message header by copying g0 to the MRF. */
223 brw_push_insn_state(p);
224 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
225 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
226
227 brw_set_default_access_mode(p, BRW_ALIGN_1);
228
229 if (inst->offset)
230 /* Set the texel offset bits in DWord 2. */
231 dw2 = inst->offset;
232
233 if (devinfo->gen >= 9)
234 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
235 * based on bit 22 in the header.
236 */
237 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
238
239 if (dw2)
240 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
241
242 brw_adjust_sampler_state_pointer(p, header, sampler_index);
243 brw_pop_insn_state(p);
244 }
245 }
246
247 uint32_t return_format;
248
249 switch (dst.type) {
250 case BRW_REGISTER_TYPE_D:
251 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
252 break;
253 case BRW_REGISTER_TYPE_UD:
254 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
255 break;
256 default:
257 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
258 break;
259 }
260
261 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
262 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
263 ? prog_data->base.binding_table.gather_texture_start
264 : prog_data->base.binding_table.texture_start;
265
266 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
267 uint32_t sampler = sampler_index.dw1.ud;
268
269 brw_SAMPLE(p,
270 dst,
271 inst->base_mrf,
272 src,
273 sampler + base_binding_table_index,
274 sampler % 16,
275 msg_type,
276 1, /* response length */
277 inst->mlen,
278 inst->header_size != 0,
279 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
280 return_format);
281
282 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
283 } else {
284 /* Non-constant sampler index. */
285
286 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
287 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
288
289 brw_push_insn_state(p);
290 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
291 brw_set_default_access_mode(p, BRW_ALIGN_1);
292
293 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
294 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
295 if (base_binding_table_index)
296 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
297 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
298
299 brw_pop_insn_state(p);
300
301 if (inst->base_mrf != -1)
302 gen6_resolve_implied_move(p, &src, inst->base_mrf);
303
304 /* dst = send(offset, a0.0 | <descriptor>) */
305 brw_inst *insn = brw_send_indirect_message(
306 p, BRW_SFID_SAMPLER, dst, src, addr);
307 brw_set_sampler_message(p, insn,
308 0 /* surface */,
309 0 /* sampler */,
310 msg_type,
311 1 /* rlen */,
312 inst->mlen /* mlen */,
313 inst->header_size != 0 /* header */,
314 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
315 return_format);
316
317 /* visitor knows more than we do about the surface limit required,
318 * so has already done marking.
319 */
320 }
321 }
322
323 static void
324 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
325 {
326 brw_urb_WRITE(p,
327 brw_null_reg(), /* dest */
328 inst->base_mrf, /* starting mrf reg nr */
329 brw_vec8_grf(0, 0), /* src */
330 inst->urb_write_flags,
331 inst->mlen,
332 0, /* response len */
333 inst->offset, /* urb destination offset */
334 BRW_URB_SWIZZLE_INTERLEAVE);
335 }
336
337 static void
338 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
339 {
340 struct brw_reg src = brw_message_reg(inst->base_mrf);
341 brw_urb_WRITE(p,
342 brw_null_reg(), /* dest */
343 inst->base_mrf, /* starting mrf reg nr */
344 src,
345 inst->urb_write_flags,
346 inst->mlen,
347 0, /* response len */
348 inst->offset, /* urb destination offset */
349 BRW_URB_SWIZZLE_INTERLEAVE);
350 }
351
352 static void
353 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
354 {
355 struct brw_reg src = brw_message_reg(inst->base_mrf);
356
357 /* We pass the temporary passed in src0 as the writeback register */
358 brw_urb_WRITE(p,
359 inst->src[0].fixed_hw_reg, /* dest */
360 inst->base_mrf, /* starting mrf reg nr */
361 src,
362 BRW_URB_WRITE_ALLOCATE_COMPLETE,
363 inst->mlen,
364 1, /* response len */
365 inst->offset, /* urb destination offset */
366 BRW_URB_SWIZZLE_INTERLEAVE);
367
368 /* Now put allocated urb handle in dst.0 */
369 brw_push_insn_state(p);
370 brw_set_default_access_mode(p, BRW_ALIGN_1);
371 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
372 brw_MOV(p, get_element_ud(inst->dst.fixed_hw_reg, 0),
373 get_element_ud(inst->src[0].fixed_hw_reg, 0));
374 brw_pop_insn_state(p);
375 }
376
377 static void
378 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
379 {
380 struct brw_reg src = brw_message_reg(inst->base_mrf);
381 brw_urb_WRITE(p,
382 brw_null_reg(), /* dest */
383 inst->base_mrf, /* starting mrf reg nr */
384 src,
385 BRW_URB_WRITE_EOT | inst->urb_write_flags,
386 inst->mlen,
387 0, /* response len */
388 0, /* urb destination offset */
389 BRW_URB_SWIZZLE_INTERLEAVE);
390 }
391
392 static void
393 generate_gs_set_write_offset(struct brw_codegen *p,
394 struct brw_reg dst,
395 struct brw_reg src0,
396 struct brw_reg src1)
397 {
398 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
399 * Header: M0.3):
400 *
401 * Slot 0 Offset. This field, after adding to the Global Offset field
402 * in the message descriptor, specifies the offset (in 256-bit units)
403 * from the start of the URB entry, as referenced by URB Handle 0, at
404 * which the data will be accessed.
405 *
406 * Similar text describes DWORD M0.4, which is slot 1 offset.
407 *
408 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
409 * of the register for geometry shader invocations 0 and 1) by the
410 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
411 *
412 * We can do this with the following EU instruction:
413 *
414 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
415 */
416 brw_push_insn_state(p);
417 brw_set_default_access_mode(p, BRW_ALIGN_1);
418 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
419 assert(p->devinfo->gen >= 7 &&
420 src1.file == BRW_IMMEDIATE_VALUE &&
421 src1.type == BRW_REGISTER_TYPE_UD &&
422 src1.dw1.ud <= USHRT_MAX);
423 if (src0.file == BRW_IMMEDIATE_VALUE) {
424 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
425 brw_imm_ud(src0.dw1.ud * src1.dw1.ud));
426 } else {
427 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
428 retype(src1, BRW_REGISTER_TYPE_UW));
429 }
430 brw_pop_insn_state(p);
431 }
432
433 static void
434 generate_gs_set_vertex_count(struct brw_codegen *p,
435 struct brw_reg dst,
436 struct brw_reg src)
437 {
438 brw_push_insn_state(p);
439 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
440
441 if (p->devinfo->gen >= 8) {
442 /* Move the vertex count into the second MRF for the EOT write. */
443 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
444 src);
445 } else {
446 /* If we think of the src and dst registers as composed of 8 DWORDs each,
447 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
448 * them to WORDs, and then pack them into DWORD 2 of dst.
449 *
450 * It's easier to get the EU to do this if we think of the src and dst
451 * registers as composed of 16 WORDS each; then, we want to pick up the
452 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
453 * of dst.
454 *
455 * We can do that by the following EU instruction:
456 *
457 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
458 */
459 brw_set_default_access_mode(p, BRW_ALIGN_1);
460 brw_MOV(p,
461 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
462 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
463 }
464 brw_pop_insn_state(p);
465 }
466
467 static void
468 generate_gs_svb_write(struct brw_codegen *p,
469 struct brw_vue_prog_data *prog_data,
470 vec4_instruction *inst,
471 struct brw_reg dst,
472 struct brw_reg src0,
473 struct brw_reg src1)
474 {
475 int binding = inst->sol_binding;
476 bool final_write = inst->sol_final_write;
477
478 brw_push_insn_state(p);
479 /* Copy Vertex data into M0.x */
480 brw_MOV(p, stride(dst, 4, 4, 1),
481 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
482
483 /* Send SVB Write */
484 brw_svb_write(p,
485 final_write ? src1 : brw_null_reg(), /* dest == src1 */
486 1, /* msg_reg_nr */
487 dst, /* src0 == previous dst */
488 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
489 final_write); /* send_commit_msg */
490
491 /* Finally, wait for the write commit to occur so that we can proceed to
492 * other things safely.
493 *
494 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
495 *
496 * The write commit does not modify the destination register, but
497 * merely clears the dependency associated with the destination
498 * register. Thus, a simple “mov” instruction using the register as a
499 * source is sufficient to wait for the write commit to occur.
500 */
501 if (final_write) {
502 brw_MOV(p, src1, src1);
503 }
504 brw_pop_insn_state(p);
505 }
506
507 static void
508 generate_gs_svb_set_destination_index(struct brw_codegen *p,
509 vec4_instruction *inst,
510 struct brw_reg dst,
511 struct brw_reg src)
512 {
513 int vertex = inst->sol_vertex;
514 brw_push_insn_state(p);
515 brw_set_default_access_mode(p, BRW_ALIGN_1);
516 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
517 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
518 brw_pop_insn_state(p);
519 }
520
521 static void
522 generate_gs_set_dword_2(struct brw_codegen *p,
523 struct brw_reg dst,
524 struct brw_reg src)
525 {
526 brw_push_insn_state(p);
527 brw_set_default_access_mode(p, BRW_ALIGN_1);
528 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
529 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
530 brw_pop_insn_state(p);
531 }
532
533 static void
534 generate_gs_prepare_channel_masks(struct brw_codegen *p,
535 struct brw_reg dst)
536 {
537 /* We want to left shift just DWORD 4 (the x component belonging to the
538 * second geometry shader invocation) by 4 bits. So generate the
539 * instruction:
540 *
541 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
542 */
543 dst = suboffset(vec1(dst), 4);
544 brw_push_insn_state(p);
545 brw_set_default_access_mode(p, BRW_ALIGN_1);
546 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
547 brw_SHL(p, dst, dst, brw_imm_ud(4));
548 brw_pop_insn_state(p);
549 }
550
551 static void
552 generate_gs_set_channel_masks(struct brw_codegen *p,
553 struct brw_reg dst,
554 struct brw_reg src)
555 {
556 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
557 * Header: M0.5):
558 *
559 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
560 *
561 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
562 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
563 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
564 * channel enable to determine the final channel enable. For the
565 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
566 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
567 * in the writeback message. For the URB_WRITE_OWORD &
568 * URB_WRITE_HWORD messages, when final channel enable is 1 it
569 * indicates that Vertex 1 DATA [3] will be written to the surface.
570 *
571 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
572 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
573 *
574 * 14 Vertex 1 DATA [2] Channel Mask
575 * 13 Vertex 1 DATA [1] Channel Mask
576 * 12 Vertex 1 DATA [0] Channel Mask
577 * 11 Vertex 0 DATA [3] Channel Mask
578 * 10 Vertex 0 DATA [2] Channel Mask
579 * 9 Vertex 0 DATA [1] Channel Mask
580 * 8 Vertex 0 DATA [0] Channel Mask
581 *
582 * (This is from a section of the PRM that is agnostic to the particular
583 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
584 * geometry shader invocations 0 and 1, respectively). Since we have the
585 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
586 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
587 * DWORD 4, we just need to OR them together and store the result in bits
588 * 15:8 of DWORD 5.
589 *
590 * It's easier to get the EU to do this if we think of the src and dst
591 * registers as composed of 32 bytes each; then, we want to pick up the
592 * contents of bytes 0 and 16 from src, OR them together, and store them in
593 * byte 21.
594 *
595 * We can do that by the following EU instruction:
596 *
597 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
598 *
599 * Note: this relies on the source register having zeros in (a) bits 7:4 of
600 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
601 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
602 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
603 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
604 * contain valid channel mask values (which are in the range 0x0-0xf).
605 */
606 dst = retype(dst, BRW_REGISTER_TYPE_UB);
607 src = retype(src, BRW_REGISTER_TYPE_UB);
608 brw_push_insn_state(p);
609 brw_set_default_access_mode(p, BRW_ALIGN_1);
610 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
611 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
612 brw_pop_insn_state(p);
613 }
614
615 static void
616 generate_gs_get_instance_id(struct brw_codegen *p,
617 struct brw_reg dst)
618 {
619 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
620 * and store into dst.0 & dst.4. So generate the instruction:
621 *
622 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
623 */
624 brw_push_insn_state(p);
625 brw_set_default_access_mode(p, BRW_ALIGN_1);
626 dst = retype(dst, BRW_REGISTER_TYPE_UD);
627 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
628 brw_SHR(p, dst, stride(r0, 1, 4, 0),
629 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
630 brw_pop_insn_state(p);
631 }
632
633 static void
634 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
635 struct brw_reg dst,
636 struct brw_reg src0,
637 struct brw_reg src1,
638 struct brw_reg src2)
639 {
640 brw_push_insn_state(p);
641 brw_set_default_access_mode(p, BRW_ALIGN_1);
642 /* Save src0 data in 16:31 bits of dst.0 */
643 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
644 brw_imm_ud(0xffffu));
645 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
646 /* Save src1 data in 0:15 bits of dst.0 */
647 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
648 brw_imm_ud(0xffffu));
649 brw_OR(p, suboffset(vec1(dst), 0),
650 suboffset(vec1(dst), 0),
651 suboffset(vec1(src2), 0));
652 brw_pop_insn_state(p);
653 }
654
655 static void
656 generate_gs_ff_sync(struct brw_codegen *p,
657 vec4_instruction *inst,
658 struct brw_reg dst,
659 struct brw_reg src0,
660 struct brw_reg src1)
661 {
662 /* This opcode uses an implied MRF register for:
663 * - the header of the ff_sync message. And as such it is expected to be
664 * initialized to r0 before calling here.
665 * - the destination where we will write the allocated URB handle.
666 */
667 struct brw_reg header =
668 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
669
670 /* Overwrite dword 0 of the header (SO vertices to write) and
671 * dword 1 (number of primitives written).
672 */
673 brw_push_insn_state(p);
674 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
675 brw_set_default_access_mode(p, BRW_ALIGN_1);
676 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
677 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
678 brw_pop_insn_state(p);
679
680 /* Allocate URB handle in dst */
681 brw_ff_sync(p,
682 dst,
683 0,
684 header,
685 1, /* allocate */
686 1, /* response length */
687 0 /* eot */);
688
689 /* Now put allocated urb handle in header.0 */
690 brw_push_insn_state(p);
691 brw_set_default_access_mode(p, BRW_ALIGN_1);
692 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
693 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
694
695 /* src1 is not an immediate when we use transform feedback */
696 if (src1.file != BRW_IMMEDIATE_VALUE)
697 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
698
699 brw_pop_insn_state(p);
700 }
701
702 static void
703 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
704 {
705 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
706 struct brw_reg src = brw_vec8_grf(0, 0);
707 brw_push_insn_state(p);
708 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
709 brw_set_default_access_mode(p, BRW_ALIGN_1);
710 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
711 brw_pop_insn_state(p);
712 }
713
714 static void
715 generate_oword_dual_block_offsets(struct brw_codegen *p,
716 struct brw_reg m1,
717 struct brw_reg index)
718 {
719 int second_vertex_offset;
720
721 if (p->devinfo->gen >= 6)
722 second_vertex_offset = 1;
723 else
724 second_vertex_offset = 16;
725
726 m1 = retype(m1, BRW_REGISTER_TYPE_D);
727
728 /* Set up M1 (message payload). Only the block offsets in M1.0 and
729 * M1.4 are used, and the rest are ignored.
730 */
731 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
732 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
733 struct brw_reg index_0 = suboffset(vec1(index), 0);
734 struct brw_reg index_4 = suboffset(vec1(index), 4);
735
736 brw_push_insn_state(p);
737 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
738 brw_set_default_access_mode(p, BRW_ALIGN_1);
739
740 brw_MOV(p, m1_0, index_0);
741
742 if (index.file == BRW_IMMEDIATE_VALUE) {
743 index_4.dw1.ud += second_vertex_offset;
744 brw_MOV(p, m1_4, index_4);
745 } else {
746 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
747 }
748
749 brw_pop_insn_state(p);
750 }
751
752 static void
753 generate_unpack_flags(struct brw_codegen *p,
754 struct brw_reg dst)
755 {
756 brw_push_insn_state(p);
757 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
758 brw_set_default_access_mode(p, BRW_ALIGN_1);
759
760 struct brw_reg flags = brw_flag_reg(0, 0);
761 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
762 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
763
764 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
765 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
766 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
767
768 brw_pop_insn_state(p);
769 }
770
771 static void
772 generate_scratch_read(struct brw_codegen *p,
773 vec4_instruction *inst,
774 struct brw_reg dst,
775 struct brw_reg index)
776 {
777 const struct brw_device_info *devinfo = p->devinfo;
778 struct brw_reg header = brw_vec8_grf(0, 0);
779
780 gen6_resolve_implied_move(p, &header, inst->base_mrf);
781
782 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
783 index);
784
785 uint32_t msg_type;
786
787 if (devinfo->gen >= 6)
788 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
789 else if (devinfo->gen == 5 || devinfo->is_g4x)
790 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
791 else
792 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
793
794 /* Each of the 8 channel enables is considered for whether each
795 * dword is written.
796 */
797 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
798 brw_set_dest(p, send, dst);
799 brw_set_src0(p, send, header);
800 if (devinfo->gen < 6)
801 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
802 brw_set_dp_read_message(p, send,
803 255, /* binding table index: stateless access */
804 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
805 msg_type,
806 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
807 2, /* mlen */
808 true, /* header_present */
809 1 /* rlen */);
810 }
811
812 static void
813 generate_scratch_write(struct brw_codegen *p,
814 vec4_instruction *inst,
815 struct brw_reg dst,
816 struct brw_reg src,
817 struct brw_reg index)
818 {
819 const struct brw_device_info *devinfo = p->devinfo;
820 struct brw_reg header = brw_vec8_grf(0, 0);
821 bool write_commit;
822
823 /* If the instruction is predicated, we'll predicate the send, not
824 * the header setup.
825 */
826 brw_set_default_predicate_control(p, false);
827
828 gen6_resolve_implied_move(p, &header, inst->base_mrf);
829
830 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
831 index);
832
833 brw_MOV(p,
834 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
835 retype(src, BRW_REGISTER_TYPE_D));
836
837 uint32_t msg_type;
838
839 if (devinfo->gen >= 7)
840 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
841 else if (devinfo->gen == 6)
842 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
843 else
844 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
845
846 brw_set_default_predicate_control(p, inst->predicate);
847
848 /* Pre-gen6, we have to specify write commits to ensure ordering
849 * between reads and writes within a thread. Afterwards, that's
850 * guaranteed and write commits only matter for inter-thread
851 * synchronization.
852 */
853 if (devinfo->gen >= 6) {
854 write_commit = false;
855 } else {
856 /* The visitor set up our destination register to be g0. This
857 * means that when the next read comes along, we will end up
858 * reading from g0 and causing a block on the write commit. For
859 * write-after-read, we are relying on the value of the previous
860 * read being used (and thus blocking on completion) before our
861 * write is executed. This means we have to be careful in
862 * instruction scheduling to not violate this assumption.
863 */
864 write_commit = true;
865 }
866
867 /* Each of the 8 channel enables is considered for whether each
868 * dword is written.
869 */
870 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
871 brw_set_dest(p, send, dst);
872 brw_set_src0(p, send, header);
873 if (devinfo->gen < 6)
874 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
875 brw_set_dp_write_message(p, send,
876 255, /* binding table index: stateless access */
877 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
878 msg_type,
879 3, /* mlen */
880 true, /* header present */
881 false, /* not a render target write */
882 write_commit, /* rlen */
883 false, /* eot */
884 write_commit);
885 }
886
887 static void
888 generate_pull_constant_load(struct brw_codegen *p,
889 struct brw_vue_prog_data *prog_data,
890 vec4_instruction *inst,
891 struct brw_reg dst,
892 struct brw_reg index,
893 struct brw_reg offset)
894 {
895 const struct brw_device_info *devinfo = p->devinfo;
896 assert(index.file == BRW_IMMEDIATE_VALUE &&
897 index.type == BRW_REGISTER_TYPE_UD);
898 uint32_t surf_index = index.dw1.ud;
899
900 struct brw_reg header = brw_vec8_grf(0, 0);
901
902 gen6_resolve_implied_move(p, &header, inst->base_mrf);
903
904 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
905 offset);
906
907 uint32_t msg_type;
908
909 if (devinfo->gen >= 6)
910 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
911 else if (devinfo->gen == 5 || devinfo->is_g4x)
912 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
913 else
914 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
915
916 /* Each of the 8 channel enables is considered for whether each
917 * dword is written.
918 */
919 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
920 brw_set_dest(p, send, dst);
921 brw_set_src0(p, send, header);
922 if (devinfo->gen < 6)
923 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
924 brw_set_dp_read_message(p, send,
925 surf_index,
926 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
927 msg_type,
928 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
929 2, /* mlen */
930 true, /* header_present */
931 1 /* rlen */);
932 }
933
934 static void
935 generate_get_buffer_size(struct brw_codegen *p,
936 struct brw_vue_prog_data *prog_data,
937 vec4_instruction *inst,
938 struct brw_reg dst,
939 struct brw_reg src,
940 struct brw_reg surf_index)
941 {
942 assert(p->devinfo->gen >= 7);
943 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
944 surf_index.file == BRW_IMMEDIATE_VALUE);
945
946 brw_SAMPLE(p,
947 dst,
948 inst->base_mrf,
949 src,
950 surf_index.dw1.ud,
951 0,
952 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
953 1, /* response length */
954 inst->mlen,
955 inst->header_size > 0,
956 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
957 BRW_SAMPLER_RETURN_FORMAT_SINT32);
958
959 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
960 }
961
962 static void
963 generate_pull_constant_load_gen7(struct brw_codegen *p,
964 struct brw_vue_prog_data *prog_data,
965 vec4_instruction *inst,
966 struct brw_reg dst,
967 struct brw_reg surf_index,
968 struct brw_reg offset)
969 {
970 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
971
972 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
973
974 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
975 brw_set_dest(p, insn, dst);
976 brw_set_src0(p, insn, offset);
977 brw_set_sampler_message(p, insn,
978 surf_index.dw1.ud,
979 0, /* LD message ignores sampler unit */
980 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
981 1, /* rlen */
982 inst->mlen,
983 inst->header_size != 0,
984 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
985 0);
986 } else {
987
988 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
989
990 brw_push_insn_state(p);
991 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
992 brw_set_default_access_mode(p, BRW_ALIGN_1);
993
994 /* a0.0 = surf_index & 0xff */
995 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
996 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
997 brw_set_dest(p, insn_and, addr);
998 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
999 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1000
1001 brw_pop_insn_state(p);
1002
1003 /* dst = send(offset, a0.0 | <descriptor>) */
1004 brw_inst *insn = brw_send_indirect_message(
1005 p, BRW_SFID_SAMPLER, dst, offset, addr);
1006 brw_set_sampler_message(p, insn,
1007 0 /* surface */,
1008 0 /* sampler */,
1009 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1010 1 /* rlen */,
1011 inst->mlen,
1012 inst->header_size != 0,
1013 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1014 0);
1015 }
1016 }
1017
1018 static void
1019 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1020 vec4_instruction *inst,
1021 struct brw_reg dst)
1022 {
1023 brw_push_insn_state(p);
1024 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1025
1026 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1027 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1028
1029 brw_set_default_access_mode(p, BRW_ALIGN_1);
1030 brw_MOV(p, get_element_ud(dst, 2),
1031 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1032
1033 brw_pop_insn_state(p);
1034 }
1035
1036 static void
1037 generate_code(struct brw_codegen *p,
1038 const struct brw_compiler *compiler,
1039 void *log_data,
1040 const nir_shader *nir,
1041 struct brw_vue_prog_data *prog_data,
1042 const struct cfg_t *cfg)
1043 {
1044 const struct brw_device_info *devinfo = p->devinfo;
1045 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
1046 bool debug_flag = INTEL_DEBUG &
1047 intel_debug_flag_for_shader_stage(nir->stage);
1048 struct annotation_info annotation;
1049 memset(&annotation, 0, sizeof(annotation));
1050 int loop_count = 0;
1051
1052 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1053 struct brw_reg src[3], dst;
1054
1055 if (unlikely(debug_flag))
1056 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1057
1058 for (unsigned int i = 0; i < 3; i++) {
1059 src[i] = inst->src[i].fixed_hw_reg;
1060 }
1061 dst = inst->dst.fixed_hw_reg;
1062
1063 brw_set_default_predicate_control(p, inst->predicate);
1064 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1065 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1066 brw_set_default_saturate(p, inst->saturate);
1067 brw_set_default_mask_control(p, inst->force_writemask_all);
1068 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1069
1070 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1071 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1072
1073 unsigned pre_emit_nr_insn = p->nr_insn;
1074
1075 if (dst.width == BRW_WIDTH_4) {
1076 /* This happens in attribute fixups for "dual instanced" geometry
1077 * shaders, since they use attributes that are vec4's. Since the exec
1078 * width is only 4, it's essential that the caller set
1079 * force_writemask_all in order to make sure the instruction is executed
1080 * regardless of which channels are enabled.
1081 */
1082 assert(inst->force_writemask_all);
1083
1084 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1085 * the following register region restrictions (from Graphics BSpec:
1086 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1087 * > Register Region Restrictions)
1088 *
1089 * 1. ExecSize must be greater than or equal to Width.
1090 *
1091 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1092 * to Width * HorzStride."
1093 */
1094 for (int i = 0; i < 3; i++) {
1095 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1096 src[i] = stride(src[i], 4, 4, 1);
1097 }
1098 }
1099
1100 switch (inst->opcode) {
1101 case VEC4_OPCODE_UNPACK_UNIFORM:
1102 case BRW_OPCODE_MOV:
1103 brw_MOV(p, dst, src[0]);
1104 break;
1105 case BRW_OPCODE_ADD:
1106 brw_ADD(p, dst, src[0], src[1]);
1107 break;
1108 case BRW_OPCODE_MUL:
1109 brw_MUL(p, dst, src[0], src[1]);
1110 break;
1111 case BRW_OPCODE_MACH:
1112 brw_MACH(p, dst, src[0], src[1]);
1113 break;
1114
1115 case BRW_OPCODE_MAD:
1116 assert(devinfo->gen >= 6);
1117 brw_MAD(p, dst, src[0], src[1], src[2]);
1118 break;
1119
1120 case BRW_OPCODE_FRC:
1121 brw_FRC(p, dst, src[0]);
1122 break;
1123 case BRW_OPCODE_RNDD:
1124 brw_RNDD(p, dst, src[0]);
1125 break;
1126 case BRW_OPCODE_RNDE:
1127 brw_RNDE(p, dst, src[0]);
1128 break;
1129 case BRW_OPCODE_RNDZ:
1130 brw_RNDZ(p, dst, src[0]);
1131 break;
1132
1133 case BRW_OPCODE_AND:
1134 brw_AND(p, dst, src[0], src[1]);
1135 break;
1136 case BRW_OPCODE_OR:
1137 brw_OR(p, dst, src[0], src[1]);
1138 break;
1139 case BRW_OPCODE_XOR:
1140 brw_XOR(p, dst, src[0], src[1]);
1141 break;
1142 case BRW_OPCODE_NOT:
1143 brw_NOT(p, dst, src[0]);
1144 break;
1145 case BRW_OPCODE_ASR:
1146 brw_ASR(p, dst, src[0], src[1]);
1147 break;
1148 case BRW_OPCODE_SHR:
1149 brw_SHR(p, dst, src[0], src[1]);
1150 break;
1151 case BRW_OPCODE_SHL:
1152 brw_SHL(p, dst, src[0], src[1]);
1153 break;
1154
1155 case BRW_OPCODE_CMP:
1156 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1157 break;
1158 case BRW_OPCODE_SEL:
1159 brw_SEL(p, dst, src[0], src[1]);
1160 break;
1161
1162 case BRW_OPCODE_DPH:
1163 brw_DPH(p, dst, src[0], src[1]);
1164 break;
1165
1166 case BRW_OPCODE_DP4:
1167 brw_DP4(p, dst, src[0], src[1]);
1168 break;
1169
1170 case BRW_OPCODE_DP3:
1171 brw_DP3(p, dst, src[0], src[1]);
1172 break;
1173
1174 case BRW_OPCODE_DP2:
1175 brw_DP2(p, dst, src[0], src[1]);
1176 break;
1177
1178 case BRW_OPCODE_F32TO16:
1179 assert(devinfo->gen >= 7);
1180 brw_F32TO16(p, dst, src[0]);
1181 break;
1182
1183 case BRW_OPCODE_F16TO32:
1184 assert(devinfo->gen >= 7);
1185 brw_F16TO32(p, dst, src[0]);
1186 break;
1187
1188 case BRW_OPCODE_LRP:
1189 assert(devinfo->gen >= 6);
1190 brw_LRP(p, dst, src[0], src[1], src[2]);
1191 break;
1192
1193 case BRW_OPCODE_BFREV:
1194 assert(devinfo->gen >= 7);
1195 /* BFREV only supports UD type for src and dst. */
1196 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1197 retype(src[0], BRW_REGISTER_TYPE_UD));
1198 break;
1199 case BRW_OPCODE_FBH:
1200 assert(devinfo->gen >= 7);
1201 /* FBH only supports UD type for dst. */
1202 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1203 break;
1204 case BRW_OPCODE_FBL:
1205 assert(devinfo->gen >= 7);
1206 /* FBL only supports UD type for dst. */
1207 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1208 break;
1209 case BRW_OPCODE_CBIT:
1210 assert(devinfo->gen >= 7);
1211 /* CBIT only supports UD type for dst. */
1212 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1213 break;
1214 case BRW_OPCODE_ADDC:
1215 assert(devinfo->gen >= 7);
1216 brw_ADDC(p, dst, src[0], src[1]);
1217 break;
1218 case BRW_OPCODE_SUBB:
1219 assert(devinfo->gen >= 7);
1220 brw_SUBB(p, dst, src[0], src[1]);
1221 break;
1222 case BRW_OPCODE_MAC:
1223 brw_MAC(p, dst, src[0], src[1]);
1224 break;
1225
1226 case BRW_OPCODE_BFE:
1227 assert(devinfo->gen >= 7);
1228 brw_BFE(p, dst, src[0], src[1], src[2]);
1229 break;
1230
1231 case BRW_OPCODE_BFI1:
1232 assert(devinfo->gen >= 7);
1233 brw_BFI1(p, dst, src[0], src[1]);
1234 break;
1235 case BRW_OPCODE_BFI2:
1236 assert(devinfo->gen >= 7);
1237 brw_BFI2(p, dst, src[0], src[1], src[2]);
1238 break;
1239
1240 case BRW_OPCODE_IF:
1241 if (inst->src[0].file != BAD_FILE) {
1242 /* The instruction has an embedded compare (only allowed on gen6) */
1243 assert(devinfo->gen == 6);
1244 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1245 } else {
1246 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1247 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1248 }
1249 break;
1250
1251 case BRW_OPCODE_ELSE:
1252 brw_ELSE(p);
1253 break;
1254 case BRW_OPCODE_ENDIF:
1255 brw_ENDIF(p);
1256 break;
1257
1258 case BRW_OPCODE_DO:
1259 brw_DO(p, BRW_EXECUTE_8);
1260 break;
1261
1262 case BRW_OPCODE_BREAK:
1263 brw_BREAK(p);
1264 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1265 break;
1266 case BRW_OPCODE_CONTINUE:
1267 brw_CONT(p);
1268 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1269 break;
1270
1271 case BRW_OPCODE_WHILE:
1272 brw_WHILE(p);
1273 loop_count++;
1274 break;
1275
1276 case SHADER_OPCODE_RCP:
1277 case SHADER_OPCODE_RSQ:
1278 case SHADER_OPCODE_SQRT:
1279 case SHADER_OPCODE_EXP2:
1280 case SHADER_OPCODE_LOG2:
1281 case SHADER_OPCODE_SIN:
1282 case SHADER_OPCODE_COS:
1283 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1284 if (devinfo->gen >= 7) {
1285 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1286 brw_null_reg());
1287 } else if (devinfo->gen == 6) {
1288 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1289 } else {
1290 generate_math1_gen4(p, inst, dst, src[0]);
1291 }
1292 break;
1293
1294 case SHADER_OPCODE_POW:
1295 case SHADER_OPCODE_INT_QUOTIENT:
1296 case SHADER_OPCODE_INT_REMAINDER:
1297 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1298 if (devinfo->gen >= 7) {
1299 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1300 } else if (devinfo->gen == 6) {
1301 generate_math_gen6(p, inst, dst, src[0], src[1]);
1302 } else {
1303 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1304 }
1305 break;
1306
1307 case SHADER_OPCODE_TEX:
1308 case SHADER_OPCODE_TXD:
1309 case SHADER_OPCODE_TXF:
1310 case SHADER_OPCODE_TXF_CMS:
1311 case SHADER_OPCODE_TXF_CMS_W:
1312 case SHADER_OPCODE_TXF_MCS:
1313 case SHADER_OPCODE_TXL:
1314 case SHADER_OPCODE_TXS:
1315 case SHADER_OPCODE_TG4:
1316 case SHADER_OPCODE_TG4_OFFSET:
1317 case SHADER_OPCODE_SAMPLEINFO:
1318 generate_tex(p, prog_data, inst, dst, src[0], src[1]);
1319 break;
1320
1321 case VS_OPCODE_URB_WRITE:
1322 generate_vs_urb_write(p, inst);
1323 break;
1324
1325 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1326 generate_scratch_read(p, inst, dst, src[0]);
1327 break;
1328
1329 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1330 generate_scratch_write(p, inst, dst, src[0], src[1]);
1331 break;
1332
1333 case VS_OPCODE_PULL_CONSTANT_LOAD:
1334 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1335 break;
1336
1337 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1338 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1339 break;
1340
1341 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1342 generate_set_simd4x2_header_gen9(p, inst, dst);
1343 break;
1344
1345
1346 case VS_OPCODE_GET_BUFFER_SIZE:
1347 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1348 break;
1349
1350 case GS_OPCODE_URB_WRITE:
1351 generate_gs_urb_write(p, inst);
1352 break;
1353
1354 case GS_OPCODE_URB_WRITE_ALLOCATE:
1355 generate_gs_urb_write_allocate(p, inst);
1356 break;
1357
1358 case GS_OPCODE_SVB_WRITE:
1359 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1360 break;
1361
1362 case GS_OPCODE_SVB_SET_DST_INDEX:
1363 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1364 break;
1365
1366 case GS_OPCODE_THREAD_END:
1367 generate_gs_thread_end(p, inst);
1368 break;
1369
1370 case GS_OPCODE_SET_WRITE_OFFSET:
1371 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1372 break;
1373
1374 case GS_OPCODE_SET_VERTEX_COUNT:
1375 generate_gs_set_vertex_count(p, dst, src[0]);
1376 break;
1377
1378 case GS_OPCODE_FF_SYNC:
1379 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1380 break;
1381
1382 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1383 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1384 break;
1385
1386 case GS_OPCODE_SET_PRIMITIVE_ID:
1387 generate_gs_set_primitive_id(p, dst);
1388 break;
1389
1390 case GS_OPCODE_SET_DWORD_2:
1391 generate_gs_set_dword_2(p, dst, src[0]);
1392 break;
1393
1394 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1395 generate_gs_prepare_channel_masks(p, dst);
1396 break;
1397
1398 case GS_OPCODE_SET_CHANNEL_MASKS:
1399 generate_gs_set_channel_masks(p, dst, src[0]);
1400 break;
1401
1402 case GS_OPCODE_GET_INSTANCE_ID:
1403 generate_gs_get_instance_id(p, dst);
1404 break;
1405
1406 case SHADER_OPCODE_SHADER_TIME_ADD:
1407 brw_shader_time_add(p, src[0],
1408 prog_data->base.binding_table.shader_time_start);
1409 brw_mark_surface_used(&prog_data->base,
1410 prog_data->base.binding_table.shader_time_start);
1411 break;
1412
1413 case SHADER_OPCODE_UNTYPED_ATOMIC:
1414 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1415 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
1416 !inst->dst.is_null());
1417 break;
1418
1419 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1420 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1421 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1422 src[2].dw1.ud);
1423 break;
1424
1425 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1426 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1427 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1428 src[2].dw1.ud);
1429 break;
1430
1431 case SHADER_OPCODE_TYPED_ATOMIC:
1432 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1433 brw_typed_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
1434 !inst->dst.is_null());
1435 break;
1436
1437 case SHADER_OPCODE_TYPED_SURFACE_READ:
1438 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1439 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1440 src[2].dw1.ud);
1441 break;
1442
1443 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1444 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1445 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1446 src[2].dw1.ud);
1447 break;
1448
1449 case SHADER_OPCODE_MEMORY_FENCE:
1450 brw_memory_fence(p, dst);
1451 break;
1452
1453 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1454 brw_find_live_channel(p, dst);
1455 break;
1456
1457 case SHADER_OPCODE_BROADCAST:
1458 brw_broadcast(p, dst, src[0], src[1]);
1459 break;
1460
1461 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1462 generate_unpack_flags(p, dst);
1463 break;
1464
1465 case VEC4_OPCODE_MOV_BYTES: {
1466 /* Moves the low byte from each channel, using an Align1 access mode
1467 * and a <4,1,0> source region.
1468 */
1469 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1470 src[0].type == BRW_REGISTER_TYPE_B);
1471
1472 brw_set_default_access_mode(p, BRW_ALIGN_1);
1473 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1474 src[0].width = BRW_WIDTH_1;
1475 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1476 brw_MOV(p, dst, src[0]);
1477 brw_set_default_access_mode(p, BRW_ALIGN_16);
1478 break;
1479 }
1480
1481 case VEC4_OPCODE_PACK_BYTES: {
1482 /* Is effectively:
1483 *
1484 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1485 *
1486 * but destinations' only regioning is horizontal stride, so instead we
1487 * have to use two instructions:
1488 *
1489 * mov(4) dst<1>:UB src<4,1,0>:UB
1490 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1491 *
1492 * where they pack the four bytes from the low and high four DW.
1493 */
1494 assert(_mesa_is_pow_two(dst.dw1.bits.writemask) &&
1495 dst.dw1.bits.writemask != 0);
1496 unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
1497
1498 dst.type = BRW_REGISTER_TYPE_UB;
1499
1500 brw_set_default_access_mode(p, BRW_ALIGN_1);
1501
1502 src[0].type = BRW_REGISTER_TYPE_UB;
1503 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1504 src[0].width = BRW_WIDTH_1;
1505 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1506 dst.subnr = offset * 4;
1507 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1508 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1509 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1510 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1511
1512 src[0].subnr = 16;
1513 dst.subnr = 16 + offset * 4;
1514 insn = brw_MOV(p, dst, src[0]);
1515 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1516 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1517 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1518
1519 brw_set_default_access_mode(p, BRW_ALIGN_16);
1520 break;
1521 }
1522
1523 default:
1524 unreachable("Unsupported opcode");
1525 }
1526
1527 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1528 /* Handled dependency hints in the generator. */
1529
1530 assert(!inst->conditional_mod);
1531 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1532 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1533 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1534 "emitting more than 1 instruction");
1535
1536 brw_inst *last = &p->store[pre_emit_nr_insn];
1537
1538 if (inst->conditional_mod)
1539 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1540 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1541 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1542 }
1543 }
1544
1545 brw_set_uip_jip(p);
1546 annotation_finalize(&annotation, p->next_insn_offset);
1547
1548 int before_size = p->next_insn_offset;
1549 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1550 int after_size = p->next_insn_offset;
1551
1552 if (unlikely(debug_flag)) {
1553 fprintf(stderr, "Native code for %s %s shader %s:\n",
1554 nir->info.label ? nir->info.label : "unnamed",
1555 _mesa_shader_stage_to_string(nir->stage), nir->info.name);
1556
1557 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles."
1558 "Compacted %d to %d bytes (%.0f%%)\n",
1559 stage_abbrev,
1560 before_size / 16, loop_count, cfg->cycle_count, before_size, after_size,
1561 100.0f * (before_size - after_size) / before_size);
1562
1563 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1564 p->devinfo);
1565 ralloc_free(annotation.ann);
1566 }
1567
1568 compiler->shader_debug_log(log_data,
1569 "%s vec4 shader: %d inst, %d loops, %u cycles, "
1570 "compacted %d to %d bytes.\n",
1571 stage_abbrev, before_size / 16,
1572 loop_count, cfg->cycle_count,
1573 before_size, after_size);
1574 }
1575
1576 extern "C" const unsigned *
1577 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
1578 void *log_data,
1579 void *mem_ctx,
1580 const nir_shader *nir,
1581 struct brw_vue_prog_data *prog_data,
1582 const struct cfg_t *cfg,
1583 unsigned *out_assembly_size)
1584 {
1585 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
1586 brw_init_codegen(compiler->devinfo, p, mem_ctx);
1587 brw_set_default_access_mode(p, BRW_ALIGN_16);
1588
1589 generate_code(p, compiler, log_data, nir, prog_data, cfg);
1590
1591 return brw_get_program(p, out_assembly_size);
1592 }