1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 unreachable("not reached");
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].fixed_hw_reg
.dw1
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].fixed_hw_reg
.dw1
.d
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].fixed_hw_reg
.dw1
.ud
);
96 unreachable("not reached");
101 brw_reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
102 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
103 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
105 brw_reg
= retype(brw_reg
, src
[i
].type
);
106 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
108 brw_reg
= brw_abs(brw_reg
);
110 brw_reg
= negate(brw_reg
);
112 /* This should have been moved to pull constants. */
113 assert(!src
[i
].reladdr
);
117 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 unreachable("not reached");
133 vec4_generator::vec4_generator(struct brw_context
*brw
,
134 struct gl_shader_program
*shader_prog
,
135 struct gl_program
*prog
,
136 struct brw_vec4_prog_data
*prog_data
,
139 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
140 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
142 p
= rzalloc(mem_ctx
, struct brw_compile
);
143 brw_init_compile(brw
, p
, mem_ctx
);
146 vec4_generator::~vec4_generator()
151 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
157 brw_math_function(inst
->opcode
),
160 BRW_MATH_DATA_VECTOR
,
161 BRW_MATH_PRECISION_FULL
);
165 check_gen6_math_src_arg(struct brw_reg src
)
167 /* Source swizzles are ignored. */
170 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
174 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
179 /* Can't do writemask because math can't be align16. */
180 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0
);
183 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
184 check_gen6_math_src_arg(src1
);
186 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
187 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
188 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
192 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * "Operand1[7]. For the INT DIV functions, this operand is the
206 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
207 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
208 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
210 brw_push_insn_state(p
);
211 brw_set_default_saturate(p
, false);
212 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
213 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
214 brw_pop_insn_state(p
);
218 brw_math_function(inst
->opcode
),
221 BRW_MATH_DATA_VECTOR
,
222 BRW_MATH_PRECISION_FULL
);
226 vec4_generator::generate_tex(vec4_instruction
*inst
,
229 struct brw_reg sampler_index
)
234 switch (inst
->opcode
) {
235 case SHADER_OPCODE_TEX
:
236 case SHADER_OPCODE_TXL
:
237 if (inst
->shadow_compare
) {
238 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
240 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
243 case SHADER_OPCODE_TXD
:
244 if (inst
->shadow_compare
) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw
->gen
>= 8 || brw
->is_haswell
);
247 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
249 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
252 case SHADER_OPCODE_TXF
:
253 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
255 case SHADER_OPCODE_TXF_CMS
:
257 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
259 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
261 case SHADER_OPCODE_TXF_MCS
:
262 assert(brw
->gen
>= 7);
263 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
265 case SHADER_OPCODE_TXS
:
266 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
268 case SHADER_OPCODE_TG4
:
269 if (inst
->shadow_compare
) {
270 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
272 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
275 case SHADER_OPCODE_TG4_OFFSET
:
276 if (inst
->shadow_compare
) {
277 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
279 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
283 unreachable("should not get here: invalid vec4 texture opcode");
286 switch (inst
->opcode
) {
287 case SHADER_OPCODE_TEX
:
288 case SHADER_OPCODE_TXL
:
289 if (inst
->shadow_compare
) {
290 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
291 assert(inst
->mlen
== 3);
293 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
294 assert(inst
->mlen
== 2);
297 case SHADER_OPCODE_TXD
:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
300 assert(inst
->mlen
== 4);
302 case SHADER_OPCODE_TXF
:
303 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
304 assert(inst
->mlen
== 2);
306 case SHADER_OPCODE_TXS
:
307 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
308 assert(inst
->mlen
== 2);
311 unreachable("should not get here: invalid vec4 texture opcode");
315 assert(msg_type
!= -1);
317 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
318 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
320 uint32_t sampler
= sampler_index
.dw1
.ud
;
322 /* Load the message header if present. If there's a texture offset, we need
323 * to set it up explicitly and load the offset bitfield. Otherwise, we can
324 * use an implied move from g0 to the first message register.
326 if (inst
->header_present
) {
327 if (brw
->gen
< 6 && !inst
->texture_offset
) {
328 /* Set up an implied move from g0 to the MRF. */
329 src
= brw_vec8_grf(0, 0);
331 struct brw_reg header
=
332 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
334 /* Explicitly set up the message header by copying g0 to the MRF. */
335 brw_push_insn_state(p
);
336 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
337 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
339 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
341 if (inst
->texture_offset
) {
342 /* Set the texel offset bits in DWord 2. */
343 brw_MOV(p
, get_element_ud(header
, 2),
344 brw_imm_ud(inst
->texture_offset
));
348 /* The "Sampler Index" field can only store values between 0 and 15.
349 * However, we can add an offset to the "Sampler State Pointer"
350 * field, effectively selecting a different set of 16 samplers.
352 * The "Sampler State Pointer" needs to be aligned to a 32-byte
353 * offset, and each sampler state is only 16-bytes, so we can't
354 * exclusively use the offset - we have to use both.
356 const int sampler_state_size
= 16; /* 16 bytes */
357 assert(brw
->gen
>= 8 || brw
->is_haswell
);
359 get_element_ud(header
, 3),
360 get_element_ud(brw_vec8_grf(0, 0), 3),
361 brw_imm_ud(16 * (sampler
/ 16) * sampler_state_size
));
363 brw_pop_insn_state(p
);
367 uint32_t return_format
;
370 case BRW_REGISTER_TYPE_D
:
371 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
373 case BRW_REGISTER_TYPE_UD
:
374 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
377 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
381 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
382 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
383 ? prog_data
->base
.binding_table
.gather_texture_start
384 : prog_data
->base
.binding_table
.texture_start
) + sampler
;
393 1, /* response length */
395 inst
->header_present
,
396 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
399 brw_mark_surface_used(&prog_data
->base
, surface_index
);
403 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
406 brw_null_reg(), /* dest */
407 inst
->base_mrf
, /* starting mrf reg nr */
408 brw_vec8_grf(0, 0), /* src */
409 inst
->urb_write_flags
,
411 0, /* response len */
412 inst
->offset
, /* urb destination offset */
413 BRW_URB_SWIZZLE_INTERLEAVE
);
417 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
419 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
421 brw_null_reg(), /* dest */
422 inst
->base_mrf
, /* starting mrf reg nr */
424 inst
->urb_write_flags
,
426 0, /* response len */
427 inst
->offset
, /* urb destination offset */
428 BRW_URB_SWIZZLE_INTERLEAVE
);
432 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
434 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
436 brw_null_reg(), /* dest */
437 inst
->base_mrf
, /* starting mrf reg nr */
441 0, /* response len */
442 0, /* urb destination offset */
443 BRW_URB_SWIZZLE_INTERLEAVE
);
447 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
451 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
454 * Slot 0 Offset. This field, after adding to the Global Offset field
455 * in the message descriptor, specifies the offset (in 256-bit units)
456 * from the start of the URB entry, as referenced by URB Handle 0, at
457 * which the data will be accessed.
459 * Similar text describes DWORD M0.4, which is slot 1 offset.
461 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
462 * of the register for geometry shader invocations 0 and 1) by the
463 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
465 * We can do this with the following EU instruction:
467 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
469 brw_push_insn_state(p
);
470 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
471 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
472 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
474 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
475 brw_pop_insn_state(p
);
479 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
482 brw_push_insn_state(p
);
483 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
484 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
486 /* If we think of the src and dst registers as composed of 8 DWORDs each,
487 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
488 * them to WORDs, and then pack them into DWORD 2 of dst.
490 * It's easier to get the EU to do this if we think of the src and dst
491 * registers as composed of 16 WORDS each; then, we want to pick up the
492 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
495 * We can do that by the following EU instruction:
497 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
499 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
500 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
501 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
502 brw_pop_insn_state(p
);
506 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
509 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
511 brw_push_insn_state(p
);
512 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
513 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
514 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
515 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
516 brw_pop_insn_state(p
);
520 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
522 /* We want to left shift just DWORD 4 (the x component belonging to the
523 * second geometry shader invocation) by 4 bits. So generate the
526 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
528 dst
= suboffset(vec1(dst
), 4);
529 brw_push_insn_state(p
);
530 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
531 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
532 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
533 brw_pop_insn_state(p
);
537 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
540 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
543 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
545 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
546 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
547 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
548 * channel enable to determine the final channel enable. For the
549 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
550 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
551 * in the writeback message. For the URB_WRITE_OWORD &
552 * URB_WRITE_HWORD messages, when final channel enable is 1 it
553 * indicates that Vertex 1 DATA [3] will be written to the surface.
555 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
556 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
558 * 14 Vertex 1 DATA [2] Channel Mask
559 * 13 Vertex 1 DATA [1] Channel Mask
560 * 12 Vertex 1 DATA [0] Channel Mask
561 * 11 Vertex 0 DATA [3] Channel Mask
562 * 10 Vertex 0 DATA [2] Channel Mask
563 * 9 Vertex 0 DATA [1] Channel Mask
564 * 8 Vertex 0 DATA [0] Channel Mask
566 * (This is from a section of the PRM that is agnostic to the particular
567 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
568 * geometry shader invocations 0 and 1, respectively). Since we have the
569 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
570 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
571 * DWORD 4, we just need to OR them together and store the result in bits
574 * It's easier to get the EU to do this if we think of the src and dst
575 * registers as composed of 32 bytes each; then, we want to pick up the
576 * contents of bytes 0 and 16 from src, OR them together, and store them in
579 * We can do that by the following EU instruction:
581 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
583 * Note: this relies on the source register having zeros in (a) bits 7:4 of
584 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
585 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
586 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
587 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
588 * contain valid channel mask values (which are in the range 0x0-0xf).
590 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
591 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
592 brw_push_insn_state(p
);
593 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
594 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
595 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
596 brw_pop_insn_state(p
);
600 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
602 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
603 * and store into dst.0 & dst.4. So generate the instruction:
605 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
607 brw_push_insn_state(p
);
608 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
609 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
610 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
611 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
612 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
613 brw_pop_insn_state(p
);
617 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
618 struct brw_reg index
)
620 int second_vertex_offset
;
623 second_vertex_offset
= 1;
625 second_vertex_offset
= 16;
627 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
629 /* Set up M1 (message payload). Only the block offsets in M1.0 and
630 * M1.4 are used, and the rest are ignored.
632 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
633 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
634 struct brw_reg index_0
= suboffset(vec1(index
), 0);
635 struct brw_reg index_4
= suboffset(vec1(index
), 4);
637 brw_push_insn_state(p
);
638 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
639 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
641 brw_MOV(p
, m1_0
, index_0
);
643 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
644 index_4
.dw1
.ud
+= second_vertex_offset
;
645 brw_MOV(p
, m1_4
, index_4
);
647 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
650 brw_pop_insn_state(p
);
654 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
657 brw_push_insn_state(p
);
658 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
659 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
661 struct brw_reg flags
= brw_flag_reg(0, 0);
662 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
663 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
665 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
666 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
667 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
669 brw_pop_insn_state(p
);
673 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
675 struct brw_reg index
)
677 struct brw_reg header
= brw_vec8_grf(0, 0);
679 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
681 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
687 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
688 else if (brw
->gen
== 5 || brw
->is_g4x
)
689 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
691 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
693 /* Each of the 8 channel enables is considered for whether each
696 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
697 brw_set_dest(p
, send
, dst
);
698 brw_set_src0(p
, send
, header
);
700 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
701 brw_set_dp_read_message(p
, send
,
702 255, /* binding table index: stateless access */
703 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
705 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
707 true, /* header_present */
712 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
715 struct brw_reg index
)
717 struct brw_reg header
= brw_vec8_grf(0, 0);
720 /* If the instruction is predicated, we'll predicate the send, not
723 brw_set_default_predicate_control(p
, false);
725 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
727 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
731 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
732 retype(src
, BRW_REGISTER_TYPE_D
));
737 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
738 else if (brw
->gen
== 6)
739 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
741 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
743 brw_set_default_predicate_control(p
, inst
->predicate
);
745 /* Pre-gen6, we have to specify write commits to ensure ordering
746 * between reads and writes within a thread. Afterwards, that's
747 * guaranteed and write commits only matter for inter-thread
751 write_commit
= false;
753 /* The visitor set up our destination register to be g0. This
754 * means that when the next read comes along, we will end up
755 * reading from g0 and causing a block on the write commit. For
756 * write-after-read, we are relying on the value of the previous
757 * read being used (and thus blocking on completion) before our
758 * write is executed. This means we have to be careful in
759 * instruction scheduling to not violate this assumption.
764 /* Each of the 8 channel enables is considered for whether each
767 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
768 brw_set_dest(p
, send
, dst
);
769 brw_set_src0(p
, send
, header
);
771 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
772 brw_set_dp_write_message(p
, send
,
773 255, /* binding table index: stateless access */
774 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
777 true, /* header present */
778 false, /* not a render target write */
779 write_commit
, /* rlen */
785 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
787 struct brw_reg index
,
788 struct brw_reg offset
)
790 assert(brw
->gen
<= 7);
791 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
792 index
.type
== BRW_REGISTER_TYPE_UD
);
793 uint32_t surf_index
= index
.dw1
.ud
;
795 struct brw_reg header
= brw_vec8_grf(0, 0);
797 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
799 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
805 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
806 else if (brw
->gen
== 5 || brw
->is_g4x
)
807 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
809 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
811 /* Each of the 8 channel enables is considered for whether each
814 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
815 brw_set_dest(p
, send
, dst
);
816 brw_set_src0(p
, send
, header
);
818 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
819 brw_set_dp_read_message(p
, send
,
821 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
823 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
825 true, /* header_present */
828 brw_mark_surface_used(&prog_data
->base
, surf_index
);
832 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
834 struct brw_reg surf_index
,
835 struct brw_reg offset
)
837 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
838 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
840 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
841 brw_set_dest(p
, insn
, dst
);
842 brw_set_src0(p
, insn
, offset
);
843 brw_set_sampler_message(p
, insn
,
845 0, /* LD message ignores sampler unit */
846 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
849 false, /* no header */
850 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
853 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
857 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
859 struct brw_reg atomic_op
,
860 struct brw_reg surf_index
)
862 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
863 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
864 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
865 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
867 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
868 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
871 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
875 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
877 struct brw_reg surf_index
)
879 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
880 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
882 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
886 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
890 * Generate assembly for a Vec4 IR instruction.
892 * \param instruction The Vec4 IR instruction to generate code for.
893 * \param dst The destination register.
894 * \param src An array of up to three source registers.
897 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
901 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
903 if (dst
.width
== BRW_WIDTH_4
) {
904 /* This happens in attribute fixups for "dual instanced" geometry
905 * shaders, since they use attributes that are vec4's. Since the exec
906 * width is only 4, it's essential that the caller set
907 * force_writemask_all in order to make sure the instruction is executed
908 * regardless of which channels are enabled.
910 assert(inst
->force_writemask_all
);
912 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
913 * the following register region restrictions (from Graphics BSpec:
914 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
915 * > Register Region Restrictions)
917 * 1. ExecSize must be greater than or equal to Width.
919 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
920 * to Width * HorzStride."
922 for (int i
= 0; i
< 3; i
++) {
923 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
924 src
[i
] = stride(src
[i
], 4, 4, 1);
928 switch (inst
->opcode
) {
930 brw_MOV(p
, dst
, src
[0]);
933 brw_ADD(p
, dst
, src
[0], src
[1]);
936 brw_MUL(p
, dst
, src
[0], src
[1]);
938 case BRW_OPCODE_MACH
:
939 brw_MACH(p
, dst
, src
[0], src
[1]);
943 assert(brw
->gen
>= 6);
944 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
948 brw_FRC(p
, dst
, src
[0]);
950 case BRW_OPCODE_RNDD
:
951 brw_RNDD(p
, dst
, src
[0]);
953 case BRW_OPCODE_RNDE
:
954 brw_RNDE(p
, dst
, src
[0]);
956 case BRW_OPCODE_RNDZ
:
957 brw_RNDZ(p
, dst
, src
[0]);
961 brw_AND(p
, dst
, src
[0], src
[1]);
964 brw_OR(p
, dst
, src
[0], src
[1]);
967 brw_XOR(p
, dst
, src
[0], src
[1]);
970 brw_NOT(p
, dst
, src
[0]);
973 brw_ASR(p
, dst
, src
[0], src
[1]);
976 brw_SHR(p
, dst
, src
[0], src
[1]);
979 brw_SHL(p
, dst
, src
[0], src
[1]);
983 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
986 brw_SEL(p
, dst
, src
[0], src
[1]);
990 brw_DPH(p
, dst
, src
[0], src
[1]);
994 brw_DP4(p
, dst
, src
[0], src
[1]);
998 brw_DP3(p
, dst
, src
[0], src
[1]);
1001 case BRW_OPCODE_DP2
:
1002 brw_DP2(p
, dst
, src
[0], src
[1]);
1005 case BRW_OPCODE_F32TO16
:
1006 assert(brw
->gen
>= 7);
1007 brw_F32TO16(p
, dst
, src
[0]);
1010 case BRW_OPCODE_F16TO32
:
1011 assert(brw
->gen
>= 7);
1012 brw_F16TO32(p
, dst
, src
[0]);
1015 case BRW_OPCODE_LRP
:
1016 assert(brw
->gen
>= 6);
1017 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1020 case BRW_OPCODE_BFREV
:
1021 assert(brw
->gen
>= 7);
1022 /* BFREV only supports UD type for src and dst. */
1023 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1024 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1026 case BRW_OPCODE_FBH
:
1027 assert(brw
->gen
>= 7);
1028 /* FBH only supports UD type for dst. */
1029 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1031 case BRW_OPCODE_FBL
:
1032 assert(brw
->gen
>= 7);
1033 /* FBL only supports UD type for dst. */
1034 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1036 case BRW_OPCODE_CBIT
:
1037 assert(brw
->gen
>= 7);
1038 /* CBIT only supports UD type for dst. */
1039 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1041 case BRW_OPCODE_ADDC
:
1042 assert(brw
->gen
>= 7);
1043 brw_ADDC(p
, dst
, src
[0], src
[1]);
1045 case BRW_OPCODE_SUBB
:
1046 assert(brw
->gen
>= 7);
1047 brw_SUBB(p
, dst
, src
[0], src
[1]);
1049 case BRW_OPCODE_MAC
:
1050 brw_MAC(p
, dst
, src
[0], src
[1]);
1053 case BRW_OPCODE_BFE
:
1054 assert(brw
->gen
>= 7);
1055 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1058 case BRW_OPCODE_BFI1
:
1059 assert(brw
->gen
>= 7);
1060 brw_BFI1(p
, dst
, src
[0], src
[1]);
1062 case BRW_OPCODE_BFI2
:
1063 assert(brw
->gen
>= 7);
1064 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1068 if (inst
->src
[0].file
!= BAD_FILE
) {
1069 /* The instruction has an embedded compare (only allowed on gen6) */
1070 assert(brw
->gen
== 6);
1071 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1073 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1074 brw_inst_set_pred_control(brw
, if_inst
, inst
->predicate
);
1078 case BRW_OPCODE_ELSE
:
1081 case BRW_OPCODE_ENDIF
:
1086 brw_DO(p
, BRW_EXECUTE_8
);
1089 case BRW_OPCODE_BREAK
:
1091 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1093 case BRW_OPCODE_CONTINUE
:
1095 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1098 case BRW_OPCODE_WHILE
:
1102 case SHADER_OPCODE_RCP
:
1103 case SHADER_OPCODE_RSQ
:
1104 case SHADER_OPCODE_SQRT
:
1105 case SHADER_OPCODE_EXP2
:
1106 case SHADER_OPCODE_LOG2
:
1107 case SHADER_OPCODE_SIN
:
1108 case SHADER_OPCODE_COS
:
1109 if (brw
->gen
>= 7) {
1110 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1112 } else if (brw
->gen
== 6) {
1113 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1115 generate_math1_gen4(inst
, dst
, src
[0]);
1119 case SHADER_OPCODE_POW
:
1120 case SHADER_OPCODE_INT_QUOTIENT
:
1121 case SHADER_OPCODE_INT_REMAINDER
:
1122 if (brw
->gen
>= 7) {
1123 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1124 } else if (brw
->gen
== 6) {
1125 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1127 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1131 case SHADER_OPCODE_TEX
:
1132 case SHADER_OPCODE_TXD
:
1133 case SHADER_OPCODE_TXF
:
1134 case SHADER_OPCODE_TXF_CMS
:
1135 case SHADER_OPCODE_TXF_MCS
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_TG4
:
1139 case SHADER_OPCODE_TG4_OFFSET
:
1140 generate_tex(inst
, dst
, src
[0], src
[1]);
1143 case VS_OPCODE_URB_WRITE
:
1144 generate_vs_urb_write(inst
);
1147 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1148 generate_scratch_read(inst
, dst
, src
[0]);
1151 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1155 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1156 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1159 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1160 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1163 case GS_OPCODE_URB_WRITE
:
1164 generate_gs_urb_write(inst
);
1167 case GS_OPCODE_THREAD_END
:
1168 generate_gs_thread_end(inst
);
1171 case GS_OPCODE_SET_WRITE_OFFSET
:
1172 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1175 case GS_OPCODE_SET_VERTEX_COUNT
:
1176 generate_gs_set_vertex_count(dst
, src
[0]);
1179 case GS_OPCODE_SET_DWORD_2_IMMED
:
1180 generate_gs_set_dword_2_immed(dst
, src
[0]);
1183 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1184 generate_gs_prepare_channel_masks(dst
);
1187 case GS_OPCODE_SET_CHANNEL_MASKS
:
1188 generate_gs_set_channel_masks(dst
, src
[0]);
1191 case GS_OPCODE_GET_INSTANCE_ID
:
1192 generate_gs_get_instance_id(dst
);
1195 case SHADER_OPCODE_SHADER_TIME_ADD
:
1196 brw_shader_time_add(p
, src
[0],
1197 prog_data
->base
.binding_table
.shader_time_start
);
1198 brw_mark_surface_used(&prog_data
->base
,
1199 prog_data
->base
.binding_table
.shader_time_start
);
1202 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1203 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1206 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1207 generate_untyped_surface_read(inst
, dst
, src
[0]);
1210 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1211 generate_unpack_flags(inst
, dst
);
1215 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1216 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1217 opcode_descs
[inst
->opcode
].name
);
1219 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1226 vec4_generator::generate_code(exec_list
*instructions
)
1228 struct annotation_info annotation
;
1229 memset(&annotation
, 0, sizeof(annotation
));
1232 if (unlikely(debug_flag
))
1233 cfg
= new(mem_ctx
) cfg_t(instructions
);
1235 foreach_in_list(vec4_instruction
, inst
, instructions
) {
1236 struct brw_reg src
[3], dst
;
1238 if (unlikely(debug_flag
))
1239 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1241 for (unsigned int i
= 0; i
< 3; i
++) {
1242 src
[i
] = inst
->get_src(this->prog_data
, i
);
1244 dst
= inst
->get_dst();
1246 brw_set_default_predicate_control(p
, inst
->predicate
);
1247 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1248 brw_set_default_saturate(p
, inst
->saturate
);
1249 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1250 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1252 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1254 generate_vec4_instruction(inst
, dst
, src
);
1256 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1257 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1258 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1259 "emitting more than 1 instruction");
1261 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1263 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1264 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1265 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1270 annotation_finalize(&annotation
, p
->next_insn_offset
);
1272 int before_size
= p
->next_insn_offset
;
1273 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1274 int after_size
= p
->next_insn_offset
;
1276 if (unlikely(debug_flag
)) {
1278 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1279 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1282 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1284 fprintf(stderr
, "vec4 shader: %d instructions. Compacted %d to %d"
1285 " bytes (%.0f%%)\n",
1286 before_size
/ 16, before_size
, after_size
,
1287 100.0f
* (before_size
- after_size
) / before_size
);
1289 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
1290 ralloc_free(annotation
.ann
);
1295 vec4_generator::generate_assembly(exec_list
*instructions
,
1296 unsigned *assembly_size
)
1298 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1299 generate_code(instructions
);
1301 return brw_get_program(p
, assembly_size
);
1304 } /* namespace brw */