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i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 assert(!"not reached");
64 brw_reg = brw_null_reg();
65 break;
66 }
67 return brw_reg;
68 }
69
70 struct brw_reg
71 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
72 {
73 struct brw_reg brw_reg;
74
75 switch (src[i].file) {
76 case GRF:
77 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
78 brw_reg = retype(brw_reg, src[i].type);
79 brw_reg.dw1.bits.swizzle = src[i].swizzle;
80 if (src[i].abs)
81 brw_reg = brw_abs(brw_reg);
82 if (src[i].negate)
83 brw_reg = negate(brw_reg);
84 break;
85
86 case IMM:
87 switch (src[i].type) {
88 case BRW_REGISTER_TYPE_F:
89 brw_reg = brw_imm_f(src[i].imm.f);
90 break;
91 case BRW_REGISTER_TYPE_D:
92 brw_reg = brw_imm_d(src[i].imm.i);
93 break;
94 case BRW_REGISTER_TYPE_UD:
95 brw_reg = brw_imm_ud(src[i].imm.u);
96 break;
97 default:
98 assert(!"not reached");
99 brw_reg = brw_null_reg();
100 break;
101 }
102 break;
103
104 case UNIFORM:
105 brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
106 (src[i].reg + src[i].reg_offset) / 2,
107 ((src[i].reg + src[i].reg_offset) % 2) * 4),
108 0, 4, 1);
109 brw_reg = retype(brw_reg, src[i].type);
110 brw_reg.dw1.bits.swizzle = src[i].swizzle;
111 if (src[i].abs)
112 brw_reg = brw_abs(brw_reg);
113 if (src[i].negate)
114 brw_reg = negate(brw_reg);
115
116 /* This should have been moved to pull constants. */
117 assert(!src[i].reladdr);
118 break;
119
120 case HW_REG:
121 assert(src[i].type == src[i].fixed_hw_reg.type);
122 brw_reg = src[i].fixed_hw_reg;
123 break;
124
125 case BAD_FILE:
126 /* Probably unused. */
127 brw_reg = brw_null_reg();
128 break;
129 case ATTR:
130 default:
131 assert(!"not reached");
132 brw_reg = brw_null_reg();
133 break;
134 }
135
136 return brw_reg;
137 }
138
139 vec4_generator::vec4_generator(struct brw_context *brw,
140 struct gl_shader_program *shader_prog,
141 struct gl_program *prog,
142 struct brw_vec4_prog_data *prog_data,
143 void *mem_ctx,
144 bool debug_flag)
145 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
146 mem_ctx(mem_ctx), debug_flag(debug_flag)
147 {
148 p = rzalloc(mem_ctx, struct brw_compile);
149 brw_init_compile(brw, p, mem_ctx);
150 }
151
152 vec4_generator::~vec4_generator()
153 {
154 }
155
156 void
157 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
158 struct brw_reg dst,
159 struct brw_reg src)
160 {
161 brw_math(p,
162 dst,
163 brw_math_function(inst->opcode),
164 inst->base_mrf,
165 src,
166 BRW_MATH_DATA_VECTOR,
167 BRW_MATH_PRECISION_FULL);
168 }
169
170 static void
171 check_gen6_math_src_arg(struct brw_reg src)
172 {
173 /* Source swizzles are ignored. */
174 assert(!src.abs);
175 assert(!src.negate);
176 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
177 }
178
179 void
180 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
181 struct brw_reg dst,
182 struct brw_reg src)
183 {
184 /* Can't do writemask because math can't be align16. */
185 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
186 check_gen6_math_src_arg(src);
187
188 brw_set_access_mode(p, BRW_ALIGN_1);
189 brw_math(p,
190 dst,
191 brw_math_function(inst->opcode),
192 inst->base_mrf,
193 src,
194 BRW_MATH_DATA_SCALAR,
195 BRW_MATH_PRECISION_FULL);
196 brw_set_access_mode(p, BRW_ALIGN_16);
197 }
198
199 void
200 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
201 struct brw_reg dst,
202 struct brw_reg src0,
203 struct brw_reg src1)
204 {
205 brw_math2(p,
206 dst,
207 brw_math_function(inst->opcode),
208 src0, src1);
209 }
210
211 void
212 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
213 struct brw_reg dst,
214 struct brw_reg src0,
215 struct brw_reg src1)
216 {
217 /* Can't do writemask because math can't be align16. */
218 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
219 /* Source swizzles are ignored. */
220 check_gen6_math_src_arg(src0);
221 check_gen6_math_src_arg(src1);
222
223 brw_set_access_mode(p, BRW_ALIGN_1);
224 brw_math2(p,
225 dst,
226 brw_math_function(inst->opcode),
227 src0, src1);
228 brw_set_access_mode(p, BRW_ALIGN_16);
229 }
230
231 void
232 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
233 struct brw_reg dst,
234 struct brw_reg src0,
235 struct brw_reg src1)
236 {
237 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
238 * "Message Payload":
239 *
240 * "Operand0[7]. For the INT DIV functions, this operand is the
241 * denominator."
242 * ...
243 * "Operand1[7]. For the INT DIV functions, this operand is the
244 * numerator."
245 */
246 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
247 struct brw_reg &op0 = is_int_div ? src1 : src0;
248 struct brw_reg &op1 = is_int_div ? src0 : src1;
249
250 brw_push_insn_state(p);
251 brw_set_saturate(p, false);
252 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
253 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
254 brw_pop_insn_state(p);
255
256 brw_math(p,
257 dst,
258 brw_math_function(inst->opcode),
259 inst->base_mrf,
260 op0,
261 BRW_MATH_DATA_VECTOR,
262 BRW_MATH_PRECISION_FULL);
263 }
264
265 void
266 vec4_generator::generate_tex(vec4_instruction *inst,
267 struct brw_reg dst,
268 struct brw_reg src)
269 {
270 int msg_type = -1;
271
272 if (brw->gen >= 5) {
273 switch (inst->opcode) {
274 case SHADER_OPCODE_TEX:
275 case SHADER_OPCODE_TXL:
276 if (inst->shadow_compare) {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
278 } else {
279 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
280 }
281 break;
282 case SHADER_OPCODE_TXD:
283 if (inst->shadow_compare) {
284 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
285 assert(brw->is_haswell);
286 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
287 } else {
288 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
289 }
290 break;
291 case SHADER_OPCODE_TXF:
292 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
293 break;
294 case SHADER_OPCODE_TXF_CMS:
295 if (brw->gen >= 7)
296 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
297 else
298 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
299 break;
300 case SHADER_OPCODE_TXF_MCS:
301 assert(brw->gen >= 7);
302 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
303 break;
304 case SHADER_OPCODE_TXS:
305 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
306 break;
307 case SHADER_OPCODE_TG4:
308 if (inst->shadow_compare) {
309 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
310 } else {
311 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
312 }
313 break;
314 case SHADER_OPCODE_TG4_OFFSET:
315 if (inst->shadow_compare) {
316 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
317 } else {
318 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
319 }
320 break;
321 default:
322 assert(!"should not get here: invalid vec4 texture opcode");
323 break;
324 }
325 } else {
326 switch (inst->opcode) {
327 case SHADER_OPCODE_TEX:
328 case SHADER_OPCODE_TXL:
329 if (inst->shadow_compare) {
330 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
331 assert(inst->mlen == 3);
332 } else {
333 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
334 assert(inst->mlen == 2);
335 }
336 break;
337 case SHADER_OPCODE_TXD:
338 /* There is no sample_d_c message; comparisons are done manually. */
339 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
340 assert(inst->mlen == 4);
341 break;
342 case SHADER_OPCODE_TXF:
343 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
344 assert(inst->mlen == 2);
345 break;
346 case SHADER_OPCODE_TXS:
347 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
348 assert(inst->mlen == 2);
349 break;
350 default:
351 assert(!"should not get here: invalid vec4 texture opcode");
352 break;
353 }
354 }
355
356 assert(msg_type != -1);
357
358 /* Load the message header if present. If there's a texture offset, we need
359 * to set it up explicitly and load the offset bitfield. Otherwise, we can
360 * use an implied move from g0 to the first message register.
361 */
362 if (inst->header_present) {
363 if (brw->gen < 6 && !inst->texture_offset) {
364 /* Set up an implied move from g0 to the MRF. */
365 src = brw_vec8_grf(0, 0);
366 } else {
367 struct brw_reg header =
368 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
369
370 /* Explicitly set up the message header by copying g0 to the MRF. */
371 brw_push_insn_state(p);
372 brw_set_mask_control(p, BRW_MASK_DISABLE);
373 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
374
375 brw_set_access_mode(p, BRW_ALIGN_1);
376
377 if (inst->texture_offset) {
378 /* Set the texel offset bits in DWord 2. */
379 brw_MOV(p, get_element_ud(header, 2),
380 brw_imm_ud(inst->texture_offset));
381 }
382
383 if (inst->sampler >= 16) {
384 /* The "Sampler Index" field can only store values between 0 and 15.
385 * However, we can add an offset to the "Sampler State Pointer"
386 * field, effectively selecting a different set of 16 samplers.
387 *
388 * The "Sampler State Pointer" needs to be aligned to a 32-byte
389 * offset, and each sampler state is only 16-bytes, so we can't
390 * exclusively use the offset - we have to use both.
391 */
392 assert(brw->is_haswell); /* field only exists on Haswell */
393 brw_ADD(p,
394 get_element_ud(header, 3),
395 get_element_ud(brw_vec8_grf(0, 0), 3),
396 brw_imm_ud(16 * (inst->sampler / 16) *
397 sizeof(gen7_sampler_state)));
398 }
399 brw_pop_insn_state(p);
400 }
401 }
402
403 uint32_t return_format;
404
405 switch (dst.type) {
406 case BRW_REGISTER_TYPE_D:
407 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
408 break;
409 case BRW_REGISTER_TYPE_UD:
410 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
411 break;
412 default:
413 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
414 break;
415 }
416
417 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
418 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
419 ? prog_data->base.binding_table.gather_texture_start
420 : prog_data->base.binding_table.texture_start) + inst->sampler;
421
422 brw_SAMPLE(p,
423 dst,
424 inst->base_mrf,
425 src,
426 surface_index,
427 inst->sampler % 16,
428 msg_type,
429 1, /* response length */
430 inst->mlen,
431 inst->header_present,
432 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
433 return_format);
434
435 brw_mark_surface_used(&prog_data->base, surface_index);
436 }
437
438 void
439 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
440 {
441 brw_urb_WRITE(p,
442 brw_null_reg(), /* dest */
443 inst->base_mrf, /* starting mrf reg nr */
444 brw_vec8_grf(0, 0), /* src */
445 inst->urb_write_flags,
446 inst->mlen,
447 0, /* response len */
448 inst->offset, /* urb destination offset */
449 BRW_URB_SWIZZLE_INTERLEAVE);
450 }
451
452 void
453 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
454 {
455 struct brw_reg src = brw_message_reg(inst->base_mrf);
456 brw_urb_WRITE(p,
457 brw_null_reg(), /* dest */
458 inst->base_mrf, /* starting mrf reg nr */
459 src,
460 inst->urb_write_flags,
461 inst->mlen,
462 0, /* response len */
463 inst->offset, /* urb destination offset */
464 BRW_URB_SWIZZLE_INTERLEAVE);
465 }
466
467 void
468 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
469 {
470 struct brw_reg src = brw_message_reg(inst->base_mrf);
471 brw_urb_WRITE(p,
472 brw_null_reg(), /* dest */
473 inst->base_mrf, /* starting mrf reg nr */
474 src,
475 BRW_URB_WRITE_EOT,
476 1, /* message len */
477 0, /* response len */
478 0, /* urb destination offset */
479 BRW_URB_SWIZZLE_INTERLEAVE);
480 }
481
482 void
483 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
484 struct brw_reg src0,
485 struct brw_reg src1)
486 {
487 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
488 * Header: M0.3):
489 *
490 * Slot 0 Offset. This field, after adding to the Global Offset field
491 * in the message descriptor, specifies the offset (in 256-bit units)
492 * from the start of the URB entry, as referenced by URB Handle 0, at
493 * which the data will be accessed.
494 *
495 * Similar text describes DWORD M0.4, which is slot 1 offset.
496 *
497 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
498 * of the register for geometry shader invocations 0 and 1) by the
499 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
500 *
501 * We can do this with the following EU instruction:
502 *
503 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
504 */
505 brw_push_insn_state(p);
506 brw_set_access_mode(p, BRW_ALIGN_1);
507 brw_set_mask_control(p, BRW_MASK_DISABLE);
508 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
509 src1);
510 brw_set_access_mode(p, BRW_ALIGN_16);
511 brw_pop_insn_state(p);
512 }
513
514 void
515 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
516 struct brw_reg src)
517 {
518 brw_push_insn_state(p);
519 brw_set_access_mode(p, BRW_ALIGN_1);
520 brw_set_mask_control(p, BRW_MASK_DISABLE);
521
522 /* If we think of the src and dst registers as composed of 8 DWORDs each,
523 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
524 * them to WORDs, and then pack them into DWORD 2 of dst.
525 *
526 * It's easier to get the EU to do this if we think of the src and dst
527 * registers as composed of 16 WORDS each; then, we want to pick up the
528 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
529 * dst.
530 *
531 * We can do that by the following EU instruction:
532 *
533 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
534 */
535 brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
536 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
537 brw_set_access_mode(p, BRW_ALIGN_16);
538 brw_pop_insn_state(p);
539 }
540
541 void
542 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
543 struct brw_reg src)
544 {
545 assert(src.file == BRW_IMMEDIATE_VALUE);
546
547 brw_push_insn_state(p);
548 brw_set_access_mode(p, BRW_ALIGN_1);
549 brw_set_mask_control(p, BRW_MASK_DISABLE);
550 brw_MOV(p, suboffset(vec1(dst), 2), src);
551 brw_set_access_mode(p, BRW_ALIGN_16);
552 brw_pop_insn_state(p);
553 }
554
555 void
556 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
557 {
558 /* We want to left shift just DWORD 4 (the x component belonging to the
559 * second geometry shader invocation) by 4 bits. So generate the
560 * instruction:
561 *
562 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
563 */
564 dst = suboffset(vec1(dst), 4);
565 brw_push_insn_state(p);
566 brw_set_access_mode(p, BRW_ALIGN_1);
567 brw_set_mask_control(p, BRW_MASK_DISABLE);
568 brw_SHL(p, dst, dst, brw_imm_ud(4));
569 brw_pop_insn_state(p);
570 }
571
572 void
573 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
574 struct brw_reg src)
575 {
576 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
577 * Header: M0.5):
578 *
579 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
580 *
581 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
582 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
583 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
584 * channel enable to determine the final channel enable. For the
585 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
586 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
587 * in the writeback message. For the URB_WRITE_OWORD &
588 * URB_WRITE_HWORD messages, when final channel enable is 1 it
589 * indicates that Vertex 1 DATA [3] will be written to the surface.
590 *
591 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
592 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
593 *
594 * 14 Vertex 1 DATA [2] Channel Mask
595 * 13 Vertex 1 DATA [1] Channel Mask
596 * 12 Vertex 1 DATA [0] Channel Mask
597 * 11 Vertex 0 DATA [3] Channel Mask
598 * 10 Vertex 0 DATA [2] Channel Mask
599 * 9 Vertex 0 DATA [1] Channel Mask
600 * 8 Vertex 0 DATA [0] Channel Mask
601 *
602 * (This is from a section of the PRM that is agnostic to the particular
603 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
604 * geometry shader invocations 0 and 1, respectively). Since we have the
605 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
606 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
607 * DWORD 4, we just need to OR them together and store the result in bits
608 * 15:8 of DWORD 5.
609 *
610 * It's easier to get the EU to do this if we think of the src and dst
611 * registers as composed of 32 bytes each; then, we want to pick up the
612 * contents of bytes 0 and 16 from src, OR them together, and store them in
613 * byte 21.
614 *
615 * We can do that by the following EU instruction:
616 *
617 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
618 *
619 * Note: this relies on the source register having zeros in (a) bits 7:4 of
620 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
621 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
622 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
623 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
624 * contain valid channel mask values (which are in the range 0x0-0xf).
625 */
626 dst = retype(dst, BRW_REGISTER_TYPE_UB);
627 src = retype(src, BRW_REGISTER_TYPE_UB);
628 brw_push_insn_state(p);
629 brw_set_access_mode(p, BRW_ALIGN_1);
630 brw_set_mask_control(p, BRW_MASK_DISABLE);
631 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
632 brw_pop_insn_state(p);
633 }
634
635 void
636 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
637 {
638 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
639 * and store into dst.0 & dst.4. So generate the instruction:
640 *
641 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
642 */
643 brw_push_insn_state(p);
644 brw_set_access_mode(p, BRW_ALIGN_1);
645 dst = retype(dst, BRW_REGISTER_TYPE_UD);
646 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
647 brw_SHR(p, dst, stride(r0, 1, 4, 0),
648 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
649 brw_pop_insn_state(p);
650 }
651
652 void
653 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
654 struct brw_reg index)
655 {
656 int second_vertex_offset;
657
658 if (brw->gen >= 6)
659 second_vertex_offset = 1;
660 else
661 second_vertex_offset = 16;
662
663 m1 = retype(m1, BRW_REGISTER_TYPE_D);
664
665 /* Set up M1 (message payload). Only the block offsets in M1.0 and
666 * M1.4 are used, and the rest are ignored.
667 */
668 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
669 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
670 struct brw_reg index_0 = suboffset(vec1(index), 0);
671 struct brw_reg index_4 = suboffset(vec1(index), 4);
672
673 brw_push_insn_state(p);
674 brw_set_mask_control(p, BRW_MASK_DISABLE);
675 brw_set_access_mode(p, BRW_ALIGN_1);
676
677 brw_MOV(p, m1_0, index_0);
678
679 if (index.file == BRW_IMMEDIATE_VALUE) {
680 index_4.dw1.ud += second_vertex_offset;
681 brw_MOV(p, m1_4, index_4);
682 } else {
683 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
684 }
685
686 brw_pop_insn_state(p);
687 }
688
689 void
690 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
691 struct brw_reg dst)
692 {
693 brw_push_insn_state(p);
694 brw_set_mask_control(p, BRW_MASK_DISABLE);
695 brw_set_access_mode(p, BRW_ALIGN_1);
696
697 struct brw_reg flags = brw_flag_reg(0, 0);
698 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
699 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
700
701 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
702 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
703 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
704
705 brw_pop_insn_state(p);
706 }
707
708 void
709 vec4_generator::generate_scratch_read(vec4_instruction *inst,
710 struct brw_reg dst,
711 struct brw_reg index)
712 {
713 struct brw_reg header = brw_vec8_grf(0, 0);
714
715 gen6_resolve_implied_move(p, &header, inst->base_mrf);
716
717 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
718 index);
719
720 uint32_t msg_type;
721
722 if (brw->gen >= 6)
723 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
724 else if (brw->gen == 5 || brw->is_g4x)
725 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
726 else
727 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
728
729 /* Each of the 8 channel enables is considered for whether each
730 * dword is written.
731 */
732 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
733 brw_set_dest(p, send, dst);
734 brw_set_src0(p, send, header);
735 if (brw->gen < 6)
736 send->header.destreg__conditionalmod = inst->base_mrf;
737 brw_set_dp_read_message(p, send,
738 255, /* binding table index: stateless access */
739 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
740 msg_type,
741 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
742 2, /* mlen */
743 true, /* header_present */
744 1 /* rlen */);
745 }
746
747 void
748 vec4_generator::generate_scratch_write(vec4_instruction *inst,
749 struct brw_reg dst,
750 struct brw_reg src,
751 struct brw_reg index)
752 {
753 struct brw_reg header = brw_vec8_grf(0, 0);
754 bool write_commit;
755
756 /* If the instruction is predicated, we'll predicate the send, not
757 * the header setup.
758 */
759 brw_set_predicate_control(p, false);
760
761 gen6_resolve_implied_move(p, &header, inst->base_mrf);
762
763 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
764 index);
765
766 brw_MOV(p,
767 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
768 retype(src, BRW_REGISTER_TYPE_D));
769
770 uint32_t msg_type;
771
772 if (brw->gen >= 7)
773 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
774 else if (brw->gen == 6)
775 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
776 else
777 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
778
779 brw_set_predicate_control(p, inst->predicate);
780
781 /* Pre-gen6, we have to specify write commits to ensure ordering
782 * between reads and writes within a thread. Afterwards, that's
783 * guaranteed and write commits only matter for inter-thread
784 * synchronization.
785 */
786 if (brw->gen >= 6) {
787 write_commit = false;
788 } else {
789 /* The visitor set up our destination register to be g0. This
790 * means that when the next read comes along, we will end up
791 * reading from g0 and causing a block on the write commit. For
792 * write-after-read, we are relying on the value of the previous
793 * read being used (and thus blocking on completion) before our
794 * write is executed. This means we have to be careful in
795 * instruction scheduling to not violate this assumption.
796 */
797 write_commit = true;
798 }
799
800 /* Each of the 8 channel enables is considered for whether each
801 * dword is written.
802 */
803 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
804 brw_set_dest(p, send, dst);
805 brw_set_src0(p, send, header);
806 if (brw->gen < 6)
807 send->header.destreg__conditionalmod = inst->base_mrf;
808 brw_set_dp_write_message(p, send,
809 255, /* binding table index: stateless access */
810 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
811 msg_type,
812 3, /* mlen */
813 true, /* header present */
814 false, /* not a render target write */
815 write_commit, /* rlen */
816 false, /* eot */
817 write_commit);
818 }
819
820 void
821 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
822 struct brw_reg dst,
823 struct brw_reg index,
824 struct brw_reg offset)
825 {
826 assert(brw->gen <= 7);
827 assert(index.file == BRW_IMMEDIATE_VALUE &&
828 index.type == BRW_REGISTER_TYPE_UD);
829 uint32_t surf_index = index.dw1.ud;
830
831 struct brw_reg header = brw_vec8_grf(0, 0);
832
833 gen6_resolve_implied_move(p, &header, inst->base_mrf);
834
835 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
836 offset);
837
838 uint32_t msg_type;
839
840 if (brw->gen >= 6)
841 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
842 else if (brw->gen == 5 || brw->is_g4x)
843 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
844 else
845 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
846
847 /* Each of the 8 channel enables is considered for whether each
848 * dword is written.
849 */
850 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
851 brw_set_dest(p, send, dst);
852 brw_set_src0(p, send, header);
853 if (brw->gen < 6)
854 send->header.destreg__conditionalmod = inst->base_mrf;
855 brw_set_dp_read_message(p, send,
856 surf_index,
857 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
858 msg_type,
859 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
860 2, /* mlen */
861 true, /* header_present */
862 1 /* rlen */);
863
864 brw_mark_surface_used(&prog_data->base, surf_index);
865 }
866
867 void
868 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
869 struct brw_reg dst,
870 struct brw_reg surf_index,
871 struct brw_reg offset)
872 {
873 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
874 surf_index.type == BRW_REGISTER_TYPE_UD);
875
876 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
877 brw_set_dest(p, insn, dst);
878 brw_set_src0(p, insn, offset);
879 brw_set_sampler_message(p, insn,
880 surf_index.dw1.ud,
881 0, /* LD message ignores sampler unit */
882 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
883 1, /* rlen */
884 1, /* mlen */
885 false, /* no header */
886 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
887 0);
888
889 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
890 }
891
892 void
893 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
894 struct brw_reg dst,
895 struct brw_reg atomic_op,
896 struct brw_reg surf_index)
897 {
898 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
899 atomic_op.type == BRW_REGISTER_TYPE_UD &&
900 surf_index.file == BRW_IMMEDIATE_VALUE &&
901 surf_index.type == BRW_REGISTER_TYPE_UD);
902
903 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
904 atomic_op.dw1.ud, surf_index.dw1.ud,
905 inst->mlen, 1);
906
907 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
908 }
909
910 void
911 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
912 struct brw_reg dst,
913 struct brw_reg surf_index)
914 {
915 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
916 surf_index.type == BRW_REGISTER_TYPE_UD);
917
918 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
919 surf_index.dw1.ud,
920 inst->mlen, 1);
921
922 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
923 }
924
925 /**
926 * Generate assembly for a Vec4 IR instruction.
927 *
928 * \param instruction The Vec4 IR instruction to generate code for.
929 * \param dst The destination register.
930 * \param src An array of up to three source registers.
931 */
932 void
933 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
934 struct brw_reg dst,
935 struct brw_reg *src)
936 {
937 vec4_instruction *inst = (vec4_instruction *) instruction;
938
939 if (dst.width == BRW_WIDTH_4) {
940 /* This happens in attribute fixups for "dual instanced" geometry
941 * shaders, since they use attributes that are vec4's. Since the exec
942 * width is only 4, it's essential that the caller set
943 * force_writemask_all in order to make sure the instruction is executed
944 * regardless of which channels are enabled.
945 */
946 assert(inst->force_writemask_all);
947
948 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
949 * the following register region restrictions (from Graphics BSpec:
950 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
951 * > Register Region Restrictions)
952 *
953 * 1. ExecSize must be greater than or equal to Width.
954 *
955 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
956 * to Width * HorzStride."
957 */
958 for (int i = 0; i < 3; i++) {
959 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
960 src[i] = stride(src[i], 4, 4, 1);
961 }
962 }
963
964 switch (inst->opcode) {
965 case BRW_OPCODE_MOV:
966 brw_MOV(p, dst, src[0]);
967 break;
968 case BRW_OPCODE_ADD:
969 brw_ADD(p, dst, src[0], src[1]);
970 break;
971 case BRW_OPCODE_MUL:
972 brw_MUL(p, dst, src[0], src[1]);
973 break;
974 case BRW_OPCODE_MACH:
975 brw_MACH(p, dst, src[0], src[1]);
976 break;
977
978 case BRW_OPCODE_MAD:
979 assert(brw->gen >= 6);
980 brw_MAD(p, dst, src[0], src[1], src[2]);
981 break;
982
983 case BRW_OPCODE_FRC:
984 brw_FRC(p, dst, src[0]);
985 break;
986 case BRW_OPCODE_RNDD:
987 brw_RNDD(p, dst, src[0]);
988 break;
989 case BRW_OPCODE_RNDE:
990 brw_RNDE(p, dst, src[0]);
991 break;
992 case BRW_OPCODE_RNDZ:
993 brw_RNDZ(p, dst, src[0]);
994 break;
995
996 case BRW_OPCODE_AND:
997 brw_AND(p, dst, src[0], src[1]);
998 break;
999 case BRW_OPCODE_OR:
1000 brw_OR(p, dst, src[0], src[1]);
1001 break;
1002 case BRW_OPCODE_XOR:
1003 brw_XOR(p, dst, src[0], src[1]);
1004 break;
1005 case BRW_OPCODE_NOT:
1006 brw_NOT(p, dst, src[0]);
1007 break;
1008 case BRW_OPCODE_ASR:
1009 brw_ASR(p, dst, src[0], src[1]);
1010 break;
1011 case BRW_OPCODE_SHR:
1012 brw_SHR(p, dst, src[0], src[1]);
1013 break;
1014 case BRW_OPCODE_SHL:
1015 brw_SHL(p, dst, src[0], src[1]);
1016 break;
1017
1018 case BRW_OPCODE_CMP:
1019 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1020 break;
1021 case BRW_OPCODE_SEL:
1022 brw_SEL(p, dst, src[0], src[1]);
1023 break;
1024
1025 case BRW_OPCODE_DPH:
1026 brw_DPH(p, dst, src[0], src[1]);
1027 break;
1028
1029 case BRW_OPCODE_DP4:
1030 brw_DP4(p, dst, src[0], src[1]);
1031 break;
1032
1033 case BRW_OPCODE_DP3:
1034 brw_DP3(p, dst, src[0], src[1]);
1035 break;
1036
1037 case BRW_OPCODE_DP2:
1038 brw_DP2(p, dst, src[0], src[1]);
1039 break;
1040
1041 case BRW_OPCODE_F32TO16:
1042 assert(brw->gen >= 7);
1043 brw_F32TO16(p, dst, src[0]);
1044 break;
1045
1046 case BRW_OPCODE_F16TO32:
1047 assert(brw->gen >= 7);
1048 brw_F16TO32(p, dst, src[0]);
1049 break;
1050
1051 case BRW_OPCODE_LRP:
1052 assert(brw->gen >= 6);
1053 brw_LRP(p, dst, src[0], src[1], src[2]);
1054 break;
1055
1056 case BRW_OPCODE_BFREV:
1057 assert(brw->gen >= 7);
1058 /* BFREV only supports UD type for src and dst. */
1059 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1060 retype(src[0], BRW_REGISTER_TYPE_UD));
1061 break;
1062 case BRW_OPCODE_FBH:
1063 assert(brw->gen >= 7);
1064 /* FBH only supports UD type for dst. */
1065 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1066 break;
1067 case BRW_OPCODE_FBL:
1068 assert(brw->gen >= 7);
1069 /* FBL only supports UD type for dst. */
1070 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1071 break;
1072 case BRW_OPCODE_CBIT:
1073 assert(brw->gen >= 7);
1074 /* CBIT only supports UD type for dst. */
1075 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1076 break;
1077 case BRW_OPCODE_ADDC:
1078 assert(brw->gen >= 7);
1079 brw_ADDC(p, dst, src[0], src[1]);
1080 break;
1081 case BRW_OPCODE_SUBB:
1082 assert(brw->gen >= 7);
1083 brw_SUBB(p, dst, src[0], src[1]);
1084 break;
1085 case BRW_OPCODE_MAC:
1086 brw_MAC(p, dst, src[0], src[1]);
1087 break;
1088
1089 case BRW_OPCODE_BFE:
1090 assert(brw->gen >= 7);
1091 brw_BFE(p, dst, src[0], src[1], src[2]);
1092 break;
1093
1094 case BRW_OPCODE_BFI1:
1095 assert(brw->gen >= 7);
1096 brw_BFI1(p, dst, src[0], src[1]);
1097 break;
1098 case BRW_OPCODE_BFI2:
1099 assert(brw->gen >= 7);
1100 brw_BFI2(p, dst, src[0], src[1], src[2]);
1101 break;
1102
1103 case BRW_OPCODE_IF:
1104 if (inst->src[0].file != BAD_FILE) {
1105 /* The instruction has an embedded compare (only allowed on gen6) */
1106 assert(brw->gen == 6);
1107 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1108 } else {
1109 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
1110 brw_inst->header.predicate_control = inst->predicate;
1111 }
1112 break;
1113
1114 case BRW_OPCODE_ELSE:
1115 brw_ELSE(p);
1116 break;
1117 case BRW_OPCODE_ENDIF:
1118 brw_ENDIF(p);
1119 break;
1120
1121 case BRW_OPCODE_DO:
1122 brw_DO(p, BRW_EXECUTE_8);
1123 break;
1124
1125 case BRW_OPCODE_BREAK:
1126 brw_BREAK(p);
1127 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1128 break;
1129 case BRW_OPCODE_CONTINUE:
1130 /* FINISHME: We need to write the loop instruction support still. */
1131 if (brw->gen >= 6)
1132 gen6_CONT(p);
1133 else
1134 brw_CONT(p);
1135 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1136 break;
1137
1138 case BRW_OPCODE_WHILE:
1139 brw_WHILE(p);
1140 break;
1141
1142 case SHADER_OPCODE_RCP:
1143 case SHADER_OPCODE_RSQ:
1144 case SHADER_OPCODE_SQRT:
1145 case SHADER_OPCODE_EXP2:
1146 case SHADER_OPCODE_LOG2:
1147 case SHADER_OPCODE_SIN:
1148 case SHADER_OPCODE_COS:
1149 if (brw->gen == 6) {
1150 generate_math1_gen6(inst, dst, src[0]);
1151 } else {
1152 /* Also works for Gen7. */
1153 generate_math1_gen4(inst, dst, src[0]);
1154 }
1155 break;
1156
1157 case SHADER_OPCODE_POW:
1158 case SHADER_OPCODE_INT_QUOTIENT:
1159 case SHADER_OPCODE_INT_REMAINDER:
1160 if (brw->gen >= 7) {
1161 generate_math2_gen7(inst, dst, src[0], src[1]);
1162 } else if (brw->gen == 6) {
1163 generate_math2_gen6(inst, dst, src[0], src[1]);
1164 } else {
1165 generate_math2_gen4(inst, dst, src[0], src[1]);
1166 }
1167 break;
1168
1169 case SHADER_OPCODE_TEX:
1170 case SHADER_OPCODE_TXD:
1171 case SHADER_OPCODE_TXF:
1172 case SHADER_OPCODE_TXF_CMS:
1173 case SHADER_OPCODE_TXF_MCS:
1174 case SHADER_OPCODE_TXL:
1175 case SHADER_OPCODE_TXS:
1176 case SHADER_OPCODE_TG4:
1177 case SHADER_OPCODE_TG4_OFFSET:
1178 generate_tex(inst, dst, src[0]);
1179 break;
1180
1181 case VS_OPCODE_URB_WRITE:
1182 generate_vs_urb_write(inst);
1183 break;
1184
1185 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1186 generate_scratch_read(inst, dst, src[0]);
1187 break;
1188
1189 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1190 generate_scratch_write(inst, dst, src[0], src[1]);
1191 break;
1192
1193 case VS_OPCODE_PULL_CONSTANT_LOAD:
1194 generate_pull_constant_load(inst, dst, src[0], src[1]);
1195 break;
1196
1197 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1198 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1199 break;
1200
1201 case GS_OPCODE_URB_WRITE:
1202 generate_gs_urb_write(inst);
1203 break;
1204
1205 case GS_OPCODE_THREAD_END:
1206 generate_gs_thread_end(inst);
1207 break;
1208
1209 case GS_OPCODE_SET_WRITE_OFFSET:
1210 generate_gs_set_write_offset(dst, src[0], src[1]);
1211 break;
1212
1213 case GS_OPCODE_SET_VERTEX_COUNT:
1214 generate_gs_set_vertex_count(dst, src[0]);
1215 break;
1216
1217 case GS_OPCODE_SET_DWORD_2_IMMED:
1218 generate_gs_set_dword_2_immed(dst, src[0]);
1219 break;
1220
1221 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1222 generate_gs_prepare_channel_masks(dst);
1223 break;
1224
1225 case GS_OPCODE_SET_CHANNEL_MASKS:
1226 generate_gs_set_channel_masks(dst, src[0]);
1227 break;
1228
1229 case GS_OPCODE_GET_INSTANCE_ID:
1230 generate_gs_get_instance_id(dst);
1231 break;
1232
1233 case SHADER_OPCODE_SHADER_TIME_ADD:
1234 brw_shader_time_add(p, src[0],
1235 prog_data->base.binding_table.shader_time_start);
1236 brw_mark_surface_used(&prog_data->base,
1237 prog_data->base.binding_table.shader_time_start);
1238 break;
1239
1240 case SHADER_OPCODE_UNTYPED_ATOMIC:
1241 generate_untyped_atomic(inst, dst, src[0], src[1]);
1242 break;
1243
1244 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1245 generate_untyped_surface_read(inst, dst, src[0]);
1246 break;
1247
1248 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1249 generate_unpack_flags(inst, dst);
1250 break;
1251
1252 default:
1253 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1254 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1255 opcode_descs[inst->opcode].name);
1256 } else {
1257 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1258 }
1259 abort();
1260 }
1261 }
1262
1263 void
1264 vec4_generator::generate_code(exec_list *instructions,
1265 struct annotation_info *annotation)
1266 {
1267 if (unlikely(debug_flag)) {
1268 if (shader_prog) {
1269 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1270 shader_prog->Label ? shader_prog->Label : "unnamed",
1271 shader_prog->Name);
1272 } else {
1273 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1274 }
1275 }
1276
1277 cfg_t *cfg = NULL;
1278 if (unlikely(debug_flag))
1279 cfg = new(mem_ctx) cfg_t(instructions);
1280
1281 foreach_list(node, instructions) {
1282 vec4_instruction *inst = (vec4_instruction *)node;
1283 struct brw_reg src[3], dst;
1284
1285 if (unlikely(debug_flag))
1286 annotate(brw, annotation, cfg, inst, p->next_insn_offset);
1287
1288 for (unsigned int i = 0; i < 3; i++) {
1289 src[i] = inst->get_src(this->prog_data, i);
1290 }
1291 dst = inst->get_dst();
1292
1293 brw_set_predicate_control(p, inst->predicate);
1294 brw_set_predicate_inverse(p, inst->predicate_inverse);
1295 brw_set_saturate(p, inst->saturate);
1296 brw_set_mask_control(p, inst->force_writemask_all);
1297 brw_set_acc_write_control(p, inst->writes_accumulator);
1298
1299 unsigned pre_emit_nr_insn = p->nr_insn;
1300
1301 generate_vec4_instruction(inst, dst, src);
1302
1303 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1304 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1305 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1306 "emitting more than 1 instruction");
1307
1308 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
1309
1310 if (inst->conditional_mod)
1311 last->header.destreg__conditionalmod = inst->conditional_mod;
1312 if (inst->no_dd_clear)
1313 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
1314 if (inst->no_dd_check)
1315 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
1316 }
1317 }
1318
1319 brw_set_uip_jip(p);
1320 annotation_finalize(annotation, p->next_insn_offset);
1321 }
1322
1323 const unsigned *
1324 vec4_generator::generate_assembly(exec_list *instructions,
1325 unsigned *assembly_size)
1326 {
1327 struct annotation_info annotation;
1328 memset(&annotation, 0, sizeof(annotation));
1329
1330 brw_set_access_mode(p, BRW_ALIGN_16);
1331 generate_code(instructions, &annotation);
1332 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1333
1334 if (unlikely(debug_flag)) {
1335 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1336 brw, prog, brw_disassemble);
1337 ralloc_free(annotation.ann);
1338 }
1339
1340 return brw_get_program(p, assembly_size);
1341 }
1342
1343 } /* namespace brw */