1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_program.h"
31 generate_math1_gen4(struct brw_codegen
*p
,
32 vec4_instruction
*inst
,
38 brw_math_function(inst
->opcode
),
41 BRW_MATH_PRECISION_FULL
);
45 check_gen6_math_src_arg(struct brw_reg src
)
47 /* Source swizzles are ignored. */
50 assert(src
.swizzle
== BRW_SWIZZLE_XYZW
);
54 generate_math_gen6(struct brw_codegen
*p
,
55 vec4_instruction
*inst
,
60 /* Can't do writemask because math can't be align16. */
61 assert(dst
.writemask
== WRITEMASK_XYZW
);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0
);
64 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
65 check_gen6_math_src_arg(src1
);
67 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
68 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
69 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
73 generate_math2_gen4(struct brw_codegen
*p
,
74 vec4_instruction
*inst
,
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
82 * "Operand0[7]. For the INT DIV functions, this operand is the
85 * "Operand1[7]. For the INT DIV functions, this operand is the
88 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
89 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
90 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
92 brw_push_insn_state(p
);
93 brw_set_default_saturate(p
, false);
94 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
95 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
96 brw_pop_insn_state(p
);
100 brw_math_function(inst
->opcode
),
103 BRW_MATH_PRECISION_FULL
);
107 generate_tex(struct brw_codegen
*p
,
108 struct brw_vue_prog_data
*prog_data
,
109 vec4_instruction
*inst
,
112 struct brw_reg surface_index
,
113 struct brw_reg sampler_index
)
115 const struct gen_device_info
*devinfo
= p
->devinfo
;
118 if (devinfo
->gen
>= 5) {
119 switch (inst
->opcode
) {
120 case SHADER_OPCODE_TEX
:
121 case SHADER_OPCODE_TXL
:
122 if (inst
->shadow_compare
) {
123 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
125 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
128 case SHADER_OPCODE_TXD
:
129 if (inst
->shadow_compare
) {
130 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
131 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
132 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
134 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
137 case SHADER_OPCODE_TXF
:
138 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
140 case SHADER_OPCODE_TXF_CMS_W
:
141 assert(devinfo
->gen
>= 9);
142 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
144 case SHADER_OPCODE_TXF_CMS
:
145 if (devinfo
->gen
>= 7)
146 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
148 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
150 case SHADER_OPCODE_TXF_MCS
:
151 assert(devinfo
->gen
>= 7);
152 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
154 case SHADER_OPCODE_TXS
:
155 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
157 case SHADER_OPCODE_TG4
:
158 if (inst
->shadow_compare
) {
159 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
161 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
164 case SHADER_OPCODE_TG4_OFFSET
:
165 if (inst
->shadow_compare
) {
166 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
168 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
171 case SHADER_OPCODE_SAMPLEINFO
:
172 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
175 unreachable("should not get here: invalid vec4 texture opcode");
178 switch (inst
->opcode
) {
179 case SHADER_OPCODE_TEX
:
180 case SHADER_OPCODE_TXL
:
181 if (inst
->shadow_compare
) {
182 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
183 assert(inst
->mlen
== 3);
185 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
186 assert(inst
->mlen
== 2);
189 case SHADER_OPCODE_TXD
:
190 /* There is no sample_d_c message; comparisons are done manually. */
191 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
192 assert(inst
->mlen
== 4);
194 case SHADER_OPCODE_TXF
:
195 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
196 assert(inst
->mlen
== 2);
198 case SHADER_OPCODE_TXS
:
199 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
200 assert(inst
->mlen
== 2);
203 unreachable("should not get here: invalid vec4 texture opcode");
207 assert(msg_type
!= -1);
209 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
211 /* Load the message header if present. If there's a texture offset, we need
212 * to set it up explicitly and load the offset bitfield. Otherwise, we can
213 * use an implied move from g0 to the first message register.
215 if (inst
->header_size
!= 0) {
216 if (devinfo
->gen
< 6 && !inst
->offset
) {
217 /* Set up an implied move from g0 to the MRF. */
218 src
= brw_vec8_grf(0, 0);
220 struct brw_reg header
=
221 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
224 /* Explicitly set up the message header by copying g0 to the MRF. */
225 brw_push_insn_state(p
);
226 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
227 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
229 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
232 /* Set the texel offset bits in DWord 2. */
235 if (devinfo
->gen
>= 9)
236 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
237 * based on bit 22 in the header.
239 dw2
|= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
;
242 brw_MOV(p
, get_element_ud(header
, 2), brw_imm_ud(dw2
));
244 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
);
245 brw_pop_insn_state(p
);
249 uint32_t return_format
;
252 case BRW_REGISTER_TYPE_D
:
253 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
255 case BRW_REGISTER_TYPE_UD
:
256 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
259 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
263 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
264 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
265 ? prog_data
->base
.binding_table
.gather_texture_start
266 : prog_data
->base
.binding_table
.texture_start
;
268 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
269 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
270 uint32_t surface
= surface_index
.ud
;
271 uint32_t sampler
= sampler_index
.ud
;
277 surface
+ base_binding_table_index
,
280 1, /* response length */
282 inst
->header_size
!= 0,
283 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
286 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
288 /* Non-constant sampler index. */
290 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
291 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
292 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
294 brw_push_insn_state(p
);
295 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
296 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
298 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
299 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
301 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
302 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
304 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
305 brw_OR(p
, addr
, addr
, surface_reg
);
308 if (base_binding_table_index
)
309 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
310 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
312 brw_pop_insn_state(p
);
314 if (inst
->base_mrf
!= -1)
315 gen6_resolve_implied_move(p
, &src
, inst
->base_mrf
);
317 /* dst = send(offset, a0.0 | <descriptor>) */
318 brw_inst
*insn
= brw_send_indirect_message(
319 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
320 brw_set_sampler_message(p
, insn
,
325 inst
->mlen
/* mlen */,
326 inst
->header_size
!= 0 /* header */,
327 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
330 /* visitor knows more than we do about the surface limit required,
331 * so has already done marking.
337 generate_vs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
340 brw_null_reg(), /* dest */
341 inst
->base_mrf
, /* starting mrf reg nr */
342 brw_vec8_grf(0, 0), /* src */
343 inst
->urb_write_flags
,
345 0, /* response len */
346 inst
->offset
, /* urb destination offset */
347 BRW_URB_SWIZZLE_INTERLEAVE
);
351 generate_gs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
353 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
355 brw_null_reg(), /* dest */
356 inst
->base_mrf
, /* starting mrf reg nr */
358 inst
->urb_write_flags
,
360 0, /* response len */
361 inst
->offset
, /* urb destination offset */
362 BRW_URB_SWIZZLE_INTERLEAVE
);
366 generate_gs_urb_write_allocate(struct brw_codegen
*p
, vec4_instruction
*inst
)
368 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
370 /* We pass the temporary passed in src0 as the writeback register */
372 inst
->src
[0].as_brw_reg(), /* dest */
373 inst
->base_mrf
, /* starting mrf reg nr */
375 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
377 1, /* response len */
378 inst
->offset
, /* urb destination offset */
379 BRW_URB_SWIZZLE_INTERLEAVE
);
381 /* Now put allocated urb handle in dst.0 */
382 brw_push_insn_state(p
);
383 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
384 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
385 brw_MOV(p
, get_element_ud(inst
->dst
.as_brw_reg(), 0),
386 get_element_ud(inst
->src
[0].as_brw_reg(), 0));
387 brw_pop_insn_state(p
);
391 generate_gs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
393 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
395 brw_null_reg(), /* dest */
396 inst
->base_mrf
, /* starting mrf reg nr */
398 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
400 0, /* response len */
401 0, /* urb destination offset */
402 BRW_URB_SWIZZLE_INTERLEAVE
);
406 generate_gs_set_write_offset(struct brw_codegen
*p
,
411 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
414 * Slot 0 Offset. This field, after adding to the Global Offset field
415 * in the message descriptor, specifies the offset (in 256-bit units)
416 * from the start of the URB entry, as referenced by URB Handle 0, at
417 * which the data will be accessed.
419 * Similar text describes DWORD M0.4, which is slot 1 offset.
421 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
422 * of the register for geometry shader invocations 0 and 1) by the
423 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
425 * We can do this with the following EU instruction:
427 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
429 brw_push_insn_state(p
);
430 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
431 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
432 assert(p
->devinfo
->gen
>= 7 &&
433 src1
.file
== BRW_IMMEDIATE_VALUE
&&
434 src1
.type
== BRW_REGISTER_TYPE_UD
&&
435 src1
.ud
<= USHRT_MAX
);
436 if (src0
.file
== BRW_IMMEDIATE_VALUE
) {
437 brw_MOV(p
, suboffset(stride(dst
, 2, 2, 1), 3),
438 brw_imm_ud(src0
.ud
* src1
.ud
));
440 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
441 retype(src1
, BRW_REGISTER_TYPE_UW
));
443 brw_pop_insn_state(p
);
447 generate_gs_set_vertex_count(struct brw_codegen
*p
,
451 brw_push_insn_state(p
);
452 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
454 if (p
->devinfo
->gen
>= 8) {
455 /* Move the vertex count into the second MRF for the EOT write. */
456 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
459 /* If we think of the src and dst registers as composed of 8 DWORDs each,
460 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
461 * them to WORDs, and then pack them into DWORD 2 of dst.
463 * It's easier to get the EU to do this if we think of the src and dst
464 * registers as composed of 16 WORDS each; then, we want to pick up the
465 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
468 * We can do that by the following EU instruction:
470 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
472 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
474 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
475 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
477 brw_pop_insn_state(p
);
481 generate_gs_svb_write(struct brw_codegen
*p
,
482 struct brw_vue_prog_data
*prog_data
,
483 vec4_instruction
*inst
,
488 int binding
= inst
->sol_binding
;
489 bool final_write
= inst
->sol_final_write
;
491 brw_push_insn_state(p
);
492 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
493 /* Copy Vertex data into M0.x */
494 brw_MOV(p
, stride(dst
, 4, 4, 1),
495 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
496 brw_pop_insn_state(p
);
498 brw_push_insn_state(p
);
501 final_write
? src1
: brw_null_reg(), /* dest == src1 */
503 dst
, /* src0 == previous dst */
504 SURF_INDEX_GEN6_SOL_BINDING(binding
), /* binding_table_index */
505 final_write
); /* send_commit_msg */
507 /* Finally, wait for the write commit to occur so that we can proceed to
508 * other things safely.
510 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
512 * The write commit does not modify the destination register, but
513 * merely clears the dependency associated with the destination
514 * register. Thus, a simple “mov” instruction using the register as a
515 * source is sufficient to wait for the write commit to occur.
518 brw_MOV(p
, src1
, src1
);
520 brw_pop_insn_state(p
);
524 generate_gs_svb_set_destination_index(struct brw_codegen
*p
,
525 vec4_instruction
*inst
,
529 int vertex
= inst
->sol_vertex
;
530 brw_push_insn_state(p
);
531 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
532 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
533 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
534 brw_pop_insn_state(p
);
538 generate_gs_set_dword_2(struct brw_codegen
*p
,
542 brw_push_insn_state(p
);
543 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
544 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
545 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
546 brw_pop_insn_state(p
);
550 generate_gs_prepare_channel_masks(struct brw_codegen
*p
,
553 /* We want to left shift just DWORD 4 (the x component belonging to the
554 * second geometry shader invocation) by 4 bits. So generate the
557 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
559 dst
= suboffset(vec1(dst
), 4);
560 brw_push_insn_state(p
);
561 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
562 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
563 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
564 brw_pop_insn_state(p
);
568 generate_gs_set_channel_masks(struct brw_codegen
*p
,
572 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
575 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
577 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
578 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
579 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
580 * channel enable to determine the final channel enable. For the
581 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
582 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
583 * in the writeback message. For the URB_WRITE_OWORD &
584 * URB_WRITE_HWORD messages, when final channel enable is 1 it
585 * indicates that Vertex 1 DATA [3] will be written to the surface.
587 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
588 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
590 * 14 Vertex 1 DATA [2] Channel Mask
591 * 13 Vertex 1 DATA [1] Channel Mask
592 * 12 Vertex 1 DATA [0] Channel Mask
593 * 11 Vertex 0 DATA [3] Channel Mask
594 * 10 Vertex 0 DATA [2] Channel Mask
595 * 9 Vertex 0 DATA [1] Channel Mask
596 * 8 Vertex 0 DATA [0] Channel Mask
598 * (This is from a section of the PRM that is agnostic to the particular
599 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
600 * geometry shader invocations 0 and 1, respectively). Since we have the
601 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
602 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
603 * DWORD 4, we just need to OR them together and store the result in bits
606 * It's easier to get the EU to do this if we think of the src and dst
607 * registers as composed of 32 bytes each; then, we want to pick up the
608 * contents of bytes 0 and 16 from src, OR them together, and store them in
611 * We can do that by the following EU instruction:
613 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
615 * Note: this relies on the source register having zeros in (a) bits 7:4 of
616 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
617 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
618 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
619 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
620 * contain valid channel mask values (which are in the range 0x0-0xf).
622 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
623 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
624 brw_push_insn_state(p
);
625 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
626 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
627 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
628 brw_pop_insn_state(p
);
632 generate_gs_get_instance_id(struct brw_codegen
*p
,
635 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
636 * and store into dst.0 & dst.4. So generate the instruction:
638 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
640 brw_push_insn_state(p
);
641 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
642 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
643 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
644 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
645 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
646 brw_pop_insn_state(p
);
650 generate_gs_ff_sync_set_primitives(struct brw_codegen
*p
,
656 brw_push_insn_state(p
);
657 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
658 /* Save src0 data in 16:31 bits of dst.0 */
659 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
660 brw_imm_ud(0xffffu
));
661 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
662 /* Save src1 data in 0:15 bits of dst.0 */
663 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
664 brw_imm_ud(0xffffu
));
665 brw_OR(p
, suboffset(vec1(dst
), 0),
666 suboffset(vec1(dst
), 0),
667 suboffset(vec1(src2
), 0));
668 brw_pop_insn_state(p
);
672 generate_gs_ff_sync(struct brw_codegen
*p
,
673 vec4_instruction
*inst
,
678 /* This opcode uses an implied MRF register for:
679 * - the header of the ff_sync message. And as such it is expected to be
680 * initialized to r0 before calling here.
681 * - the destination where we will write the allocated URB handle.
683 struct brw_reg header
=
684 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
686 /* Overwrite dword 0 of the header (SO vertices to write) and
687 * dword 1 (number of primitives written).
689 brw_push_insn_state(p
);
690 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
691 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
692 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(src1
, 0));
693 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
694 brw_pop_insn_state(p
);
696 /* Allocate URB handle in dst */
702 1, /* response length */
705 /* Now put allocated urb handle in header.0 */
706 brw_push_insn_state(p
);
707 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
708 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
709 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
711 /* src1 is not an immediate when we use transform feedback */
712 if (src1
.file
!= BRW_IMMEDIATE_VALUE
) {
713 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
714 brw_MOV(p
, brw_vec4_grf(src1
.nr
, 0), brw_vec4_grf(dst
.nr
, 1));
717 brw_pop_insn_state(p
);
721 generate_gs_set_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
723 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
724 struct brw_reg src
= brw_vec8_grf(0, 0);
725 brw_push_insn_state(p
);
726 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
727 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
728 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
729 brw_pop_insn_state(p
);
733 generate_tcs_get_instance_id(struct brw_codegen
*p
, struct brw_reg dst
)
735 const struct gen_device_info
*devinfo
= p
->devinfo
;
736 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
738 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
740 * Since we operate in SIMD4x2 mode, we need run half as many threads
741 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
742 * shift right by one less to accomplish the multiplication by two.
744 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
745 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
747 brw_push_insn_state(p
);
748 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
750 const int mask
= ivb
? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
751 const int shift
= ivb
? 16 : 17;
753 brw_AND(p
, get_element_ud(dst
, 0), get_element_ud(r0
, 2), brw_imm_ud(mask
));
754 brw_SHR(p
, get_element_ud(dst
, 0), get_element_ud(dst
, 0),
755 brw_imm_ud(shift
- 1));
756 brw_ADD(p
, get_element_ud(dst
, 4), get_element_ud(dst
, 0), brw_imm_ud(1));
758 brw_pop_insn_state(p
);
762 generate_tcs_urb_write(struct brw_codegen
*p
,
763 vec4_instruction
*inst
,
764 struct brw_reg urb_header
)
766 const struct gen_device_info
*devinfo
= p
->devinfo
;
768 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
769 brw_set_dest(p
, send
, brw_null_reg());
770 brw_set_src0(p
, send
, urb_header
);
772 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
773 inst
->mlen
/* mlen */, 0 /* rlen */,
774 true /* header */, false /* eot */);
775 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_WRITE_OWORD
);
776 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
777 if (inst
->urb_write_flags
& BRW_URB_WRITE_EOT
) {
778 brw_inst_set_eot(devinfo
, send
, 1);
780 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
781 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
784 /* what happens to swizzles? */
789 generate_tcs_input_urb_offsets(struct brw_codegen
*p
,
791 struct brw_reg vertex
,
792 struct brw_reg offset
)
794 /* Generates an URB read/write message header for HS/DS operation.
795 * Inputs are a vertex index, and a byte offset from the beginning of
798 /* If `vertex` is not an immediate, we clobber a0.0 */
800 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
|| vertex
.file
== BRW_GENERAL_REGISTER_FILE
);
801 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
|| vertex
.type
== BRW_REGISTER_TYPE_D
);
803 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
);
805 brw_push_insn_state(p
);
806 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
807 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
808 brw_MOV(p
, dst
, brw_imm_ud(0));
810 /* m0.5 bits 8-15 are channel enables */
811 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
813 /* m0.0-0.1: URB handles */
814 if (vertex
.file
== BRW_IMMEDIATE_VALUE
) {
815 uint32_t vertex_index
= vertex
.ud
;
816 struct brw_reg index_reg
= brw_vec1_grf(
817 1 + (vertex_index
>> 3), vertex_index
& 7);
819 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
820 retype(index_reg
, BRW_REGISTER_TYPE_UD
));
822 /* Use indirect addressing. ICP Handles are DWords (single channels
823 * of a register) and start at g1.0.
825 * In order to start our region at g1.0, we add 8 to the vertex index,
826 * effectively skipping over the 8 channels in g0.0. This gives us a
827 * DWord offset to the ICP Handle.
829 * Indirect addressing works in terms of bytes, so we then multiply
830 * the DWord offset by 4 (by shifting left by 2).
832 struct brw_reg addr
= brw_address_reg(0);
834 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
835 brw_ADD(p
, addr
, get_element_ud(vertex
, 0), brw_imm_uw(0x8));
836 brw_SHL(p
, addr
, addr
, brw_imm_ud(2));
837 brw_MOV(p
, get_element_ud(dst
, 0), deref_1ud(brw_indirect(0, 0), 0));
839 /* top half: m0.1 = g[1.0 + vertex.4]UD */
840 brw_ADD(p
, addr
, get_element_ud(vertex
, 4), brw_imm_uw(0x8));
841 brw_SHL(p
, addr
, addr
, brw_imm_ud(2));
842 brw_MOV(p
, get_element_ud(dst
, 1), deref_1ud(brw_indirect(0, 0), 0));
845 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
846 if (offset
.file
!= ARF
)
847 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
849 brw_pop_insn_state(p
);
854 generate_tcs_output_urb_offsets(struct brw_codegen
*p
,
856 struct brw_reg write_mask
,
857 struct brw_reg offset
)
859 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
860 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
|| dst
.file
== BRW_MESSAGE_REGISTER_FILE
);
862 assert(write_mask
.file
== BRW_IMMEDIATE_VALUE
);
863 assert(write_mask
.type
== BRW_REGISTER_TYPE_UD
);
865 brw_push_insn_state(p
);
867 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
868 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
869 brw_MOV(p
, dst
, brw_imm_ud(0));
871 unsigned mask
= write_mask
.ud
;
873 /* m0.5 bits 15:12 and 11:8 are channel enables */
874 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud((mask
<< 8) | (mask
<< 12)));
876 /* HS patch URB handle is delivered in r0.0 */
877 struct brw_reg urb_handle
= brw_vec1_grf(0, 0);
879 /* m0.0-0.1: URB handles */
880 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
881 retype(urb_handle
, BRW_REGISTER_TYPE_UD
));
883 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
884 if (offset
.file
!= ARF
)
885 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
887 brw_pop_insn_state(p
);
891 generate_tes_create_input_read_header(struct brw_codegen
*p
,
894 brw_push_insn_state(p
);
895 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
896 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
898 /* Initialize the register to 0 */
899 brw_MOV(p
, dst
, brw_imm_ud(0));
901 /* Enable all the channels in m0.5 bits 15:8 */
902 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
904 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
905 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
907 brw_AND(p
, vec2(get_element_ud(dst
, 0)),
908 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD
),
910 brw_pop_insn_state(p
);
914 generate_tes_add_indirect_urb_offset(struct brw_codegen
*p
,
916 struct brw_reg header
,
917 struct brw_reg offset
)
919 brw_push_insn_state(p
);
920 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
921 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
923 brw_MOV(p
, dst
, header
);
924 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
925 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
927 brw_pop_insn_state(p
);
931 generate_vec4_urb_read(struct brw_codegen
*p
,
932 vec4_instruction
*inst
,
934 struct brw_reg header
)
936 const struct gen_device_info
*devinfo
= p
->devinfo
;
938 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
939 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
941 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
942 brw_set_dest(p
, send
, dst
);
943 brw_set_src0(p
, send
, header
);
945 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
946 1 /* mlen */, 1 /* rlen */,
947 true /* header */, false /* eot */);
948 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
949 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
950 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
952 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
956 generate_tcs_release_input(struct brw_codegen
*p
,
957 struct brw_reg header
,
958 struct brw_reg vertex
,
959 struct brw_reg is_unpaired
)
961 const struct gen_device_info
*devinfo
= p
->devinfo
;
963 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
);
964 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
);
966 /* m0.0-0.1: URB handles */
967 struct brw_reg urb_handles
=
968 retype(brw_vec2_grf(1 + (vertex
.ud
>> 3), vertex
.ud
& 7),
969 BRW_REGISTER_TYPE_UD
);
971 brw_push_insn_state(p
);
972 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
973 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
974 brw_MOV(p
, header
, brw_imm_ud(0));
975 brw_MOV(p
, vec2(get_element_ud(header
, 0)), urb_handles
);
976 brw_pop_insn_state(p
);
978 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
979 brw_set_dest(p
, send
, brw_null_reg());
980 brw_set_src0(p
, send
, header
);
981 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
982 1 /* mlen */, 0 /* rlen */,
983 true /* header */, false /* eot */);
984 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
985 brw_inst_set_urb_complete(devinfo
, send
, 1);
986 brw_inst_set_urb_swizzle_control(devinfo
, send
, is_unpaired
.ud
?
987 BRW_URB_SWIZZLE_NONE
:
988 BRW_URB_SWIZZLE_INTERLEAVE
);
992 generate_tcs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
994 struct brw_reg header
= brw_message_reg(inst
->base_mrf
);
996 brw_push_insn_state(p
);
997 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
998 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
999 brw_MOV(p
, header
, brw_imm_ud(0));
1000 brw_MOV(p
, get_element_ud(header
, 5), brw_imm_ud(WRITEMASK_X
<< 8));
1001 brw_MOV(p
, get_element_ud(header
, 0),
1002 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1003 brw_MOV(p
, brw_message_reg(inst
->base_mrf
+ 1), brw_imm_ud(0u));
1004 brw_pop_insn_state(p
);
1007 brw_null_reg(), /* dest */
1008 inst
->base_mrf
, /* starting mrf reg nr */
1010 BRW_URB_WRITE_EOT
| BRW_URB_WRITE_OWORD
|
1011 BRW_URB_WRITE_USE_CHANNEL_MASKS
,
1013 0, /* response len */
1014 0, /* urb destination offset */
1019 generate_tes_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1021 brw_push_insn_state(p
);
1022 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1023 brw_MOV(p
, dst
, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D
));
1024 brw_pop_insn_state(p
);
1028 generate_tcs_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1030 brw_push_insn_state(p
);
1031 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1032 brw_MOV(p
, dst
, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
1033 brw_pop_insn_state(p
);
1037 generate_tcs_create_barrier_header(struct brw_codegen
*p
,
1038 struct brw_vue_prog_data
*prog_data
,
1041 const struct gen_device_info
*devinfo
= p
->devinfo
;
1042 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
1043 struct brw_reg m0_2
= get_element_ud(dst
, 2);
1044 unsigned instances
= ((struct brw_tcs_prog_data
*) prog_data
)->instances
;
1046 brw_push_insn_state(p
);
1047 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1048 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1050 /* Zero the message header */
1051 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
1053 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1055 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
1056 brw_imm_ud(ivb
? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1058 /* Shift it up to bits 27:24. */
1059 brw_SHL(p
, m0_2
, get_element_ud(dst
, 2), brw_imm_ud(ivb
? 12 : 11));
1061 /* Set the Barrier Count and the enable bit */
1062 brw_OR(p
, m0_2
, m0_2
, brw_imm_ud(instances
<< 9 | (1 << 15)));
1064 brw_pop_insn_state(p
);
1068 generate_oword_dual_block_offsets(struct brw_codegen
*p
,
1070 struct brw_reg index
)
1072 int second_vertex_offset
;
1074 if (p
->devinfo
->gen
>= 6)
1075 second_vertex_offset
= 1;
1077 second_vertex_offset
= 16;
1079 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
1081 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1082 * M1.4 are used, and the rest are ignored.
1084 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
1085 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
1086 struct brw_reg index_0
= suboffset(vec1(index
), 0);
1087 struct brw_reg index_4
= suboffset(vec1(index
), 4);
1089 brw_push_insn_state(p
);
1090 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1091 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1093 brw_MOV(p
, m1_0
, index_0
);
1095 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1096 index_4
.ud
+= second_vertex_offset
;
1097 brw_MOV(p
, m1_4
, index_4
);
1099 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
1102 brw_pop_insn_state(p
);
1106 generate_unpack_flags(struct brw_codegen
*p
,
1109 brw_push_insn_state(p
);
1110 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1111 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1113 struct brw_reg flags
= brw_flag_reg(0, 0);
1114 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
1115 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
1117 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
1118 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
1119 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
1121 brw_pop_insn_state(p
);
1125 generate_scratch_read(struct brw_codegen
*p
,
1126 vec4_instruction
*inst
,
1128 struct brw_reg index
)
1130 const struct gen_device_info
*devinfo
= p
->devinfo
;
1131 struct brw_reg header
= brw_vec8_grf(0, 0);
1133 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1135 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1140 if (devinfo
->gen
>= 6)
1141 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1142 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1143 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1145 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1147 const unsigned target_cache
=
1148 devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1149 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1150 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
1152 /* Each of the 8 channel enables is considered for whether each
1155 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1156 brw_set_dest(p
, send
, dst
);
1157 brw_set_src0(p
, send
, header
);
1158 if (devinfo
->gen
< 6)
1159 brw_inst_set_cond_modifier(devinfo
, send
, inst
->base_mrf
);
1160 brw_set_dp_read_message(p
, send
,
1161 brw_scratch_surface_idx(p
),
1162 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1163 msg_type
, target_cache
,
1165 true, /* header_present */
1170 generate_scratch_write(struct brw_codegen
*p
,
1171 vec4_instruction
*inst
,
1174 struct brw_reg index
)
1176 const struct gen_device_info
*devinfo
= p
->devinfo
;
1177 const unsigned target_cache
=
1178 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1179 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1180 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
1181 struct brw_reg header
= brw_vec8_grf(0, 0);
1184 /* If the instruction is predicated, we'll predicate the send, not
1187 brw_set_default_predicate_control(p
, false);
1189 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1191 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1195 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
1196 retype(src
, BRW_REGISTER_TYPE_D
));
1200 if (devinfo
->gen
>= 7)
1201 msg_type
= GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
;
1202 else if (devinfo
->gen
== 6)
1203 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1205 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1207 brw_set_default_predicate_control(p
, inst
->predicate
);
1209 /* Pre-gen6, we have to specify write commits to ensure ordering
1210 * between reads and writes within a thread. Afterwards, that's
1211 * guaranteed and write commits only matter for inter-thread
1214 if (devinfo
->gen
>= 6) {
1215 write_commit
= false;
1217 /* The visitor set up our destination register to be g0. This
1218 * means that when the next read comes along, we will end up
1219 * reading from g0 and causing a block on the write commit. For
1220 * write-after-read, we are relying on the value of the previous
1221 * read being used (and thus blocking on completion) before our
1222 * write is executed. This means we have to be careful in
1223 * instruction scheduling to not violate this assumption.
1225 write_commit
= true;
1228 /* Each of the 8 channel enables is considered for whether each
1231 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1232 brw_set_dest(p
, send
, dst
);
1233 brw_set_src0(p
, send
, header
);
1234 if (devinfo
->gen
< 6)
1235 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1236 brw_set_dp_write_message(p
, send
,
1237 brw_scratch_surface_idx(p
),
1238 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1242 true, /* header present */
1243 false, /* not a render target write */
1244 write_commit
, /* rlen */
1250 generate_pull_constant_load(struct brw_codegen
*p
,
1251 struct brw_vue_prog_data
*prog_data
,
1252 vec4_instruction
*inst
,
1254 struct brw_reg index
,
1255 struct brw_reg offset
)
1257 const struct gen_device_info
*devinfo
= p
->devinfo
;
1258 const unsigned target_cache
=
1259 (devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE
:
1260 BRW_DATAPORT_READ_TARGET_DATA_CACHE
);
1261 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1262 index
.type
== BRW_REGISTER_TYPE_UD
);
1263 uint32_t surf_index
= index
.ud
;
1265 struct brw_reg header
= brw_vec8_grf(0, 0);
1267 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1269 if (devinfo
->gen
>= 6) {
1270 if (offset
.file
== BRW_IMMEDIATE_VALUE
) {
1271 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1272 BRW_REGISTER_TYPE_D
),
1273 brw_imm_d(offset
.ud
>> 4));
1275 brw_SHR(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1276 BRW_REGISTER_TYPE_D
),
1277 offset
, brw_imm_d(4));
1280 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1281 BRW_REGISTER_TYPE_D
),
1287 if (devinfo
->gen
>= 6)
1288 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1289 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1290 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1292 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1294 /* Each of the 8 channel enables is considered for whether each
1297 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1298 brw_set_dest(p
, send
, dst
);
1299 brw_set_src0(p
, send
, header
);
1300 if (devinfo
->gen
< 6)
1301 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1302 brw_set_dp_read_message(p
, send
,
1304 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1308 true, /* header_present */
1313 generate_get_buffer_size(struct brw_codegen
*p
,
1314 struct brw_vue_prog_data
*prog_data
,
1315 vec4_instruction
*inst
,
1318 struct brw_reg surf_index
)
1320 assert(p
->devinfo
->gen
>= 7);
1321 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
&&
1322 surf_index
.file
== BRW_IMMEDIATE_VALUE
);
1330 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
1331 1, /* response length */
1333 inst
->header_size
> 0,
1334 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1335 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
1337 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1341 generate_pull_constant_load_gen7(struct brw_codegen
*p
,
1342 struct brw_vue_prog_data
*prog_data
,
1343 vec4_instruction
*inst
,
1345 struct brw_reg surf_index
,
1346 struct brw_reg offset
)
1348 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1350 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
1352 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1353 brw_set_dest(p
, insn
, dst
);
1354 brw_set_src0(p
, insn
, offset
);
1355 brw_set_sampler_message(p
, insn
,
1357 0, /* LD message ignores sampler unit */
1358 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1361 inst
->header_size
!= 0,
1362 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1365 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1369 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1371 brw_push_insn_state(p
);
1372 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1373 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1375 /* a0.0 = surf_index & 0xff */
1376 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1377 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1378 brw_set_dest(p
, insn_and
, addr
);
1379 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1380 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1382 brw_pop_insn_state(p
);
1384 /* dst = send(offset, a0.0 | <descriptor>) */
1385 brw_inst
*insn
= brw_send_indirect_message(
1386 p
, BRW_SFID_SAMPLER
, dst
, offset
, addr
);
1387 brw_set_sampler_message(p
, insn
,
1390 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1393 inst
->header_size
!= 0,
1394 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1400 generate_set_simd4x2_header_gen9(struct brw_codegen
*p
,
1401 vec4_instruction
*inst
,
1404 brw_push_insn_state(p
);
1405 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1407 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1408 brw_MOV(p
, vec8(dst
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1410 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1411 brw_MOV(p
, get_element_ud(dst
, 2),
1412 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1414 brw_pop_insn_state(p
);
1418 generate_mov_indirect(struct brw_codegen
*p
,
1419 vec4_instruction
*inst
,
1420 struct brw_reg dst
, struct brw_reg reg
,
1421 struct brw_reg indirect
, struct brw_reg length
)
1423 assert(indirect
.type
== BRW_REGISTER_TYPE_UD
);
1424 assert(p
->devinfo
->gen
>= 6);
1426 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
* (REG_SIZE
/ 2);
1428 /* This instruction acts in align1 mode */
1429 assert(dst
.writemask
== WRITEMASK_XYZW
);
1431 if (indirect
.file
== BRW_IMMEDIATE_VALUE
) {
1432 imm_byte_offset
+= indirect
.ud
;
1434 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
1435 reg
.subnr
= (imm_byte_offset
/ (REG_SIZE
/ 2)) % 2;
1436 unsigned shift
= (imm_byte_offset
/ 4) % 4;
1437 reg
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
1439 brw_MOV(p
, dst
, reg
);
1441 brw_push_insn_state(p
);
1442 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1443 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1445 struct brw_reg addr
= vec8(brw_address_reg(0));
1447 /* We need to move the indirect value into the address register. In
1448 * order to make things make some sense, we want to respect at least the
1449 * X component of the swizzle. In order to do that, we need to convert
1450 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1452 assert(brw_is_single_value_swizzle(indirect
.swizzle
));
1453 indirect
.subnr
= (indirect
.subnr
* 4 + BRW_GET_SWZ(indirect
.swizzle
, 0));
1455 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1456 * the indirect and splat it out to all four channels of the given half
1459 indirect
.subnr
*= 2;
1460 indirect
= stride(retype(indirect
, BRW_REGISTER_TYPE_UW
), 8, 4, 0);
1461 brw_ADD(p
, addr
, indirect
, brw_imm_uw(imm_byte_offset
));
1463 /* Now we need to incorporate the swizzle from the source register */
1464 if (reg
.swizzle
!= BRW_SWIZZLE_XXXX
) {
1465 uint32_t uv_swiz
= BRW_GET_SWZ(reg
.swizzle
, 0) << 2 |
1466 BRW_GET_SWZ(reg
.swizzle
, 1) << 6 |
1467 BRW_GET_SWZ(reg
.swizzle
, 2) << 10 |
1468 BRW_GET_SWZ(reg
.swizzle
, 3) << 14;
1469 uv_swiz
|= uv_swiz
<< 16;
1471 brw_ADD(p
, addr
, addr
, brw_imm_uv(uv_swiz
));
1474 brw_MOV(p
, dst
, retype(brw_VxH_indirect(0, 0), reg
.type
));
1476 brw_pop_insn_state(p
);
1481 generate_code(struct brw_codegen
*p
,
1482 const struct brw_compiler
*compiler
,
1484 const nir_shader
*nir
,
1485 struct brw_vue_prog_data
*prog_data
,
1486 const struct cfg_t
*cfg
)
1488 const struct gen_device_info
*devinfo
= p
->devinfo
;
1489 const char *stage_abbrev
= _mesa_shader_stage_to_abbrev(nir
->stage
);
1490 bool debug_flag
= INTEL_DEBUG
&
1491 intel_debug_flag_for_shader_stage(nir
->stage
);
1492 struct annotation_info annotation
;
1493 memset(&annotation
, 0, sizeof(annotation
));
1494 int spill_count
= 0, fill_count
= 0;
1497 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1498 struct brw_reg src
[3], dst
;
1500 if (unlikely(debug_flag
))
1501 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1503 for (unsigned int i
= 0; i
< 3; i
++) {
1504 src
[i
] = inst
->src
[i
].as_brw_reg();
1506 dst
= inst
->dst
.as_brw_reg();
1508 brw_set_default_predicate_control(p
, inst
->predicate
);
1509 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1510 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1511 brw_set_default_saturate(p
, inst
->saturate
);
1512 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1513 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1515 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1516 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1518 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1520 switch (inst
->opcode
) {
1521 case VEC4_OPCODE_UNPACK_UNIFORM
:
1522 case BRW_OPCODE_MOV
:
1523 brw_MOV(p
, dst
, src
[0]);
1525 case BRW_OPCODE_ADD
:
1526 brw_ADD(p
, dst
, src
[0], src
[1]);
1528 case BRW_OPCODE_MUL
:
1529 brw_MUL(p
, dst
, src
[0], src
[1]);
1531 case BRW_OPCODE_MACH
:
1532 brw_MACH(p
, dst
, src
[0], src
[1]);
1535 case BRW_OPCODE_MAD
:
1536 assert(devinfo
->gen
>= 6);
1537 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1540 case BRW_OPCODE_FRC
:
1541 brw_FRC(p
, dst
, src
[0]);
1543 case BRW_OPCODE_RNDD
:
1544 brw_RNDD(p
, dst
, src
[0]);
1546 case BRW_OPCODE_RNDE
:
1547 brw_RNDE(p
, dst
, src
[0]);
1549 case BRW_OPCODE_RNDZ
:
1550 brw_RNDZ(p
, dst
, src
[0]);
1553 case BRW_OPCODE_AND
:
1554 brw_AND(p
, dst
, src
[0], src
[1]);
1557 brw_OR(p
, dst
, src
[0], src
[1]);
1559 case BRW_OPCODE_XOR
:
1560 brw_XOR(p
, dst
, src
[0], src
[1]);
1562 case BRW_OPCODE_NOT
:
1563 brw_NOT(p
, dst
, src
[0]);
1565 case BRW_OPCODE_ASR
:
1566 brw_ASR(p
, dst
, src
[0], src
[1]);
1568 case BRW_OPCODE_SHR
:
1569 brw_SHR(p
, dst
, src
[0], src
[1]);
1571 case BRW_OPCODE_SHL
:
1572 brw_SHL(p
, dst
, src
[0], src
[1]);
1575 case BRW_OPCODE_CMP
:
1576 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1578 case BRW_OPCODE_SEL
:
1579 brw_SEL(p
, dst
, src
[0], src
[1]);
1582 case BRW_OPCODE_DPH
:
1583 brw_DPH(p
, dst
, src
[0], src
[1]);
1586 case BRW_OPCODE_DP4
:
1587 brw_DP4(p
, dst
, src
[0], src
[1]);
1590 case BRW_OPCODE_DP3
:
1591 brw_DP3(p
, dst
, src
[0], src
[1]);
1594 case BRW_OPCODE_DP2
:
1595 brw_DP2(p
, dst
, src
[0], src
[1]);
1598 case BRW_OPCODE_F32TO16
:
1599 assert(devinfo
->gen
>= 7);
1600 brw_F32TO16(p
, dst
, src
[0]);
1603 case BRW_OPCODE_F16TO32
:
1604 assert(devinfo
->gen
>= 7);
1605 brw_F16TO32(p
, dst
, src
[0]);
1608 case BRW_OPCODE_LRP
:
1609 assert(devinfo
->gen
>= 6);
1610 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1613 case BRW_OPCODE_BFREV
:
1614 assert(devinfo
->gen
>= 7);
1615 /* BFREV only supports UD type for src and dst. */
1616 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1617 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1619 case BRW_OPCODE_FBH
:
1620 assert(devinfo
->gen
>= 7);
1621 /* FBH only supports UD type for dst. */
1622 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1624 case BRW_OPCODE_FBL
:
1625 assert(devinfo
->gen
>= 7);
1626 /* FBL only supports UD type for dst. */
1627 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1629 case BRW_OPCODE_LZD
:
1630 brw_LZD(p
, dst
, src
[0]);
1632 case BRW_OPCODE_CBIT
:
1633 assert(devinfo
->gen
>= 7);
1634 /* CBIT only supports UD type for dst. */
1635 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1637 case BRW_OPCODE_ADDC
:
1638 assert(devinfo
->gen
>= 7);
1639 brw_ADDC(p
, dst
, src
[0], src
[1]);
1641 case BRW_OPCODE_SUBB
:
1642 assert(devinfo
->gen
>= 7);
1643 brw_SUBB(p
, dst
, src
[0], src
[1]);
1645 case BRW_OPCODE_MAC
:
1646 brw_MAC(p
, dst
, src
[0], src
[1]);
1649 case BRW_OPCODE_BFE
:
1650 assert(devinfo
->gen
>= 7);
1651 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1654 case BRW_OPCODE_BFI1
:
1655 assert(devinfo
->gen
>= 7);
1656 brw_BFI1(p
, dst
, src
[0], src
[1]);
1658 case BRW_OPCODE_BFI2
:
1659 assert(devinfo
->gen
>= 7);
1660 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1664 if (!inst
->src
[0].is_null()) {
1665 /* The instruction has an embedded compare (only allowed on gen6) */
1666 assert(devinfo
->gen
== 6);
1667 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1669 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1670 brw_inst_set_pred_control(p
->devinfo
, if_inst
, inst
->predicate
);
1674 case BRW_OPCODE_ELSE
:
1677 case BRW_OPCODE_ENDIF
:
1682 brw_DO(p
, BRW_EXECUTE_8
);
1685 case BRW_OPCODE_BREAK
:
1687 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1689 case BRW_OPCODE_CONTINUE
:
1691 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1694 case BRW_OPCODE_WHILE
:
1699 case SHADER_OPCODE_RCP
:
1700 case SHADER_OPCODE_RSQ
:
1701 case SHADER_OPCODE_SQRT
:
1702 case SHADER_OPCODE_EXP2
:
1703 case SHADER_OPCODE_LOG2
:
1704 case SHADER_OPCODE_SIN
:
1705 case SHADER_OPCODE_COS
:
1706 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1707 if (devinfo
->gen
>= 7) {
1708 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1710 } else if (devinfo
->gen
== 6) {
1711 generate_math_gen6(p
, inst
, dst
, src
[0], brw_null_reg());
1713 generate_math1_gen4(p
, inst
, dst
, src
[0]);
1717 case SHADER_OPCODE_POW
:
1718 case SHADER_OPCODE_INT_QUOTIENT
:
1719 case SHADER_OPCODE_INT_REMAINDER
:
1720 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1721 if (devinfo
->gen
>= 7) {
1722 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1723 } else if (devinfo
->gen
== 6) {
1724 generate_math_gen6(p
, inst
, dst
, src
[0], src
[1]);
1726 generate_math2_gen4(p
, inst
, dst
, src
[0], src
[1]);
1730 case SHADER_OPCODE_TEX
:
1731 case SHADER_OPCODE_TXD
:
1732 case SHADER_OPCODE_TXF
:
1733 case SHADER_OPCODE_TXF_CMS
:
1734 case SHADER_OPCODE_TXF_CMS_W
:
1735 case SHADER_OPCODE_TXF_MCS
:
1736 case SHADER_OPCODE_TXL
:
1737 case SHADER_OPCODE_TXS
:
1738 case SHADER_OPCODE_TG4
:
1739 case SHADER_OPCODE_TG4_OFFSET
:
1740 case SHADER_OPCODE_SAMPLEINFO
:
1741 generate_tex(p
, prog_data
, inst
, dst
, src
[0], src
[1], src
[2]);
1744 case VS_OPCODE_URB_WRITE
:
1745 generate_vs_urb_write(p
, inst
);
1748 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1749 generate_scratch_read(p
, inst
, dst
, src
[0]);
1753 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1754 generate_scratch_write(p
, inst
, dst
, src
[0], src
[1]);
1758 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1759 generate_pull_constant_load(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1762 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1763 generate_pull_constant_load_gen7(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1766 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
1767 generate_set_simd4x2_header_gen9(p
, inst
, dst
);
1771 case VS_OPCODE_GET_BUFFER_SIZE
:
1772 generate_get_buffer_size(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1775 case GS_OPCODE_URB_WRITE
:
1776 generate_gs_urb_write(p
, inst
);
1779 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1780 generate_gs_urb_write_allocate(p
, inst
);
1783 case GS_OPCODE_SVB_WRITE
:
1784 generate_gs_svb_write(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1787 case GS_OPCODE_SVB_SET_DST_INDEX
:
1788 generate_gs_svb_set_destination_index(p
, inst
, dst
, src
[0]);
1791 case GS_OPCODE_THREAD_END
:
1792 generate_gs_thread_end(p
, inst
);
1795 case GS_OPCODE_SET_WRITE_OFFSET
:
1796 generate_gs_set_write_offset(p
, dst
, src
[0], src
[1]);
1799 case GS_OPCODE_SET_VERTEX_COUNT
:
1800 generate_gs_set_vertex_count(p
, dst
, src
[0]);
1803 case GS_OPCODE_FF_SYNC
:
1804 generate_gs_ff_sync(p
, inst
, dst
, src
[0], src
[1]);
1807 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1808 generate_gs_ff_sync_set_primitives(p
, dst
, src
[0], src
[1], src
[2]);
1811 case GS_OPCODE_SET_PRIMITIVE_ID
:
1812 generate_gs_set_primitive_id(p
, dst
);
1815 case GS_OPCODE_SET_DWORD_2
:
1816 generate_gs_set_dword_2(p
, dst
, src
[0]);
1819 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1820 generate_gs_prepare_channel_masks(p
, dst
);
1823 case GS_OPCODE_SET_CHANNEL_MASKS
:
1824 generate_gs_set_channel_masks(p
, dst
, src
[0]);
1827 case GS_OPCODE_GET_INSTANCE_ID
:
1828 generate_gs_get_instance_id(p
, dst
);
1831 case SHADER_OPCODE_SHADER_TIME_ADD
:
1832 brw_shader_time_add(p
, src
[0],
1833 prog_data
->base
.binding_table
.shader_time_start
);
1834 brw_mark_surface_used(&prog_data
->base
,
1835 prog_data
->base
.binding_table
.shader_time_start
);
1838 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1839 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1840 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1841 !inst
->dst
.is_null());
1844 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1845 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1846 brw_untyped_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1850 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1851 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1852 brw_untyped_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1856 case SHADER_OPCODE_TYPED_ATOMIC
:
1857 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1858 brw_typed_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1859 !inst
->dst
.is_null());
1862 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1863 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1864 brw_typed_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1868 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1869 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1870 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1874 case SHADER_OPCODE_MEMORY_FENCE
:
1875 brw_memory_fence(p
, dst
);
1878 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
1879 const struct brw_reg mask
=
1880 brw_stage_has_packed_dispatch(devinfo
, nir
->stage
,
1881 &prog_data
->base
) ? brw_imm_ud(~0u) :
1883 brw_find_live_channel(p
, dst
, mask
);
1887 case SHADER_OPCODE_BROADCAST
:
1888 assert(inst
->force_writemask_all
);
1889 brw_broadcast(p
, dst
, src
[0], src
[1]);
1892 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1893 generate_unpack_flags(p
, dst
);
1896 case VEC4_OPCODE_MOV_BYTES
: {
1897 /* Moves the low byte from each channel, using an Align1 access mode
1898 * and a <4,1,0> source region.
1900 assert(src
[0].type
== BRW_REGISTER_TYPE_UB
||
1901 src
[0].type
== BRW_REGISTER_TYPE_B
);
1903 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1904 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1905 src
[0].width
= BRW_WIDTH_1
;
1906 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1907 brw_MOV(p
, dst
, src
[0]);
1908 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1912 case VEC4_OPCODE_PACK_BYTES
: {
1915 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1917 * but destinations' only regioning is horizontal stride, so instead we
1918 * have to use two instructions:
1920 * mov(4) dst<1>:UB src<4,1,0>:UB
1921 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1923 * where they pack the four bytes from the low and high four DW.
1925 assert(_mesa_is_pow_two(dst
.writemask
) &&
1926 dst
.writemask
!= 0);
1927 unsigned offset
= __builtin_ctz(dst
.writemask
);
1929 dst
.type
= BRW_REGISTER_TYPE_UB
;
1931 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1933 src
[0].type
= BRW_REGISTER_TYPE_UB
;
1934 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1935 src
[0].width
= BRW_WIDTH_1
;
1936 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1937 dst
.subnr
= offset
* 4;
1938 struct brw_inst
*insn
= brw_MOV(p
, dst
, src
[0]);
1939 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1940 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, true);
1941 brw_inst_set_no_dd_check(p
->devinfo
, insn
, inst
->no_dd_check
);
1944 dst
.subnr
= 16 + offset
* 4;
1945 insn
= brw_MOV(p
, dst
, src
[0]);
1946 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1947 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, inst
->no_dd_clear
);
1948 brw_inst_set_no_dd_check(p
->devinfo
, insn
, true);
1950 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1954 case TCS_OPCODE_URB_WRITE
:
1955 generate_tcs_urb_write(p
, inst
, src
[0]);
1958 case VEC4_OPCODE_URB_READ
:
1959 generate_vec4_urb_read(p
, inst
, dst
, src
[0]);
1962 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
1963 generate_tcs_input_urb_offsets(p
, dst
, src
[0], src
[1]);
1966 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
1967 generate_tcs_output_urb_offsets(p
, dst
, src
[0], src
[1]);
1970 case TCS_OPCODE_GET_INSTANCE_ID
:
1971 generate_tcs_get_instance_id(p
, dst
);
1974 case TCS_OPCODE_GET_PRIMITIVE_ID
:
1975 generate_tcs_get_primitive_id(p
, dst
);
1978 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
1979 generate_tcs_create_barrier_header(p
, prog_data
, dst
);
1982 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
1983 generate_tes_create_input_read_header(p
, dst
);
1986 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
1987 generate_tes_add_indirect_urb_offset(p
, dst
, src
[0], src
[1]);
1990 case TES_OPCODE_GET_PRIMITIVE_ID
:
1991 generate_tes_get_primitive_id(p
, dst
);
1994 case TCS_OPCODE_SRC0_010_IS_ZERO
:
1995 /* If src_reg had stride like fs_reg, we wouldn't need this. */
1996 brw_MOV(p
, brw_null_reg(), stride(src
[0], 0, 1, 0));
1999 case TCS_OPCODE_RELEASE_INPUT
:
2000 generate_tcs_release_input(p
, dst
, src
[0], src
[1]);
2003 case TCS_OPCODE_THREAD_END
:
2004 generate_tcs_thread_end(p
, inst
);
2007 case SHADER_OPCODE_BARRIER
:
2008 brw_barrier(p
, src
[0]);
2012 case SHADER_OPCODE_MOV_INDIRECT
:
2013 generate_mov_indirect(p
, inst
, dst
, src
[0], src
[1], src
[2]);
2016 case BRW_OPCODE_DIM
:
2017 assert(devinfo
->is_haswell
);
2018 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2019 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2020 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2024 unreachable("Unsupported opcode");
2027 if (inst
->opcode
== VEC4_OPCODE_PACK_BYTES
) {
2028 /* Handled dependency hints in the generator. */
2030 assert(!inst
->conditional_mod
);
2031 } else if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2032 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
2033 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2034 "emitting more than 1 instruction");
2036 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
2038 if (inst
->conditional_mod
)
2039 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2040 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2041 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2045 brw_set_uip_jip(p
, 0);
2046 annotation_finalize(&annotation
, p
->next_insn_offset
);
2049 bool validated
= brw_validate_instructions(p
, 0, &annotation
);
2051 if (unlikely(debug_flag
))
2052 brw_validate_instructions(p
, 0, &annotation
);
2055 int before_size
= p
->next_insn_offset
;
2056 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
2057 int after_size
= p
->next_insn_offset
;
2059 if (unlikely(debug_flag
)) {
2060 fprintf(stderr
, "Native code for %s %s shader %s:\n",
2061 nir
->info
->label
? nir
->info
->label
: "unnamed",
2062 _mesa_shader_stage_to_string(nir
->stage
), nir
->info
->name
);
2064 fprintf(stderr
, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2065 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2066 stage_abbrev
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2067 spill_count
, fill_count
, before_size
, after_size
,
2068 100.0f
* (before_size
- after_size
) / before_size
);
2070 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2072 ralloc_free(annotation
.mem_ctx
);
2076 compiler
->shader_debug_log(log_data
,
2077 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2078 "%d:%d spills:fills, compacted %d to %d bytes.",
2079 stage_abbrev
, before_size
/ 16,
2080 loop_count
, cfg
->cycle_count
, spill_count
,
2081 fill_count
, before_size
, after_size
);
2085 extern "C" const unsigned *
2086 brw_vec4_generate_assembly(const struct brw_compiler
*compiler
,
2089 const nir_shader
*nir
,
2090 struct brw_vue_prog_data
*prog_data
,
2091 const struct cfg_t
*cfg
,
2092 unsigned *out_assembly_size
)
2094 struct brw_codegen
*p
= rzalloc(mem_ctx
, struct brw_codegen
);
2095 brw_init_codegen(compiler
->devinfo
, p
, mem_ctx
);
2096 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2098 generate_code(p
, compiler
, log_data
, nir
, prog_data
, cfg
);
2100 return brw_get_program(p
, out_assembly_size
);