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i965/vec4: Add vector float immediate infrastructure.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 case BRW_REGISTER_TYPE_VF:
96 brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
97 break;
98 default:
99 unreachable("not reached");
100 }
101 break;
102
103 case UNIFORM:
104 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
105 (src[i].reg + src[i].reg_offset) / 2,
106 ((src[i].reg + src[i].reg_offset) % 2) * 4),
107 0, 4, 1);
108 brw_reg = retype(brw_reg, src[i].type);
109 brw_reg.dw1.bits.swizzle = src[i].swizzle;
110 if (src[i].abs)
111 brw_reg = brw_abs(brw_reg);
112 if (src[i].negate)
113 brw_reg = negate(brw_reg);
114
115 /* This should have been moved to pull constants. */
116 assert(!src[i].reladdr);
117 break;
118
119 case HW_REG:
120 assert(src[i].type == src[i].fixed_hw_reg.type);
121 brw_reg = src[i].fixed_hw_reg;
122 break;
123
124 case BAD_FILE:
125 /* Probably unused. */
126 brw_reg = brw_null_reg();
127 break;
128 case ATTR:
129 default:
130 unreachable("not reached");
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 p = rzalloc(mem_ctx, struct brw_compile);
146 brw_init_compile(brw, p, mem_ctx);
147 }
148
149 vec4_generator::~vec4_generator()
150 {
151 }
152
153 void
154 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
155 struct brw_reg dst,
156 struct brw_reg src)
157 {
158 gen4_math(p,
159 dst,
160 brw_math_function(inst->opcode),
161 inst->base_mrf,
162 src,
163 BRW_MATH_PRECISION_FULL);
164 }
165
166 static void
167 check_gen6_math_src_arg(struct brw_reg src)
168 {
169 /* Source swizzles are ignored. */
170 assert(!src.abs);
171 assert(!src.negate);
172 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
173 }
174
175 void
176 vec4_generator::generate_math_gen6(vec4_instruction *inst,
177 struct brw_reg dst,
178 struct brw_reg src0,
179 struct brw_reg src1)
180 {
181 /* Can't do writemask because math can't be align16. */
182 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
183 /* Source swizzles are ignored. */
184 check_gen6_math_src_arg(src0);
185 if (src1.file == BRW_GENERAL_REGISTER_FILE)
186 check_gen6_math_src_arg(src1);
187
188 brw_set_default_access_mode(p, BRW_ALIGN_1);
189 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
190 brw_set_default_access_mode(p, BRW_ALIGN_16);
191 }
192
193 void
194 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
195 struct brw_reg dst,
196 struct brw_reg src0,
197 struct brw_reg src1)
198 {
199 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Message Payload":
201 *
202 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * denominator."
204 * ...
205 * "Operand1[7]. For the INT DIV functions, this operand is the
206 * numerator."
207 */
208 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
209 struct brw_reg &op0 = is_int_div ? src1 : src0;
210 struct brw_reg &op1 = is_int_div ? src0 : src1;
211
212 brw_push_insn_state(p);
213 brw_set_default_saturate(p, false);
214 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
215 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
216 brw_pop_insn_state(p);
217
218 gen4_math(p,
219 dst,
220 brw_math_function(inst->opcode),
221 inst->base_mrf,
222 op0,
223 BRW_MATH_PRECISION_FULL);
224 }
225
226 void
227 vec4_generator::generate_tex(vec4_instruction *inst,
228 struct brw_reg dst,
229 struct brw_reg src,
230 struct brw_reg sampler_index)
231 {
232 int msg_type = -1;
233
234 if (brw->gen >= 5) {
235 switch (inst->opcode) {
236 case SHADER_OPCODE_TEX:
237 case SHADER_OPCODE_TXL:
238 if (inst->shadow_compare) {
239 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
240 } else {
241 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
242 }
243 break;
244 case SHADER_OPCODE_TXD:
245 if (inst->shadow_compare) {
246 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
247 assert(brw->gen >= 8 || brw->is_haswell);
248 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
249 } else {
250 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
251 }
252 break;
253 case SHADER_OPCODE_TXF:
254 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
255 break;
256 case SHADER_OPCODE_TXF_CMS:
257 if (brw->gen >= 7)
258 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
259 else
260 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
261 break;
262 case SHADER_OPCODE_TXF_MCS:
263 assert(brw->gen >= 7);
264 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
265 break;
266 case SHADER_OPCODE_TXS:
267 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
268 break;
269 case SHADER_OPCODE_TG4:
270 if (inst->shadow_compare) {
271 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
272 } else {
273 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
274 }
275 break;
276 case SHADER_OPCODE_TG4_OFFSET:
277 if (inst->shadow_compare) {
278 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
279 } else {
280 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
281 }
282 break;
283 default:
284 unreachable("should not get here: invalid vec4 texture opcode");
285 }
286 } else {
287 switch (inst->opcode) {
288 case SHADER_OPCODE_TEX:
289 case SHADER_OPCODE_TXL:
290 if (inst->shadow_compare) {
291 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
292 assert(inst->mlen == 3);
293 } else {
294 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
295 assert(inst->mlen == 2);
296 }
297 break;
298 case SHADER_OPCODE_TXD:
299 /* There is no sample_d_c message; comparisons are done manually. */
300 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
301 assert(inst->mlen == 4);
302 break;
303 case SHADER_OPCODE_TXF:
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
305 assert(inst->mlen == 2);
306 break;
307 case SHADER_OPCODE_TXS:
308 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
309 assert(inst->mlen == 2);
310 break;
311 default:
312 unreachable("should not get here: invalid vec4 texture opcode");
313 }
314 }
315
316 assert(msg_type != -1);
317
318 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
319
320 /* Load the message header if present. If there's a texture offset, we need
321 * to set it up explicitly and load the offset bitfield. Otherwise, we can
322 * use an implied move from g0 to the first message register.
323 */
324 if (inst->header_present) {
325 if (brw->gen < 6 && !inst->offset) {
326 /* Set up an implied move from g0 to the MRF. */
327 src = brw_vec8_grf(0, 0);
328 } else {
329 struct brw_reg header =
330 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
331
332 /* Explicitly set up the message header by copying g0 to the MRF. */
333 brw_push_insn_state(p);
334 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
335 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
336
337 brw_set_default_access_mode(p, BRW_ALIGN_1);
338
339 if (inst->offset) {
340 /* Set the texel offset bits in DWord 2. */
341 brw_MOV(p, get_element_ud(header, 2),
342 brw_imm_ud(inst->offset));
343 }
344
345 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
346 brw_pop_insn_state(p);
347 }
348 }
349
350 uint32_t return_format;
351
352 switch (dst.type) {
353 case BRW_REGISTER_TYPE_D:
354 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
355 break;
356 case BRW_REGISTER_TYPE_UD:
357 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
358 break;
359 default:
360 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
361 break;
362 }
363
364 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
365 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
366 ? prog_data->base.binding_table.gather_texture_start
367 : prog_data->base.binding_table.texture_start;
368
369 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
370 uint32_t sampler = sampler_index.dw1.ud;
371
372 brw_SAMPLE(p,
373 dst,
374 inst->base_mrf,
375 src,
376 sampler + base_binding_table_index,
377 sampler % 16,
378 msg_type,
379 1, /* response length */
380 inst->mlen,
381 inst->header_present,
382 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
383 return_format);
384
385 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
386 } else {
387 /* Non-constant sampler index. */
388 /* Note: this clobbers `dst` as a temporary before emitting the send */
389
390 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
391 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
392
393 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
394
395 brw_push_insn_state(p);
396 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
397 brw_set_default_access_mode(p, BRW_ALIGN_1);
398
399 /* Some care required: `sampler` and `temp` may alias:
400 * addr = sampler & 0xff
401 * temp = (sampler << 8) & 0xf00
402 * addr = addr | temp
403 */
404 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
405 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
406 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
407 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
408 brw_OR(p, addr, addr, temp);
409
410 /* a0.0 |= <descriptor> */
411 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
412 brw_set_sampler_message(p, insn_or,
413 0 /* surface */,
414 0 /* sampler */,
415 msg_type,
416 1 /* rlen */,
417 inst->mlen /* mlen */,
418 inst->header_present /* header */,
419 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
420 return_format);
421 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
422 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
423 brw_set_src0(p, insn_or, addr);
424 brw_set_dest(p, insn_or, addr);
425
426
427 /* dst = send(offset, a0.0) */
428 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
429 brw_set_dest(p, insn_send, dst);
430 brw_set_src0(p, insn_send, src);
431 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
432
433 brw_pop_insn_state(p);
434
435 /* visitor knows more than we do about the surface limit required,
436 * so has already done marking.
437 */
438 }
439 }
440
441 void
442 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
443 {
444 brw_urb_WRITE(p,
445 brw_null_reg(), /* dest */
446 inst->base_mrf, /* starting mrf reg nr */
447 brw_vec8_grf(0, 0), /* src */
448 inst->urb_write_flags,
449 inst->mlen,
450 0, /* response len */
451 inst->offset, /* urb destination offset */
452 BRW_URB_SWIZZLE_INTERLEAVE);
453 }
454
455 void
456 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
457 {
458 struct brw_reg src = brw_message_reg(inst->base_mrf);
459 brw_urb_WRITE(p,
460 brw_null_reg(), /* dest */
461 inst->base_mrf, /* starting mrf reg nr */
462 src,
463 inst->urb_write_flags,
464 inst->mlen,
465 0, /* response len */
466 inst->offset, /* urb destination offset */
467 BRW_URB_SWIZZLE_INTERLEAVE);
468 }
469
470 void
471 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
472 {
473 struct brw_reg src = brw_message_reg(inst->base_mrf);
474
475 /* We pass the temporary passed in src0 as the writeback register */
476 brw_urb_WRITE(p,
477 inst->get_src(this->prog_data, 0), /* dest */
478 inst->base_mrf, /* starting mrf reg nr */
479 src,
480 BRW_URB_WRITE_ALLOCATE_COMPLETE,
481 inst->mlen,
482 1, /* response len */
483 inst->offset, /* urb destination offset */
484 BRW_URB_SWIZZLE_INTERLEAVE);
485
486 /* Now put allocated urb handle in dst.0 */
487 brw_push_insn_state(p);
488 brw_set_default_access_mode(p, BRW_ALIGN_1);
489 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
490 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
491 get_element_ud(inst->get_src(this->prog_data, 0), 0));
492 brw_set_default_access_mode(p, BRW_ALIGN_16);
493 brw_pop_insn_state(p);
494 }
495
496 void
497 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
498 {
499 struct brw_reg src = brw_message_reg(inst->base_mrf);
500 brw_urb_WRITE(p,
501 brw_null_reg(), /* dest */
502 inst->base_mrf, /* starting mrf reg nr */
503 src,
504 BRW_URB_WRITE_EOT | inst->urb_write_flags,
505 brw->gen >= 8 ? 2 : 1,/* message len */
506 0, /* response len */
507 0, /* urb destination offset */
508 BRW_URB_SWIZZLE_INTERLEAVE);
509 }
510
511 void
512 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
513 struct brw_reg src0,
514 struct brw_reg src1)
515 {
516 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
517 * Header: M0.3):
518 *
519 * Slot 0 Offset. This field, after adding to the Global Offset field
520 * in the message descriptor, specifies the offset (in 256-bit units)
521 * from the start of the URB entry, as referenced by URB Handle 0, at
522 * which the data will be accessed.
523 *
524 * Similar text describes DWORD M0.4, which is slot 1 offset.
525 *
526 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
527 * of the register for geometry shader invocations 0 and 1) by the
528 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
529 *
530 * We can do this with the following EU instruction:
531 *
532 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
533 */
534 brw_push_insn_state(p);
535 brw_set_default_access_mode(p, BRW_ALIGN_1);
536 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
537 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
538 src1);
539 brw_set_default_access_mode(p, BRW_ALIGN_16);
540 brw_pop_insn_state(p);
541 }
542
543 void
544 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
545 struct brw_reg src)
546 {
547 brw_push_insn_state(p);
548 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
549
550 if (brw->gen >= 8) {
551 /* Move the vertex count into the second MRF for the EOT write. */
552 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
553 src);
554 } else {
555 /* If we think of the src and dst registers as composed of 8 DWORDs each,
556 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
557 * them to WORDs, and then pack them into DWORD 2 of dst.
558 *
559 * It's easier to get the EU to do this if we think of the src and dst
560 * registers as composed of 16 WORDS each; then, we want to pick up the
561 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
562 * of dst.
563 *
564 * We can do that by the following EU instruction:
565 *
566 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
567 */
568 brw_set_default_access_mode(p, BRW_ALIGN_1);
569 brw_MOV(p,
570 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
571 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
572 brw_set_default_access_mode(p, BRW_ALIGN_16);
573 }
574 brw_pop_insn_state(p);
575 }
576
577 void
578 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
579 struct brw_reg dst,
580 struct brw_reg src0,
581 struct brw_reg src1)
582 {
583 int binding = inst->sol_binding;
584 bool final_write = inst->sol_final_write;
585
586 brw_push_insn_state(p);
587 /* Copy Vertex data into M0.x */
588 brw_MOV(p, stride(dst, 4, 4, 1),
589 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
590
591 /* Send SVB Write */
592 brw_svb_write(p,
593 final_write ? src1 : brw_null_reg(), /* dest == src1 */
594 1, /* msg_reg_nr */
595 dst, /* src0 == previous dst */
596 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
597 final_write); /* send_commit_msg */
598
599 /* Finally, wait for the write commit to occur so that we can proceed to
600 * other things safely.
601 *
602 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
603 *
604 * The write commit does not modify the destination register, but
605 * merely clears the dependency associated with the destination
606 * register. Thus, a simple “mov” instruction using the register as a
607 * source is sufficient to wait for the write commit to occur.
608 */
609 if (final_write) {
610 brw_MOV(p, src1, src1);
611 }
612 brw_pop_insn_state(p);
613 }
614
615 void
616 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
617 struct brw_reg dst,
618 struct brw_reg src)
619 {
620
621 int vertex = inst->sol_vertex;
622 brw_push_insn_state(p);
623 brw_set_default_access_mode(p, BRW_ALIGN_1);
624 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
625 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
626 brw_pop_insn_state(p);
627 }
628
629 void
630 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
631 {
632 brw_push_insn_state(p);
633 brw_set_default_access_mode(p, BRW_ALIGN_1);
634 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
635 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
636 brw_pop_insn_state(p);
637 }
638
639 void
640 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
641 {
642 /* We want to left shift just DWORD 4 (the x component belonging to the
643 * second geometry shader invocation) by 4 bits. So generate the
644 * instruction:
645 *
646 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
647 */
648 dst = suboffset(vec1(dst), 4);
649 brw_push_insn_state(p);
650 brw_set_default_access_mode(p, BRW_ALIGN_1);
651 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
652 brw_SHL(p, dst, dst, brw_imm_ud(4));
653 brw_pop_insn_state(p);
654 }
655
656 void
657 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
658 struct brw_reg src)
659 {
660 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
661 * Header: M0.5):
662 *
663 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
664 *
665 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
666 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
667 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
668 * channel enable to determine the final channel enable. For the
669 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
670 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
671 * in the writeback message. For the URB_WRITE_OWORD &
672 * URB_WRITE_HWORD messages, when final channel enable is 1 it
673 * indicates that Vertex 1 DATA [3] will be written to the surface.
674 *
675 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
676 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
677 *
678 * 14 Vertex 1 DATA [2] Channel Mask
679 * 13 Vertex 1 DATA [1] Channel Mask
680 * 12 Vertex 1 DATA [0] Channel Mask
681 * 11 Vertex 0 DATA [3] Channel Mask
682 * 10 Vertex 0 DATA [2] Channel Mask
683 * 9 Vertex 0 DATA [1] Channel Mask
684 * 8 Vertex 0 DATA [0] Channel Mask
685 *
686 * (This is from a section of the PRM that is agnostic to the particular
687 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
688 * geometry shader invocations 0 and 1, respectively). Since we have the
689 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
690 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
691 * DWORD 4, we just need to OR them together and store the result in bits
692 * 15:8 of DWORD 5.
693 *
694 * It's easier to get the EU to do this if we think of the src and dst
695 * registers as composed of 32 bytes each; then, we want to pick up the
696 * contents of bytes 0 and 16 from src, OR them together, and store them in
697 * byte 21.
698 *
699 * We can do that by the following EU instruction:
700 *
701 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
702 *
703 * Note: this relies on the source register having zeros in (a) bits 7:4 of
704 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
705 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
706 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
707 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
708 * contain valid channel mask values (which are in the range 0x0-0xf).
709 */
710 dst = retype(dst, BRW_REGISTER_TYPE_UB);
711 src = retype(src, BRW_REGISTER_TYPE_UB);
712 brw_push_insn_state(p);
713 brw_set_default_access_mode(p, BRW_ALIGN_1);
714 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
715 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
716 brw_pop_insn_state(p);
717 }
718
719 void
720 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
721 {
722 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
723 * and store into dst.0 & dst.4. So generate the instruction:
724 *
725 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
726 */
727 brw_push_insn_state(p);
728 brw_set_default_access_mode(p, BRW_ALIGN_1);
729 dst = retype(dst, BRW_REGISTER_TYPE_UD);
730 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
731 brw_SHR(p, dst, stride(r0, 1, 4, 0),
732 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
733 brw_pop_insn_state(p);
734 }
735
736 void
737 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
738 struct brw_reg src0,
739 struct brw_reg src1,
740 struct brw_reg src2)
741 {
742 brw_push_insn_state(p);
743 brw_set_default_access_mode(p, BRW_ALIGN_1);
744 /* Save src0 data in 16:31 bits of dst.0 */
745 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
746 brw_imm_ud(0xffffu));
747 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
748 /* Save src1 data in 0:15 bits of dst.0 */
749 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
750 brw_imm_ud(0xffffu));
751 brw_OR(p, suboffset(vec1(dst), 0),
752 suboffset(vec1(dst), 0),
753 suboffset(vec1(src2), 0));
754 brw_pop_insn_state(p);
755 }
756
757 void
758 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
759 struct brw_reg dst,
760 struct brw_reg src0,
761 struct brw_reg src1)
762 {
763 /* This opcode uses an implied MRF register for:
764 * - the header of the ff_sync message. And as such it is expected to be
765 * initialized to r0 before calling here.
766 * - the destination where we will write the allocated URB handle.
767 */
768 struct brw_reg header =
769 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
770
771 /* Overwrite dword 0 of the header (SO vertices to write) and
772 * dword 1 (number of primitives written).
773 */
774 brw_push_insn_state(p);
775 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
776 brw_set_default_access_mode(p, BRW_ALIGN_1);
777 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
778 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
779 brw_pop_insn_state(p);
780
781 /* Allocate URB handle in dst */
782 brw_ff_sync(p,
783 dst,
784 0,
785 header,
786 1, /* allocate */
787 1, /* response length */
788 0 /* eot */);
789
790 /* Now put allocated urb handle in header.0 */
791 brw_push_insn_state(p);
792 brw_set_default_access_mode(p, BRW_ALIGN_1);
793 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
794 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
795
796 /* src1 is not an immediate when we use transform feedback */
797 if (src1.file != BRW_IMMEDIATE_VALUE)
798 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
799
800 brw_pop_insn_state(p);
801 }
802
803 void
804 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
805 {
806 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
807 struct brw_reg src = brw_vec8_grf(0, 0);
808 brw_push_insn_state(p);
809 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
810 brw_set_default_access_mode(p, BRW_ALIGN_1);
811 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
812 brw_pop_insn_state(p);
813 }
814
815 void
816 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
817 struct brw_reg index)
818 {
819 int second_vertex_offset;
820
821 if (brw->gen >= 6)
822 second_vertex_offset = 1;
823 else
824 second_vertex_offset = 16;
825
826 m1 = retype(m1, BRW_REGISTER_TYPE_D);
827
828 /* Set up M1 (message payload). Only the block offsets in M1.0 and
829 * M1.4 are used, and the rest are ignored.
830 */
831 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
832 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
833 struct brw_reg index_0 = suboffset(vec1(index), 0);
834 struct brw_reg index_4 = suboffset(vec1(index), 4);
835
836 brw_push_insn_state(p);
837 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
838 brw_set_default_access_mode(p, BRW_ALIGN_1);
839
840 brw_MOV(p, m1_0, index_0);
841
842 if (index.file == BRW_IMMEDIATE_VALUE) {
843 index_4.dw1.ud += second_vertex_offset;
844 brw_MOV(p, m1_4, index_4);
845 } else {
846 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
847 }
848
849 brw_pop_insn_state(p);
850 }
851
852 void
853 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
854 struct brw_reg dst)
855 {
856 brw_push_insn_state(p);
857 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
858 brw_set_default_access_mode(p, BRW_ALIGN_1);
859
860 struct brw_reg flags = brw_flag_reg(0, 0);
861 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
862 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
863
864 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
865 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
866 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
867
868 brw_pop_insn_state(p);
869 }
870
871 void
872 vec4_generator::generate_scratch_read(vec4_instruction *inst,
873 struct brw_reg dst,
874 struct brw_reg index)
875 {
876 struct brw_reg header = brw_vec8_grf(0, 0);
877
878 gen6_resolve_implied_move(p, &header, inst->base_mrf);
879
880 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
881 index);
882
883 uint32_t msg_type;
884
885 if (brw->gen >= 6)
886 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
887 else if (brw->gen == 5 || brw->is_g4x)
888 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
889 else
890 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
891
892 /* Each of the 8 channel enables is considered for whether each
893 * dword is written.
894 */
895 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
896 brw_set_dest(p, send, dst);
897 brw_set_src0(p, send, header);
898 if (brw->gen < 6)
899 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
900 brw_set_dp_read_message(p, send,
901 255, /* binding table index: stateless access */
902 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
903 msg_type,
904 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
905 2, /* mlen */
906 true, /* header_present */
907 1 /* rlen */);
908 }
909
910 void
911 vec4_generator::generate_scratch_write(vec4_instruction *inst,
912 struct brw_reg dst,
913 struct brw_reg src,
914 struct brw_reg index)
915 {
916 struct brw_reg header = brw_vec8_grf(0, 0);
917 bool write_commit;
918
919 /* If the instruction is predicated, we'll predicate the send, not
920 * the header setup.
921 */
922 brw_set_default_predicate_control(p, false);
923
924 gen6_resolve_implied_move(p, &header, inst->base_mrf);
925
926 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
927 index);
928
929 brw_MOV(p,
930 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
931 retype(src, BRW_REGISTER_TYPE_D));
932
933 uint32_t msg_type;
934
935 if (brw->gen >= 7)
936 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
937 else if (brw->gen == 6)
938 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
939 else
940 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
941
942 brw_set_default_predicate_control(p, inst->predicate);
943
944 /* Pre-gen6, we have to specify write commits to ensure ordering
945 * between reads and writes within a thread. Afterwards, that's
946 * guaranteed and write commits only matter for inter-thread
947 * synchronization.
948 */
949 if (brw->gen >= 6) {
950 write_commit = false;
951 } else {
952 /* The visitor set up our destination register to be g0. This
953 * means that when the next read comes along, we will end up
954 * reading from g0 and causing a block on the write commit. For
955 * write-after-read, we are relying on the value of the previous
956 * read being used (and thus blocking on completion) before our
957 * write is executed. This means we have to be careful in
958 * instruction scheduling to not violate this assumption.
959 */
960 write_commit = true;
961 }
962
963 /* Each of the 8 channel enables is considered for whether each
964 * dword is written.
965 */
966 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
967 brw_set_dest(p, send, dst);
968 brw_set_src0(p, send, header);
969 if (brw->gen < 6)
970 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
971 brw_set_dp_write_message(p, send,
972 255, /* binding table index: stateless access */
973 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
974 msg_type,
975 3, /* mlen */
976 true, /* header present */
977 false, /* not a render target write */
978 write_commit, /* rlen */
979 false, /* eot */
980 write_commit);
981 }
982
983 void
984 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
985 struct brw_reg dst,
986 struct brw_reg index,
987 struct brw_reg offset)
988 {
989 assert(index.file == BRW_IMMEDIATE_VALUE &&
990 index.type == BRW_REGISTER_TYPE_UD);
991 uint32_t surf_index = index.dw1.ud;
992
993 struct brw_reg header = brw_vec8_grf(0, 0);
994
995 gen6_resolve_implied_move(p, &header, inst->base_mrf);
996
997 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
998 offset);
999
1000 uint32_t msg_type;
1001
1002 if (brw->gen >= 6)
1003 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1004 else if (brw->gen == 5 || brw->is_g4x)
1005 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1006 else
1007 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1008
1009 /* Each of the 8 channel enables is considered for whether each
1010 * dword is written.
1011 */
1012 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1013 brw_set_dest(p, send, dst);
1014 brw_set_src0(p, send, header);
1015 if (brw->gen < 6)
1016 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
1017 brw_set_dp_read_message(p, send,
1018 surf_index,
1019 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1020 msg_type,
1021 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1022 2, /* mlen */
1023 true, /* header_present */
1024 1 /* rlen */);
1025
1026 brw_mark_surface_used(&prog_data->base, surf_index);
1027 }
1028
1029 void
1030 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1031 struct brw_reg dst,
1032 struct brw_reg surf_index,
1033 struct brw_reg offset)
1034 {
1035 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1036
1037 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1038
1039 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1040 brw_set_dest(p, insn, dst);
1041 brw_set_src0(p, insn, offset);
1042 brw_set_sampler_message(p, insn,
1043 surf_index.dw1.ud,
1044 0, /* LD message ignores sampler unit */
1045 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1046 1, /* rlen */
1047 1, /* mlen */
1048 false, /* no header */
1049 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1050 0);
1051
1052 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1053
1054 } else {
1055
1056 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1057
1058 brw_push_insn_state(p);
1059 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1060 brw_set_default_access_mode(p, BRW_ALIGN_1);
1061
1062 /* a0.0 = surf_index & 0xff */
1063 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1064 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1065 brw_set_dest(p, insn_and, addr);
1066 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1067 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1068
1069
1070 /* a0.0 |= <descriptor> */
1071 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1072 brw_set_sampler_message(p, insn_or,
1073 0 /* surface */,
1074 0 /* sampler */,
1075 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1076 1 /* rlen */,
1077 1 /* mlen */,
1078 false /* header */,
1079 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1080 0);
1081 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1082 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1083 brw_set_src0(p, insn_or, addr);
1084 brw_set_dest(p, insn_or, addr);
1085
1086
1087 /* dst = send(offset, a0.0) */
1088 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1089 brw_set_dest(p, insn_send, dst);
1090 brw_set_src0(p, insn_send, offset);
1091 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1092
1093 brw_pop_insn_state(p);
1094
1095 /* visitor knows more than we do about the surface limit required,
1096 * so has already done marking.
1097 */
1098 }
1099 }
1100
1101 void
1102 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1103 struct brw_reg dst,
1104 struct brw_reg atomic_op,
1105 struct brw_reg surf_index)
1106 {
1107 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1108 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1109 surf_index.file == BRW_IMMEDIATE_VALUE &&
1110 surf_index.type == BRW_REGISTER_TYPE_UD);
1111
1112 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1113 atomic_op.dw1.ud, surf_index.dw1.ud,
1114 inst->mlen, 1);
1115
1116 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1117 }
1118
1119 void
1120 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1121 struct brw_reg dst,
1122 struct brw_reg surf_index)
1123 {
1124 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1125 surf_index.type == BRW_REGISTER_TYPE_UD);
1126
1127 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1128 surf_index.dw1.ud,
1129 inst->mlen, 1);
1130
1131 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1132 }
1133
1134 void
1135 vec4_generator::generate_code(const cfg_t *cfg)
1136 {
1137 struct annotation_info annotation;
1138 memset(&annotation, 0, sizeof(annotation));
1139 int loop_count = 0;
1140
1141 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1142 struct brw_reg src[3], dst;
1143
1144 if (unlikely(debug_flag))
1145 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1146
1147 for (unsigned int i = 0; i < 3; i++) {
1148 src[i] = inst->get_src(this->prog_data, i);
1149 }
1150 dst = inst->get_dst();
1151
1152 brw_set_default_predicate_control(p, inst->predicate);
1153 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1154 brw_set_default_saturate(p, inst->saturate);
1155 brw_set_default_mask_control(p, inst->force_writemask_all);
1156 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1157
1158 unsigned pre_emit_nr_insn = p->nr_insn;
1159
1160 if (dst.width == BRW_WIDTH_4) {
1161 /* This happens in attribute fixups for "dual instanced" geometry
1162 * shaders, since they use attributes that are vec4's. Since the exec
1163 * width is only 4, it's essential that the caller set
1164 * force_writemask_all in order to make sure the instruction is executed
1165 * regardless of which channels are enabled.
1166 */
1167 assert(inst->force_writemask_all);
1168
1169 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1170 * the following register region restrictions (from Graphics BSpec:
1171 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1172 * > Register Region Restrictions)
1173 *
1174 * 1. ExecSize must be greater than or equal to Width.
1175 *
1176 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1177 * to Width * HorzStride."
1178 */
1179 for (int i = 0; i < 3; i++) {
1180 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1181 src[i] = stride(src[i], 4, 4, 1);
1182 }
1183 }
1184
1185 switch (inst->opcode) {
1186 case BRW_OPCODE_MOV:
1187 brw_MOV(p, dst, src[0]);
1188 break;
1189 case BRW_OPCODE_ADD:
1190 brw_ADD(p, dst, src[0], src[1]);
1191 break;
1192 case BRW_OPCODE_MUL:
1193 brw_MUL(p, dst, src[0], src[1]);
1194 break;
1195 case BRW_OPCODE_MACH:
1196 brw_MACH(p, dst, src[0], src[1]);
1197 break;
1198
1199 case BRW_OPCODE_MAD:
1200 assert(brw->gen >= 6);
1201 brw_MAD(p, dst, src[0], src[1], src[2]);
1202 break;
1203
1204 case BRW_OPCODE_FRC:
1205 brw_FRC(p, dst, src[0]);
1206 break;
1207 case BRW_OPCODE_RNDD:
1208 brw_RNDD(p, dst, src[0]);
1209 break;
1210 case BRW_OPCODE_RNDE:
1211 brw_RNDE(p, dst, src[0]);
1212 break;
1213 case BRW_OPCODE_RNDZ:
1214 brw_RNDZ(p, dst, src[0]);
1215 break;
1216
1217 case BRW_OPCODE_AND:
1218 brw_AND(p, dst, src[0], src[1]);
1219 break;
1220 case BRW_OPCODE_OR:
1221 brw_OR(p, dst, src[0], src[1]);
1222 break;
1223 case BRW_OPCODE_XOR:
1224 brw_XOR(p, dst, src[0], src[1]);
1225 break;
1226 case BRW_OPCODE_NOT:
1227 brw_NOT(p, dst, src[0]);
1228 break;
1229 case BRW_OPCODE_ASR:
1230 brw_ASR(p, dst, src[0], src[1]);
1231 break;
1232 case BRW_OPCODE_SHR:
1233 brw_SHR(p, dst, src[0], src[1]);
1234 break;
1235 case BRW_OPCODE_SHL:
1236 brw_SHL(p, dst, src[0], src[1]);
1237 break;
1238
1239 case BRW_OPCODE_CMP:
1240 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1241 break;
1242 case BRW_OPCODE_SEL:
1243 brw_SEL(p, dst, src[0], src[1]);
1244 break;
1245
1246 case BRW_OPCODE_DPH:
1247 brw_DPH(p, dst, src[0], src[1]);
1248 break;
1249
1250 case BRW_OPCODE_DP4:
1251 brw_DP4(p, dst, src[0], src[1]);
1252 break;
1253
1254 case BRW_OPCODE_DP3:
1255 brw_DP3(p, dst, src[0], src[1]);
1256 break;
1257
1258 case BRW_OPCODE_DP2:
1259 brw_DP2(p, dst, src[0], src[1]);
1260 break;
1261
1262 case BRW_OPCODE_F32TO16:
1263 assert(brw->gen >= 7);
1264 brw_F32TO16(p, dst, src[0]);
1265 break;
1266
1267 case BRW_OPCODE_F16TO32:
1268 assert(brw->gen >= 7);
1269 brw_F16TO32(p, dst, src[0]);
1270 break;
1271
1272 case BRW_OPCODE_LRP:
1273 assert(brw->gen >= 6);
1274 brw_LRP(p, dst, src[0], src[1], src[2]);
1275 break;
1276
1277 case BRW_OPCODE_BFREV:
1278 assert(brw->gen >= 7);
1279 /* BFREV only supports UD type for src and dst. */
1280 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1281 retype(src[0], BRW_REGISTER_TYPE_UD));
1282 break;
1283 case BRW_OPCODE_FBH:
1284 assert(brw->gen >= 7);
1285 /* FBH only supports UD type for dst. */
1286 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1287 break;
1288 case BRW_OPCODE_FBL:
1289 assert(brw->gen >= 7);
1290 /* FBL only supports UD type for dst. */
1291 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1292 break;
1293 case BRW_OPCODE_CBIT:
1294 assert(brw->gen >= 7);
1295 /* CBIT only supports UD type for dst. */
1296 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1297 break;
1298 case BRW_OPCODE_ADDC:
1299 assert(brw->gen >= 7);
1300 brw_ADDC(p, dst, src[0], src[1]);
1301 break;
1302 case BRW_OPCODE_SUBB:
1303 assert(brw->gen >= 7);
1304 brw_SUBB(p, dst, src[0], src[1]);
1305 break;
1306 case BRW_OPCODE_MAC:
1307 brw_MAC(p, dst, src[0], src[1]);
1308 break;
1309
1310 case BRW_OPCODE_BFE:
1311 assert(brw->gen >= 7);
1312 brw_BFE(p, dst, src[0], src[1], src[2]);
1313 break;
1314
1315 case BRW_OPCODE_BFI1:
1316 assert(brw->gen >= 7);
1317 brw_BFI1(p, dst, src[0], src[1]);
1318 break;
1319 case BRW_OPCODE_BFI2:
1320 assert(brw->gen >= 7);
1321 brw_BFI2(p, dst, src[0], src[1], src[2]);
1322 break;
1323
1324 case BRW_OPCODE_IF:
1325 if (inst->src[0].file != BAD_FILE) {
1326 /* The instruction has an embedded compare (only allowed on gen6) */
1327 assert(brw->gen == 6);
1328 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1329 } else {
1330 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1331 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1332 }
1333 break;
1334
1335 case BRW_OPCODE_ELSE:
1336 brw_ELSE(p);
1337 break;
1338 case BRW_OPCODE_ENDIF:
1339 brw_ENDIF(p);
1340 break;
1341
1342 case BRW_OPCODE_DO:
1343 brw_DO(p, BRW_EXECUTE_8);
1344 break;
1345
1346 case BRW_OPCODE_BREAK:
1347 brw_BREAK(p);
1348 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1349 break;
1350 case BRW_OPCODE_CONTINUE:
1351 brw_CONT(p);
1352 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1353 break;
1354
1355 case BRW_OPCODE_WHILE:
1356 brw_WHILE(p);
1357 loop_count++;
1358 break;
1359
1360 case SHADER_OPCODE_RCP:
1361 case SHADER_OPCODE_RSQ:
1362 case SHADER_OPCODE_SQRT:
1363 case SHADER_OPCODE_EXP2:
1364 case SHADER_OPCODE_LOG2:
1365 case SHADER_OPCODE_SIN:
1366 case SHADER_OPCODE_COS:
1367 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1368 if (brw->gen >= 7) {
1369 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1370 brw_null_reg());
1371 } else if (brw->gen == 6) {
1372 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1373 } else {
1374 generate_math1_gen4(inst, dst, src[0]);
1375 }
1376 break;
1377
1378 case SHADER_OPCODE_POW:
1379 case SHADER_OPCODE_INT_QUOTIENT:
1380 case SHADER_OPCODE_INT_REMAINDER:
1381 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1382 if (brw->gen >= 7) {
1383 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1384 } else if (brw->gen == 6) {
1385 generate_math_gen6(inst, dst, src[0], src[1]);
1386 } else {
1387 generate_math2_gen4(inst, dst, src[0], src[1]);
1388 }
1389 break;
1390
1391 case SHADER_OPCODE_TEX:
1392 case SHADER_OPCODE_TXD:
1393 case SHADER_OPCODE_TXF:
1394 case SHADER_OPCODE_TXF_CMS:
1395 case SHADER_OPCODE_TXF_MCS:
1396 case SHADER_OPCODE_TXL:
1397 case SHADER_OPCODE_TXS:
1398 case SHADER_OPCODE_TG4:
1399 case SHADER_OPCODE_TG4_OFFSET:
1400 generate_tex(inst, dst, src[0], src[1]);
1401 break;
1402
1403 case VS_OPCODE_URB_WRITE:
1404 generate_vs_urb_write(inst);
1405 break;
1406
1407 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1408 generate_scratch_read(inst, dst, src[0]);
1409 break;
1410
1411 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1412 generate_scratch_write(inst, dst, src[0], src[1]);
1413 break;
1414
1415 case VS_OPCODE_PULL_CONSTANT_LOAD:
1416 generate_pull_constant_load(inst, dst, src[0], src[1]);
1417 break;
1418
1419 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1420 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1421 break;
1422
1423 case GS_OPCODE_URB_WRITE:
1424 generate_gs_urb_write(inst);
1425 break;
1426
1427 case GS_OPCODE_URB_WRITE_ALLOCATE:
1428 generate_gs_urb_write_allocate(inst);
1429 break;
1430
1431 case GS_OPCODE_SVB_WRITE:
1432 generate_gs_svb_write(inst, dst, src[0], src[1]);
1433 break;
1434
1435 case GS_OPCODE_SVB_SET_DST_INDEX:
1436 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1437 break;
1438
1439 case GS_OPCODE_THREAD_END:
1440 generate_gs_thread_end(inst);
1441 break;
1442
1443 case GS_OPCODE_SET_WRITE_OFFSET:
1444 generate_gs_set_write_offset(dst, src[0], src[1]);
1445 break;
1446
1447 case GS_OPCODE_SET_VERTEX_COUNT:
1448 generate_gs_set_vertex_count(dst, src[0]);
1449 break;
1450
1451 case GS_OPCODE_FF_SYNC:
1452 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1453 break;
1454
1455 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1456 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1457 break;
1458
1459 case GS_OPCODE_SET_PRIMITIVE_ID:
1460 generate_gs_set_primitive_id(dst);
1461 break;
1462
1463 case GS_OPCODE_SET_DWORD_2:
1464 generate_gs_set_dword_2(dst, src[0]);
1465 break;
1466
1467 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1468 generate_gs_prepare_channel_masks(dst);
1469 break;
1470
1471 case GS_OPCODE_SET_CHANNEL_MASKS:
1472 generate_gs_set_channel_masks(dst, src[0]);
1473 break;
1474
1475 case GS_OPCODE_GET_INSTANCE_ID:
1476 generate_gs_get_instance_id(dst);
1477 break;
1478
1479 case SHADER_OPCODE_SHADER_TIME_ADD:
1480 brw_shader_time_add(p, src[0],
1481 prog_data->base.binding_table.shader_time_start);
1482 brw_mark_surface_used(&prog_data->base,
1483 prog_data->base.binding_table.shader_time_start);
1484 break;
1485
1486 case SHADER_OPCODE_UNTYPED_ATOMIC:
1487 generate_untyped_atomic(inst, dst, src[0], src[1]);
1488 break;
1489
1490 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1491 generate_untyped_surface_read(inst, dst, src[0]);
1492 break;
1493
1494 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1495 generate_unpack_flags(inst, dst);
1496 break;
1497
1498 default:
1499 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1500 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1501 opcode_descs[inst->opcode].name);
1502 } else {
1503 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1504 }
1505 abort();
1506 }
1507
1508 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1509 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1510 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1511 "emitting more than 1 instruction");
1512
1513 brw_inst *last = &p->store[pre_emit_nr_insn];
1514
1515 if (inst->conditional_mod)
1516 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1517 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1518 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1519 }
1520 }
1521
1522 brw_set_uip_jip(p);
1523 annotation_finalize(&annotation, p->next_insn_offset);
1524
1525 int before_size = p->next_insn_offset;
1526 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1527 int after_size = p->next_insn_offset;
1528
1529 if (unlikely(debug_flag)) {
1530 if (shader_prog) {
1531 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1532 shader_prog->Label ? shader_prog->Label : "unnamed",
1533 shader_prog->Name);
1534 } else {
1535 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1536 }
1537 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1538 " bytes (%.0f%%)\n",
1539 before_size / 16, loop_count, before_size, after_size,
1540 100.0f * (before_size - after_size) / before_size);
1541
1542 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1543 ralloc_free(annotation.ann);
1544 }
1545 }
1546
1547 const unsigned *
1548 vec4_generator::generate_assembly(const cfg_t *cfg,
1549 unsigned *assembly_size)
1550 {
1551 brw_set_default_access_mode(p, BRW_ALIGN_16);
1552 generate_code(cfg);
1553
1554 return brw_get_program(p, assembly_size);
1555 }
1556
1557 } /* namespace brw */