1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "glsl/glsl_parser_extras.h"
27 #include "brw_program.h"
32 generate_math1_gen4(struct brw_codegen
*p
,
33 vec4_instruction
*inst
,
39 brw_math_function(inst
->opcode
),
42 BRW_MATH_PRECISION_FULL
);
46 check_gen6_math_src_arg(struct brw_reg src
)
48 /* Source swizzles are ignored. */
51 assert(src
.swizzle
== BRW_SWIZZLE_XYZW
);
55 generate_math_gen6(struct brw_codegen
*p
,
56 vec4_instruction
*inst
,
61 /* Can't do writemask because math can't be align16. */
62 assert(dst
.writemask
== WRITEMASK_XYZW
);
63 /* Source swizzles are ignored. */
64 check_gen6_math_src_arg(src0
);
65 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
66 check_gen6_math_src_arg(src1
);
68 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
69 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
70 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
74 generate_math2_gen4(struct brw_codegen
*p
,
75 vec4_instruction
*inst
,
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
83 * "Operand0[7]. For the INT DIV functions, this operand is the
86 * "Operand1[7]. For the INT DIV functions, this operand is the
89 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
90 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
91 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
93 brw_push_insn_state(p
);
94 brw_set_default_saturate(p
, false);
95 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
96 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
97 brw_pop_insn_state(p
);
101 brw_math_function(inst
->opcode
),
104 BRW_MATH_PRECISION_FULL
);
108 generate_tex(struct brw_codegen
*p
,
109 struct brw_vue_prog_data
*prog_data
,
110 vec4_instruction
*inst
,
113 struct brw_reg surface_index
,
114 struct brw_reg sampler_index
)
116 const struct brw_device_info
*devinfo
= p
->devinfo
;
119 if (devinfo
->gen
>= 5) {
120 switch (inst
->opcode
) {
121 case SHADER_OPCODE_TEX
:
122 case SHADER_OPCODE_TXL
:
123 if (inst
->shadow_compare
) {
124 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
126 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
129 case SHADER_OPCODE_TXD
:
130 if (inst
->shadow_compare
) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
133 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
135 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
138 case SHADER_OPCODE_TXF
:
139 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
141 case SHADER_OPCODE_TXF_CMS_W
:
142 assert(devinfo
->gen
>= 9);
143 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
145 case SHADER_OPCODE_TXF_CMS
:
146 if (devinfo
->gen
>= 7)
147 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
149 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
151 case SHADER_OPCODE_TXF_MCS
:
152 assert(devinfo
->gen
>= 7);
153 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
155 case SHADER_OPCODE_TXS
:
156 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
158 case SHADER_OPCODE_TG4
:
159 if (inst
->shadow_compare
) {
160 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
162 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
165 case SHADER_OPCODE_TG4_OFFSET
:
166 if (inst
->shadow_compare
) {
167 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
169 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
172 case SHADER_OPCODE_SAMPLEINFO
:
173 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
176 unreachable("should not get here: invalid vec4 texture opcode");
179 switch (inst
->opcode
) {
180 case SHADER_OPCODE_TEX
:
181 case SHADER_OPCODE_TXL
:
182 if (inst
->shadow_compare
) {
183 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
184 assert(inst
->mlen
== 3);
186 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
187 assert(inst
->mlen
== 2);
190 case SHADER_OPCODE_TXD
:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
193 assert(inst
->mlen
== 4);
195 case SHADER_OPCODE_TXF
:
196 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
197 assert(inst
->mlen
== 2);
199 case SHADER_OPCODE_TXS
:
200 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
201 assert(inst
->mlen
== 2);
204 unreachable("should not get here: invalid vec4 texture opcode");
208 assert(msg_type
!= -1);
210 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
216 if (inst
->header_size
!= 0) {
217 if (devinfo
->gen
< 6 && !inst
->offset
) {
218 /* Set up an implied move from g0 to the MRF. */
219 src
= brw_vec8_grf(0, 0);
221 struct brw_reg header
=
222 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p
);
227 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
228 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
230 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
233 /* Set the texel offset bits in DWord 2. */
236 if (devinfo
->gen
>= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
240 dw2
|= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
;
243 brw_MOV(p
, get_element_ud(header
, 2), brw_imm_ud(dw2
));
245 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
);
246 brw_pop_insn_state(p
);
250 uint32_t return_format
;
253 case BRW_REGISTER_TYPE_D
:
254 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
256 case BRW_REGISTER_TYPE_UD
:
257 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
260 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
264 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
265 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
266 ? prog_data
->base
.binding_table
.gather_texture_start
267 : prog_data
->base
.binding_table
.texture_start
;
269 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
270 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
271 uint32_t surface
= surface_index
.ud
;
272 uint32_t sampler
= sampler_index
.ud
;
278 surface
+ base_binding_table_index
,
281 1, /* response length */
283 inst
->header_size
!= 0,
284 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
287 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
289 /* Non-constant sampler index. */
291 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
292 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
293 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
295 brw_push_insn_state(p
);
296 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
297 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
299 if (memcmp(&surface_reg
, &sampler_reg
, sizeof(surface_reg
)) == 0) {
300 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
302 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
303 brw_OR(p
, addr
, addr
, surface_reg
);
305 if (base_binding_table_index
)
306 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
307 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
309 brw_pop_insn_state(p
);
311 if (inst
->base_mrf
!= -1)
312 gen6_resolve_implied_move(p
, &src
, inst
->base_mrf
);
314 /* dst = send(offset, a0.0 | <descriptor>) */
315 brw_inst
*insn
= brw_send_indirect_message(
316 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
317 brw_set_sampler_message(p
, insn
,
322 inst
->mlen
/* mlen */,
323 inst
->header_size
!= 0 /* header */,
324 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
327 /* visitor knows more than we do about the surface limit required,
328 * so has already done marking.
334 generate_vs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
337 brw_null_reg(), /* dest */
338 inst
->base_mrf
, /* starting mrf reg nr */
339 brw_vec8_grf(0, 0), /* src */
340 inst
->urb_write_flags
,
342 0, /* response len */
343 inst
->offset
, /* urb destination offset */
344 BRW_URB_SWIZZLE_INTERLEAVE
);
348 generate_gs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
350 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
352 brw_null_reg(), /* dest */
353 inst
->base_mrf
, /* starting mrf reg nr */
355 inst
->urb_write_flags
,
357 0, /* response len */
358 inst
->offset
, /* urb destination offset */
359 BRW_URB_SWIZZLE_INTERLEAVE
);
363 generate_gs_urb_write_allocate(struct brw_codegen
*p
, vec4_instruction
*inst
)
365 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
367 /* We pass the temporary passed in src0 as the writeback register */
369 inst
->src
[0].as_brw_reg(), /* dest */
370 inst
->base_mrf
, /* starting mrf reg nr */
372 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
374 1, /* response len */
375 inst
->offset
, /* urb destination offset */
376 BRW_URB_SWIZZLE_INTERLEAVE
);
378 /* Now put allocated urb handle in dst.0 */
379 brw_push_insn_state(p
);
380 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
381 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
382 brw_MOV(p
, get_element_ud(inst
->dst
.as_brw_reg(), 0),
383 get_element_ud(inst
->src
[0].as_brw_reg(), 0));
384 brw_pop_insn_state(p
);
388 generate_gs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
390 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
392 brw_null_reg(), /* dest */
393 inst
->base_mrf
, /* starting mrf reg nr */
395 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
397 0, /* response len */
398 0, /* urb destination offset */
399 BRW_URB_SWIZZLE_INTERLEAVE
);
403 generate_gs_set_write_offset(struct brw_codegen
*p
,
408 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
411 * Slot 0 Offset. This field, after adding to the Global Offset field
412 * in the message descriptor, specifies the offset (in 256-bit units)
413 * from the start of the URB entry, as referenced by URB Handle 0, at
414 * which the data will be accessed.
416 * Similar text describes DWORD M0.4, which is slot 1 offset.
418 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
419 * of the register for geometry shader invocations 0 and 1) by the
420 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
422 * We can do this with the following EU instruction:
424 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
426 brw_push_insn_state(p
);
427 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
428 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
429 assert(p
->devinfo
->gen
>= 7 &&
430 src1
.file
== BRW_IMMEDIATE_VALUE
&&
431 src1
.type
== BRW_REGISTER_TYPE_UD
&&
432 src1
.ud
<= USHRT_MAX
);
433 if (src0
.file
== BRW_IMMEDIATE_VALUE
) {
434 brw_MOV(p
, suboffset(stride(dst
, 2, 2, 1), 3),
435 brw_imm_ud(src0
.ud
* src1
.ud
));
437 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
438 retype(src1
, BRW_REGISTER_TYPE_UW
));
440 brw_pop_insn_state(p
);
444 generate_gs_set_vertex_count(struct brw_codegen
*p
,
448 brw_push_insn_state(p
);
449 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
451 if (p
->devinfo
->gen
>= 8) {
452 /* Move the vertex count into the second MRF for the EOT write. */
453 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
456 /* If we think of the src and dst registers as composed of 8 DWORDs each,
457 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
458 * them to WORDs, and then pack them into DWORD 2 of dst.
460 * It's easier to get the EU to do this if we think of the src and dst
461 * registers as composed of 16 WORDS each; then, we want to pick up the
462 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
465 * We can do that by the following EU instruction:
467 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
469 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
471 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
472 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
474 brw_pop_insn_state(p
);
478 generate_gs_svb_write(struct brw_codegen
*p
,
479 struct brw_vue_prog_data
*prog_data
,
480 vec4_instruction
*inst
,
485 int binding
= inst
->sol_binding
;
486 bool final_write
= inst
->sol_final_write
;
488 brw_push_insn_state(p
);
489 /* Copy Vertex data into M0.x */
490 brw_MOV(p
, stride(dst
, 4, 4, 1),
491 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
495 final_write
? src1
: brw_null_reg(), /* dest == src1 */
497 dst
, /* src0 == previous dst */
498 SURF_INDEX_GEN6_SOL_BINDING(binding
), /* binding_table_index */
499 final_write
); /* send_commit_msg */
501 /* Finally, wait for the write commit to occur so that we can proceed to
502 * other things safely.
504 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
506 * The write commit does not modify the destination register, but
507 * merely clears the dependency associated with the destination
508 * register. Thus, a simple “mov” instruction using the register as a
509 * source is sufficient to wait for the write commit to occur.
512 brw_MOV(p
, src1
, src1
);
514 brw_pop_insn_state(p
);
518 generate_gs_svb_set_destination_index(struct brw_codegen
*p
,
519 vec4_instruction
*inst
,
523 int vertex
= inst
->sol_vertex
;
524 brw_push_insn_state(p
);
525 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
526 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
527 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
528 brw_pop_insn_state(p
);
532 generate_gs_set_dword_2(struct brw_codegen
*p
,
536 brw_push_insn_state(p
);
537 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
538 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
539 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
540 brw_pop_insn_state(p
);
544 generate_gs_prepare_channel_masks(struct brw_codegen
*p
,
547 /* We want to left shift just DWORD 4 (the x component belonging to the
548 * second geometry shader invocation) by 4 bits. So generate the
551 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
553 dst
= suboffset(vec1(dst
), 4);
554 brw_push_insn_state(p
);
555 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
556 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
557 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
558 brw_pop_insn_state(p
);
562 generate_gs_set_channel_masks(struct brw_codegen
*p
,
566 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
569 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
571 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
572 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
573 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
574 * channel enable to determine the final channel enable. For the
575 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
576 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
577 * in the writeback message. For the URB_WRITE_OWORD &
578 * URB_WRITE_HWORD messages, when final channel enable is 1 it
579 * indicates that Vertex 1 DATA [3] will be written to the surface.
581 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
582 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
584 * 14 Vertex 1 DATA [2] Channel Mask
585 * 13 Vertex 1 DATA [1] Channel Mask
586 * 12 Vertex 1 DATA [0] Channel Mask
587 * 11 Vertex 0 DATA [3] Channel Mask
588 * 10 Vertex 0 DATA [2] Channel Mask
589 * 9 Vertex 0 DATA [1] Channel Mask
590 * 8 Vertex 0 DATA [0] Channel Mask
592 * (This is from a section of the PRM that is agnostic to the particular
593 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
594 * geometry shader invocations 0 and 1, respectively). Since we have the
595 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
596 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
597 * DWORD 4, we just need to OR them together and store the result in bits
600 * It's easier to get the EU to do this if we think of the src and dst
601 * registers as composed of 32 bytes each; then, we want to pick up the
602 * contents of bytes 0 and 16 from src, OR them together, and store them in
605 * We can do that by the following EU instruction:
607 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
609 * Note: this relies on the source register having zeros in (a) bits 7:4 of
610 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
611 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
612 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
613 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
614 * contain valid channel mask values (which are in the range 0x0-0xf).
616 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
617 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
618 brw_push_insn_state(p
);
619 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
620 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
621 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
622 brw_pop_insn_state(p
);
626 generate_gs_get_instance_id(struct brw_codegen
*p
,
629 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
630 * and store into dst.0 & dst.4. So generate the instruction:
632 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
634 brw_push_insn_state(p
);
635 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
636 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
637 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
638 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
639 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
640 brw_pop_insn_state(p
);
644 generate_gs_ff_sync_set_primitives(struct brw_codegen
*p
,
650 brw_push_insn_state(p
);
651 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
652 /* Save src0 data in 16:31 bits of dst.0 */
653 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
654 brw_imm_ud(0xffffu
));
655 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
656 /* Save src1 data in 0:15 bits of dst.0 */
657 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
658 brw_imm_ud(0xffffu
));
659 brw_OR(p
, suboffset(vec1(dst
), 0),
660 suboffset(vec1(dst
), 0),
661 suboffset(vec1(src2
), 0));
662 brw_pop_insn_state(p
);
666 generate_gs_ff_sync(struct brw_codegen
*p
,
667 vec4_instruction
*inst
,
672 /* This opcode uses an implied MRF register for:
673 * - the header of the ff_sync message. And as such it is expected to be
674 * initialized to r0 before calling here.
675 * - the destination where we will write the allocated URB handle.
677 struct brw_reg header
=
678 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
680 /* Overwrite dword 0 of the header (SO vertices to write) and
681 * dword 1 (number of primitives written).
683 brw_push_insn_state(p
);
684 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
685 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
686 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(src1
, 0));
687 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
688 brw_pop_insn_state(p
);
690 /* Allocate URB handle in dst */
696 1, /* response length */
699 /* Now put allocated urb handle in header.0 */
700 brw_push_insn_state(p
);
701 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
702 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
703 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
705 /* src1 is not an immediate when we use transform feedback */
706 if (src1
.file
!= BRW_IMMEDIATE_VALUE
)
707 brw_MOV(p
, brw_vec4_grf(src1
.nr
, 0), brw_vec4_grf(dst
.nr
, 1));
709 brw_pop_insn_state(p
);
713 generate_gs_set_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
715 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
716 struct brw_reg src
= brw_vec8_grf(0, 0);
717 brw_push_insn_state(p
);
718 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
719 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
720 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
721 brw_pop_insn_state(p
);
725 generate_oword_dual_block_offsets(struct brw_codegen
*p
,
727 struct brw_reg index
)
729 int second_vertex_offset
;
731 if (p
->devinfo
->gen
>= 6)
732 second_vertex_offset
= 1;
734 second_vertex_offset
= 16;
736 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
738 /* Set up M1 (message payload). Only the block offsets in M1.0 and
739 * M1.4 are used, and the rest are ignored.
741 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
742 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
743 struct brw_reg index_0
= suboffset(vec1(index
), 0);
744 struct brw_reg index_4
= suboffset(vec1(index
), 4);
746 brw_push_insn_state(p
);
747 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
748 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
750 brw_MOV(p
, m1_0
, index_0
);
752 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
753 index_4
.ud
+= second_vertex_offset
;
754 brw_MOV(p
, m1_4
, index_4
);
756 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
759 brw_pop_insn_state(p
);
763 generate_unpack_flags(struct brw_codegen
*p
,
766 brw_push_insn_state(p
);
767 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
768 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
770 struct brw_reg flags
= brw_flag_reg(0, 0);
771 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
772 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
774 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
775 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
776 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
778 brw_pop_insn_state(p
);
782 generate_scratch_read(struct brw_codegen
*p
,
783 vec4_instruction
*inst
,
785 struct brw_reg index
)
787 const struct brw_device_info
*devinfo
= p
->devinfo
;
788 struct brw_reg header
= brw_vec8_grf(0, 0);
790 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
792 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
797 if (devinfo
->gen
>= 6)
798 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
799 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
800 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
802 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
804 /* Each of the 8 channel enables is considered for whether each
807 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
808 brw_set_dest(p
, send
, dst
);
809 brw_set_src0(p
, send
, header
);
810 if (devinfo
->gen
< 6)
811 brw_inst_set_cond_modifier(devinfo
, send
, inst
->base_mrf
);
812 brw_set_dp_read_message(p
, send
,
813 brw_scratch_surface_idx(p
),
814 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
816 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
818 true, /* header_present */
823 generate_scratch_write(struct brw_codegen
*p
,
824 vec4_instruction
*inst
,
827 struct brw_reg index
)
829 const struct brw_device_info
*devinfo
= p
->devinfo
;
830 struct brw_reg header
= brw_vec8_grf(0, 0);
833 /* If the instruction is predicated, we'll predicate the send, not
836 brw_set_default_predicate_control(p
, false);
838 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
840 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
844 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
845 retype(src
, BRW_REGISTER_TYPE_D
));
849 if (devinfo
->gen
>= 7)
850 msg_type
= GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
;
851 else if (devinfo
->gen
== 6)
852 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
854 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
856 brw_set_default_predicate_control(p
, inst
->predicate
);
858 /* Pre-gen6, we have to specify write commits to ensure ordering
859 * between reads and writes within a thread. Afterwards, that's
860 * guaranteed and write commits only matter for inter-thread
863 if (devinfo
->gen
>= 6) {
864 write_commit
= false;
866 /* The visitor set up our destination register to be g0. This
867 * means that when the next read comes along, we will end up
868 * reading from g0 and causing a block on the write commit. For
869 * write-after-read, we are relying on the value of the previous
870 * read being used (and thus blocking on completion) before our
871 * write is executed. This means we have to be careful in
872 * instruction scheduling to not violate this assumption.
877 /* Each of the 8 channel enables is considered for whether each
880 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
881 brw_set_dest(p
, send
, dst
);
882 brw_set_src0(p
, send
, header
);
883 if (devinfo
->gen
< 6)
884 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
885 brw_set_dp_write_message(p
, send
,
886 brw_scratch_surface_idx(p
),
887 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
890 true, /* header present */
891 false, /* not a render target write */
892 write_commit
, /* rlen */
898 generate_pull_constant_load(struct brw_codegen
*p
,
899 struct brw_vue_prog_data
*prog_data
,
900 vec4_instruction
*inst
,
902 struct brw_reg index
,
903 struct brw_reg offset
)
905 const struct brw_device_info
*devinfo
= p
->devinfo
;
906 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
907 index
.type
== BRW_REGISTER_TYPE_UD
);
908 uint32_t surf_index
= index
.ud
;
910 struct brw_reg header
= brw_vec8_grf(0, 0);
912 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
914 if (devinfo
->gen
>= 6) {
915 if (offset
.file
== BRW_IMMEDIATE_VALUE
) {
916 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
917 BRW_REGISTER_TYPE_D
),
918 brw_imm_d(offset
.ud
>> 4));
920 brw_SHR(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
921 BRW_REGISTER_TYPE_D
),
922 offset
, brw_imm_d(4));
925 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
926 BRW_REGISTER_TYPE_D
),
932 if (devinfo
->gen
>= 6)
933 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
934 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
935 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
937 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
939 /* Each of the 8 channel enables is considered for whether each
942 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
943 brw_set_dest(p
, send
, dst
);
944 brw_set_src0(p
, send
, header
);
945 if (devinfo
->gen
< 6)
946 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
947 brw_set_dp_read_message(p
, send
,
949 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
951 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
953 true, /* header_present */
958 generate_get_buffer_size(struct brw_codegen
*p
,
959 struct brw_vue_prog_data
*prog_data
,
960 vec4_instruction
*inst
,
963 struct brw_reg surf_index
)
965 assert(p
->devinfo
->gen
>= 7);
966 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
&&
967 surf_index
.file
== BRW_IMMEDIATE_VALUE
);
975 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
976 1, /* response length */
978 inst
->header_size
> 0,
979 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
980 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
982 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
986 generate_pull_constant_load_gen7(struct brw_codegen
*p
,
987 struct brw_vue_prog_data
*prog_data
,
988 vec4_instruction
*inst
,
990 struct brw_reg surf_index
,
991 struct brw_reg offset
)
993 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
995 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
997 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
998 brw_set_dest(p
, insn
, dst
);
999 brw_set_src0(p
, insn
, offset
);
1000 brw_set_sampler_message(p
, insn
,
1002 0, /* LD message ignores sampler unit */
1003 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1006 inst
->header_size
!= 0,
1007 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1010 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1014 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1016 brw_push_insn_state(p
);
1017 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1018 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1020 /* a0.0 = surf_index & 0xff */
1021 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1022 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1023 brw_set_dest(p
, insn_and
, addr
);
1024 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1025 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1027 brw_pop_insn_state(p
);
1029 /* dst = send(offset, a0.0 | <descriptor>) */
1030 brw_inst
*insn
= brw_send_indirect_message(
1031 p
, BRW_SFID_SAMPLER
, dst
, offset
, addr
);
1032 brw_set_sampler_message(p
, insn
,
1035 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1038 inst
->header_size
!= 0,
1039 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1045 generate_set_simd4x2_header_gen9(struct brw_codegen
*p
,
1046 vec4_instruction
*inst
,
1049 brw_push_insn_state(p
);
1050 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1052 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1053 brw_MOV(p
, vec8(dst
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1055 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1056 brw_MOV(p
, get_element_ud(dst
, 2),
1057 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1059 brw_pop_insn_state(p
);
1063 generate_code(struct brw_codegen
*p
,
1064 const struct brw_compiler
*compiler
,
1066 const nir_shader
*nir
,
1067 struct brw_vue_prog_data
*prog_data
,
1068 const struct cfg_t
*cfg
)
1070 const struct brw_device_info
*devinfo
= p
->devinfo
;
1071 const char *stage_abbrev
= _mesa_shader_stage_to_abbrev(nir
->stage
);
1072 bool debug_flag
= INTEL_DEBUG
&
1073 intel_debug_flag_for_shader_stage(nir
->stage
);
1074 struct annotation_info annotation
;
1075 memset(&annotation
, 0, sizeof(annotation
));
1078 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1079 struct brw_reg src
[3], dst
;
1081 if (unlikely(debug_flag
))
1082 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1084 for (unsigned int i
= 0; i
< 3; i
++) {
1085 src
[i
] = inst
->src
[i
].as_brw_reg();
1087 dst
= inst
->dst
.as_brw_reg();
1089 brw_set_default_predicate_control(p
, inst
->predicate
);
1090 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1091 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1092 brw_set_default_saturate(p
, inst
->saturate
);
1093 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1094 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1096 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1097 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1099 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1101 if (dst
.width
== BRW_WIDTH_4
) {
1102 /* This happens in attribute fixups for "dual instanced" geometry
1103 * shaders, since they use attributes that are vec4's. Since the exec
1104 * width is only 4, it's essential that the caller set
1105 * force_writemask_all in order to make sure the instruction is executed
1106 * regardless of which channels are enabled.
1108 assert(inst
->force_writemask_all
);
1110 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1111 * the following register region restrictions (from Graphics BSpec:
1112 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1113 * > Register Region Restrictions)
1115 * 1. ExecSize must be greater than or equal to Width.
1117 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1118 * to Width * HorzStride."
1120 for (int i
= 0; i
< 3; i
++) {
1121 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
1122 src
[i
] = stride(src
[i
], 4, 4, 1);
1126 switch (inst
->opcode
) {
1127 case VEC4_OPCODE_UNPACK_UNIFORM
:
1128 case BRW_OPCODE_MOV
:
1129 brw_MOV(p
, dst
, src
[0]);
1131 case BRW_OPCODE_ADD
:
1132 brw_ADD(p
, dst
, src
[0], src
[1]);
1134 case BRW_OPCODE_MUL
:
1135 brw_MUL(p
, dst
, src
[0], src
[1]);
1137 case BRW_OPCODE_MACH
:
1138 brw_MACH(p
, dst
, src
[0], src
[1]);
1141 case BRW_OPCODE_MAD
:
1142 assert(devinfo
->gen
>= 6);
1143 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1146 case BRW_OPCODE_FRC
:
1147 brw_FRC(p
, dst
, src
[0]);
1149 case BRW_OPCODE_RNDD
:
1150 brw_RNDD(p
, dst
, src
[0]);
1152 case BRW_OPCODE_RNDE
:
1153 brw_RNDE(p
, dst
, src
[0]);
1155 case BRW_OPCODE_RNDZ
:
1156 brw_RNDZ(p
, dst
, src
[0]);
1159 case BRW_OPCODE_AND
:
1160 brw_AND(p
, dst
, src
[0], src
[1]);
1163 brw_OR(p
, dst
, src
[0], src
[1]);
1165 case BRW_OPCODE_XOR
:
1166 brw_XOR(p
, dst
, src
[0], src
[1]);
1168 case BRW_OPCODE_NOT
:
1169 brw_NOT(p
, dst
, src
[0]);
1171 case BRW_OPCODE_ASR
:
1172 brw_ASR(p
, dst
, src
[0], src
[1]);
1174 case BRW_OPCODE_SHR
:
1175 brw_SHR(p
, dst
, src
[0], src
[1]);
1177 case BRW_OPCODE_SHL
:
1178 brw_SHL(p
, dst
, src
[0], src
[1]);
1181 case BRW_OPCODE_CMP
:
1182 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1184 case BRW_OPCODE_SEL
:
1185 brw_SEL(p
, dst
, src
[0], src
[1]);
1188 case BRW_OPCODE_DPH
:
1189 brw_DPH(p
, dst
, src
[0], src
[1]);
1192 case BRW_OPCODE_DP4
:
1193 brw_DP4(p
, dst
, src
[0], src
[1]);
1196 case BRW_OPCODE_DP3
:
1197 brw_DP3(p
, dst
, src
[0], src
[1]);
1200 case BRW_OPCODE_DP2
:
1201 brw_DP2(p
, dst
, src
[0], src
[1]);
1204 case BRW_OPCODE_F32TO16
:
1205 assert(devinfo
->gen
>= 7);
1206 brw_F32TO16(p
, dst
, src
[0]);
1209 case BRW_OPCODE_F16TO32
:
1210 assert(devinfo
->gen
>= 7);
1211 brw_F16TO32(p
, dst
, src
[0]);
1214 case BRW_OPCODE_LRP
:
1215 assert(devinfo
->gen
>= 6);
1216 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1219 case BRW_OPCODE_BFREV
:
1220 assert(devinfo
->gen
>= 7);
1221 /* BFREV only supports UD type for src and dst. */
1222 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1223 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1225 case BRW_OPCODE_FBH
:
1226 assert(devinfo
->gen
>= 7);
1227 /* FBH only supports UD type for dst. */
1228 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1230 case BRW_OPCODE_FBL
:
1231 assert(devinfo
->gen
>= 7);
1232 /* FBL only supports UD type for dst. */
1233 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1235 case BRW_OPCODE_CBIT
:
1236 assert(devinfo
->gen
>= 7);
1237 /* CBIT only supports UD type for dst. */
1238 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1240 case BRW_OPCODE_ADDC
:
1241 assert(devinfo
->gen
>= 7);
1242 brw_ADDC(p
, dst
, src
[0], src
[1]);
1244 case BRW_OPCODE_SUBB
:
1245 assert(devinfo
->gen
>= 7);
1246 brw_SUBB(p
, dst
, src
[0], src
[1]);
1248 case BRW_OPCODE_MAC
:
1249 brw_MAC(p
, dst
, src
[0], src
[1]);
1252 case BRW_OPCODE_BFE
:
1253 assert(devinfo
->gen
>= 7);
1254 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1257 case BRW_OPCODE_BFI1
:
1258 assert(devinfo
->gen
>= 7);
1259 brw_BFI1(p
, dst
, src
[0], src
[1]);
1261 case BRW_OPCODE_BFI2
:
1262 assert(devinfo
->gen
>= 7);
1263 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1267 if (!inst
->src
[0].is_null()) {
1268 /* The instruction has an embedded compare (only allowed on gen6) */
1269 assert(devinfo
->gen
== 6);
1270 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1272 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1273 brw_inst_set_pred_control(p
->devinfo
, if_inst
, inst
->predicate
);
1277 case BRW_OPCODE_ELSE
:
1280 case BRW_OPCODE_ENDIF
:
1285 brw_DO(p
, BRW_EXECUTE_8
);
1288 case BRW_OPCODE_BREAK
:
1290 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1292 case BRW_OPCODE_CONTINUE
:
1294 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1297 case BRW_OPCODE_WHILE
:
1302 case SHADER_OPCODE_RCP
:
1303 case SHADER_OPCODE_RSQ
:
1304 case SHADER_OPCODE_SQRT
:
1305 case SHADER_OPCODE_EXP2
:
1306 case SHADER_OPCODE_LOG2
:
1307 case SHADER_OPCODE_SIN
:
1308 case SHADER_OPCODE_COS
:
1309 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1310 if (devinfo
->gen
>= 7) {
1311 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1313 } else if (devinfo
->gen
== 6) {
1314 generate_math_gen6(p
, inst
, dst
, src
[0], brw_null_reg());
1316 generate_math1_gen4(p
, inst
, dst
, src
[0]);
1320 case SHADER_OPCODE_POW
:
1321 case SHADER_OPCODE_INT_QUOTIENT
:
1322 case SHADER_OPCODE_INT_REMAINDER
:
1323 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1324 if (devinfo
->gen
>= 7) {
1325 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1326 } else if (devinfo
->gen
== 6) {
1327 generate_math_gen6(p
, inst
, dst
, src
[0], src
[1]);
1329 generate_math2_gen4(p
, inst
, dst
, src
[0], src
[1]);
1333 case SHADER_OPCODE_TEX
:
1334 case SHADER_OPCODE_TXD
:
1335 case SHADER_OPCODE_TXF
:
1336 case SHADER_OPCODE_TXF_CMS
:
1337 case SHADER_OPCODE_TXF_CMS_W
:
1338 case SHADER_OPCODE_TXF_MCS
:
1339 case SHADER_OPCODE_TXL
:
1340 case SHADER_OPCODE_TXS
:
1341 case SHADER_OPCODE_TG4
:
1342 case SHADER_OPCODE_TG4_OFFSET
:
1343 case SHADER_OPCODE_SAMPLEINFO
:
1344 generate_tex(p
, prog_data
, inst
, dst
, src
[0], src
[1], src
[1]);
1347 case VS_OPCODE_URB_WRITE
:
1348 generate_vs_urb_write(p
, inst
);
1351 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1352 generate_scratch_read(p
, inst
, dst
, src
[0]);
1355 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1356 generate_scratch_write(p
, inst
, dst
, src
[0], src
[1]);
1359 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1360 generate_pull_constant_load(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1363 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1364 generate_pull_constant_load_gen7(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1367 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
1368 generate_set_simd4x2_header_gen9(p
, inst
, dst
);
1372 case VS_OPCODE_GET_BUFFER_SIZE
:
1373 generate_get_buffer_size(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1376 case GS_OPCODE_URB_WRITE
:
1377 generate_gs_urb_write(p
, inst
);
1380 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1381 generate_gs_urb_write_allocate(p
, inst
);
1384 case GS_OPCODE_SVB_WRITE
:
1385 generate_gs_svb_write(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1388 case GS_OPCODE_SVB_SET_DST_INDEX
:
1389 generate_gs_svb_set_destination_index(p
, inst
, dst
, src
[0]);
1392 case GS_OPCODE_THREAD_END
:
1393 generate_gs_thread_end(p
, inst
);
1396 case GS_OPCODE_SET_WRITE_OFFSET
:
1397 generate_gs_set_write_offset(p
, dst
, src
[0], src
[1]);
1400 case GS_OPCODE_SET_VERTEX_COUNT
:
1401 generate_gs_set_vertex_count(p
, dst
, src
[0]);
1404 case GS_OPCODE_FF_SYNC
:
1405 generate_gs_ff_sync(p
, inst
, dst
, src
[0], src
[1]);
1408 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1409 generate_gs_ff_sync_set_primitives(p
, dst
, src
[0], src
[1], src
[2]);
1412 case GS_OPCODE_SET_PRIMITIVE_ID
:
1413 generate_gs_set_primitive_id(p
, dst
);
1416 case GS_OPCODE_SET_DWORD_2
:
1417 generate_gs_set_dword_2(p
, dst
, src
[0]);
1420 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1421 generate_gs_prepare_channel_masks(p
, dst
);
1424 case GS_OPCODE_SET_CHANNEL_MASKS
:
1425 generate_gs_set_channel_masks(p
, dst
, src
[0]);
1428 case GS_OPCODE_GET_INSTANCE_ID
:
1429 generate_gs_get_instance_id(p
, dst
);
1432 case SHADER_OPCODE_SHADER_TIME_ADD
:
1433 brw_shader_time_add(p
, src
[0],
1434 prog_data
->base
.binding_table
.shader_time_start
);
1435 brw_mark_surface_used(&prog_data
->base
,
1436 prog_data
->base
.binding_table
.shader_time_start
);
1439 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1440 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1441 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1442 !inst
->dst
.is_null());
1445 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1446 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1447 brw_untyped_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1451 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1452 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1453 brw_untyped_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1457 case SHADER_OPCODE_TYPED_ATOMIC
:
1458 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1459 brw_typed_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1460 !inst
->dst
.is_null());
1463 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1464 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1465 brw_typed_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1469 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1470 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1471 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1475 case SHADER_OPCODE_MEMORY_FENCE
:
1476 brw_memory_fence(p
, dst
);
1479 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1480 brw_find_live_channel(p
, dst
);
1483 case SHADER_OPCODE_BROADCAST
:
1484 brw_broadcast(p
, dst
, src
[0], src
[1]);
1487 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1488 generate_unpack_flags(p
, dst
);
1491 case VEC4_OPCODE_MOV_BYTES
: {
1492 /* Moves the low byte from each channel, using an Align1 access mode
1493 * and a <4,1,0> source region.
1495 assert(src
[0].type
== BRW_REGISTER_TYPE_UB
||
1496 src
[0].type
== BRW_REGISTER_TYPE_B
);
1498 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1499 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1500 src
[0].width
= BRW_WIDTH_1
;
1501 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1502 brw_MOV(p
, dst
, src
[0]);
1503 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1507 case VEC4_OPCODE_PACK_BYTES
: {
1510 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1512 * but destinations' only regioning is horizontal stride, so instead we
1513 * have to use two instructions:
1515 * mov(4) dst<1>:UB src<4,1,0>:UB
1516 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1518 * where they pack the four bytes from the low and high four DW.
1520 assert(_mesa_is_pow_two(dst
.writemask
) &&
1521 dst
.writemask
!= 0);
1522 unsigned offset
= __builtin_ctz(dst
.writemask
);
1524 dst
.type
= BRW_REGISTER_TYPE_UB
;
1526 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1528 src
[0].type
= BRW_REGISTER_TYPE_UB
;
1529 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1530 src
[0].width
= BRW_WIDTH_1
;
1531 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1532 dst
.subnr
= offset
* 4;
1533 struct brw_inst
*insn
= brw_MOV(p
, dst
, src
[0]);
1534 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1535 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, true);
1536 brw_inst_set_no_dd_check(p
->devinfo
, insn
, inst
->no_dd_check
);
1539 dst
.subnr
= 16 + offset
* 4;
1540 insn
= brw_MOV(p
, dst
, src
[0]);
1541 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
1542 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, inst
->no_dd_clear
);
1543 brw_inst_set_no_dd_check(p
->devinfo
, insn
, true);
1545 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1550 unreachable("Unsupported opcode");
1553 if (inst
->opcode
== VEC4_OPCODE_PACK_BYTES
) {
1554 /* Handled dependency hints in the generator. */
1556 assert(!inst
->conditional_mod
);
1557 } else if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1558 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1559 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1560 "emitting more than 1 instruction");
1562 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1564 if (inst
->conditional_mod
)
1565 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
1566 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
1567 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
1572 annotation_finalize(&annotation
, p
->next_insn_offset
);
1575 bool validated
= brw_validate_instructions(p
, 0, &annotation
);
1577 if (unlikely(debug_flag
))
1578 brw_validate_instructions(p
, 0, &annotation
);
1581 int before_size
= p
->next_insn_offset
;
1582 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1583 int after_size
= p
->next_insn_offset
;
1585 if (unlikely(debug_flag
)) {
1586 fprintf(stderr
, "Native code for %s %s shader %s:\n",
1587 nir
->info
.label
? nir
->info
.label
: "unnamed",
1588 _mesa_shader_stage_to_string(nir
->stage
), nir
->info
.name
);
1590 fprintf(stderr
, "%s vec4 shader: %d instructions. %d loops. %u cycles."
1591 "Compacted %d to %d bytes (%.0f%%)\n",
1593 before_size
/ 16, loop_count
, cfg
->cycle_count
, before_size
, after_size
,
1594 100.0f
* (before_size
- after_size
) / before_size
);
1596 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
1598 ralloc_free(annotation
.mem_ctx
);
1602 compiler
->shader_debug_log(log_data
,
1603 "%s vec4 shader: %d inst, %d loops, %u cycles, "
1604 "compacted %d to %d bytes.\n",
1605 stage_abbrev
, before_size
/ 16,
1606 loop_count
, cfg
->cycle_count
,
1607 before_size
, after_size
);
1610 extern "C" const unsigned *
1611 brw_vec4_generate_assembly(const struct brw_compiler
*compiler
,
1614 const nir_shader
*nir
,
1615 struct brw_vue_prog_data
*prog_data
,
1616 const struct cfg_t
*cfg
,
1617 unsigned *out_assembly_size
)
1619 struct brw_codegen
*p
= rzalloc(mem_ctx
, struct brw_codegen
);
1620 brw_init_codegen(compiler
->devinfo
, p
, mem_ctx
);
1621 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1623 generate_code(p
, compiler
, log_data
, nir
, prog_data
, cfg
);
1625 return brw_get_program(p
, out_assembly_size
);