1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 assert(!"not reached");
64 brw_reg
= brw_null_reg();
71 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
73 struct brw_reg brw_reg
;
75 switch (src
[i
].file
) {
77 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
78 brw_reg
= retype(brw_reg
, src
[i
].type
);
79 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
81 brw_reg
= brw_abs(brw_reg
);
83 brw_reg
= negate(brw_reg
);
87 switch (src
[i
].type
) {
88 case BRW_REGISTER_TYPE_F
:
89 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
91 case BRW_REGISTER_TYPE_D
:
92 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
94 case BRW_REGISTER_TYPE_UD
:
95 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
98 assert(!"not reached");
99 brw_reg
= brw_null_reg();
105 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
106 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
107 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
109 brw_reg
= retype(brw_reg
, src
[i
].type
);
110 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
112 brw_reg
= brw_abs(brw_reg
);
114 brw_reg
= negate(brw_reg
);
116 /* This should have been moved to pull constants. */
117 assert(!src
[i
].reladdr
);
121 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
122 brw_reg
= src
[i
].fixed_hw_reg
;
126 /* Probably unused. */
127 brw_reg
= brw_null_reg();
131 assert(!"not reached");
132 brw_reg
= brw_null_reg();
139 vec4_generator::vec4_generator(struct brw_context
*brw
,
140 struct gl_shader_program
*shader_prog
,
141 struct gl_program
*prog
,
142 struct brw_vec4_prog_data
*prog_data
,
145 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
146 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
148 p
= rzalloc(mem_ctx
, struct brw_compile
);
149 brw_init_compile(brw
, p
, mem_ctx
);
152 vec4_generator::~vec4_generator()
157 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
163 brw_math_function(inst
->opcode
),
166 BRW_MATH_DATA_VECTOR
,
167 BRW_MATH_PRECISION_FULL
);
171 check_gen6_math_src_arg(struct brw_reg src
)
173 /* Source swizzles are ignored. */
176 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
180 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
184 /* Can't do writemask because math can't be align16. */
185 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
186 check_gen6_math_src_arg(src
);
188 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
189 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
, brw_null_reg());
190 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
194 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
199 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
203 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
208 /* Can't do writemask because math can't be align16. */
209 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
210 /* Source swizzles are ignored. */
211 check_gen6_math_src_arg(src0
);
212 check_gen6_math_src_arg(src1
);
214 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
215 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
216 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
220 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
225 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
228 * "Operand0[7]. For the INT DIV functions, this operand is the
231 * "Operand1[7]. For the INT DIV functions, this operand is the
234 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
235 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
236 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
238 brw_push_insn_state(p
);
239 brw_set_default_saturate(p
, false);
240 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
241 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
242 brw_pop_insn_state(p
);
246 brw_math_function(inst
->opcode
),
249 BRW_MATH_DATA_VECTOR
,
250 BRW_MATH_PRECISION_FULL
);
254 vec4_generator::generate_tex(vec4_instruction
*inst
,
261 switch (inst
->opcode
) {
262 case SHADER_OPCODE_TEX
:
263 case SHADER_OPCODE_TXL
:
264 if (inst
->shadow_compare
) {
265 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
267 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
270 case SHADER_OPCODE_TXD
:
271 if (inst
->shadow_compare
) {
272 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
273 assert(brw
->is_haswell
);
274 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
276 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
279 case SHADER_OPCODE_TXF
:
280 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
282 case SHADER_OPCODE_TXF_CMS
:
284 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
286 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
288 case SHADER_OPCODE_TXF_MCS
:
289 assert(brw
->gen
>= 7);
290 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
292 case SHADER_OPCODE_TXS
:
293 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
295 case SHADER_OPCODE_TG4
:
296 if (inst
->shadow_compare
) {
297 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
299 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
302 case SHADER_OPCODE_TG4_OFFSET
:
303 if (inst
->shadow_compare
) {
304 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
306 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
310 assert(!"should not get here: invalid vec4 texture opcode");
314 switch (inst
->opcode
) {
315 case SHADER_OPCODE_TEX
:
316 case SHADER_OPCODE_TXL
:
317 if (inst
->shadow_compare
) {
318 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
319 assert(inst
->mlen
== 3);
321 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
322 assert(inst
->mlen
== 2);
325 case SHADER_OPCODE_TXD
:
326 /* There is no sample_d_c message; comparisons are done manually. */
327 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
328 assert(inst
->mlen
== 4);
330 case SHADER_OPCODE_TXF
:
331 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
332 assert(inst
->mlen
== 2);
334 case SHADER_OPCODE_TXS
:
335 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
336 assert(inst
->mlen
== 2);
339 assert(!"should not get here: invalid vec4 texture opcode");
344 assert(msg_type
!= -1);
346 /* Load the message header if present. If there's a texture offset, we need
347 * to set it up explicitly and load the offset bitfield. Otherwise, we can
348 * use an implied move from g0 to the first message register.
350 if (inst
->header_present
) {
351 if (brw
->gen
< 6 && !inst
->texture_offset
) {
352 /* Set up an implied move from g0 to the MRF. */
353 src
= brw_vec8_grf(0, 0);
355 struct brw_reg header
=
356 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
358 /* Explicitly set up the message header by copying g0 to the MRF. */
359 brw_push_insn_state(p
);
360 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
361 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
363 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
365 if (inst
->texture_offset
) {
366 /* Set the texel offset bits in DWord 2. */
367 brw_MOV(p
, get_element_ud(header
, 2),
368 brw_imm_ud(inst
->texture_offset
));
371 if (inst
->sampler
>= 16) {
372 /* The "Sampler Index" field can only store values between 0 and 15.
373 * However, we can add an offset to the "Sampler State Pointer"
374 * field, effectively selecting a different set of 16 samplers.
376 * The "Sampler State Pointer" needs to be aligned to a 32-byte
377 * offset, and each sampler state is only 16-bytes, so we can't
378 * exclusively use the offset - we have to use both.
380 assert(brw
->is_haswell
); /* field only exists on Haswell */
382 get_element_ud(header
, 3),
383 get_element_ud(brw_vec8_grf(0, 0), 3),
384 brw_imm_ud(16 * (inst
->sampler
/ 16) *
385 sizeof(gen7_sampler_state
)));
387 brw_pop_insn_state(p
);
391 uint32_t return_format
;
394 case BRW_REGISTER_TYPE_D
:
395 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
397 case BRW_REGISTER_TYPE_UD
:
398 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
401 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
405 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
406 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
407 ? prog_data
->base
.binding_table
.gather_texture_start
408 : prog_data
->base
.binding_table
.texture_start
) + inst
->sampler
;
417 1, /* response length */
419 inst
->header_present
,
420 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
423 brw_mark_surface_used(&prog_data
->base
, surface_index
);
427 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
430 brw_null_reg(), /* dest */
431 inst
->base_mrf
, /* starting mrf reg nr */
432 brw_vec8_grf(0, 0), /* src */
433 inst
->urb_write_flags
,
435 0, /* response len */
436 inst
->offset
, /* urb destination offset */
437 BRW_URB_SWIZZLE_INTERLEAVE
);
441 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
443 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
445 brw_null_reg(), /* dest */
446 inst
->base_mrf
, /* starting mrf reg nr */
448 inst
->urb_write_flags
,
450 0, /* response len */
451 inst
->offset
, /* urb destination offset */
452 BRW_URB_SWIZZLE_INTERLEAVE
);
456 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
458 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
460 brw_null_reg(), /* dest */
461 inst
->base_mrf
, /* starting mrf reg nr */
465 0, /* response len */
466 0, /* urb destination offset */
467 BRW_URB_SWIZZLE_INTERLEAVE
);
471 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
475 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
478 * Slot 0 Offset. This field, after adding to the Global Offset field
479 * in the message descriptor, specifies the offset (in 256-bit units)
480 * from the start of the URB entry, as referenced by URB Handle 0, at
481 * which the data will be accessed.
483 * Similar text describes DWORD M0.4, which is slot 1 offset.
485 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
486 * of the register for geometry shader invocations 0 and 1) by the
487 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
489 * We can do this with the following EU instruction:
491 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
493 brw_push_insn_state(p
);
494 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
495 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
496 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
498 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
499 brw_pop_insn_state(p
);
503 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
506 brw_push_insn_state(p
);
507 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
508 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
510 /* If we think of the src and dst registers as composed of 8 DWORDs each,
511 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
512 * them to WORDs, and then pack them into DWORD 2 of dst.
514 * It's easier to get the EU to do this if we think of the src and dst
515 * registers as composed of 16 WORDS each; then, we want to pick up the
516 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
519 * We can do that by the following EU instruction:
521 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
523 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
524 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
525 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
526 brw_pop_insn_state(p
);
530 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
533 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
535 brw_push_insn_state(p
);
536 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
537 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
538 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
539 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
540 brw_pop_insn_state(p
);
544 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
546 /* We want to left shift just DWORD 4 (the x component belonging to the
547 * second geometry shader invocation) by 4 bits. So generate the
550 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
552 dst
= suboffset(vec1(dst
), 4);
553 brw_push_insn_state(p
);
554 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
555 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
556 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
557 brw_pop_insn_state(p
);
561 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
564 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
567 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
569 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
570 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
571 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
572 * channel enable to determine the final channel enable. For the
573 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
574 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
575 * in the writeback message. For the URB_WRITE_OWORD &
576 * URB_WRITE_HWORD messages, when final channel enable is 1 it
577 * indicates that Vertex 1 DATA [3] will be written to the surface.
579 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
580 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
582 * 14 Vertex 1 DATA [2] Channel Mask
583 * 13 Vertex 1 DATA [1] Channel Mask
584 * 12 Vertex 1 DATA [0] Channel Mask
585 * 11 Vertex 0 DATA [3] Channel Mask
586 * 10 Vertex 0 DATA [2] Channel Mask
587 * 9 Vertex 0 DATA [1] Channel Mask
588 * 8 Vertex 0 DATA [0] Channel Mask
590 * (This is from a section of the PRM that is agnostic to the particular
591 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
592 * geometry shader invocations 0 and 1, respectively). Since we have the
593 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
594 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
595 * DWORD 4, we just need to OR them together and store the result in bits
598 * It's easier to get the EU to do this if we think of the src and dst
599 * registers as composed of 32 bytes each; then, we want to pick up the
600 * contents of bytes 0 and 16 from src, OR them together, and store them in
603 * We can do that by the following EU instruction:
605 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
607 * Note: this relies on the source register having zeros in (a) bits 7:4 of
608 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
609 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
610 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
611 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
612 * contain valid channel mask values (which are in the range 0x0-0xf).
614 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
615 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
616 brw_push_insn_state(p
);
617 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
618 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
619 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
620 brw_pop_insn_state(p
);
624 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
626 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
627 * and store into dst.0 & dst.4. So generate the instruction:
629 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
631 brw_push_insn_state(p
);
632 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
633 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
634 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
635 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
636 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
637 brw_pop_insn_state(p
);
641 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
642 struct brw_reg index
)
644 int second_vertex_offset
;
647 second_vertex_offset
= 1;
649 second_vertex_offset
= 16;
651 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
653 /* Set up M1 (message payload). Only the block offsets in M1.0 and
654 * M1.4 are used, and the rest are ignored.
656 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
657 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
658 struct brw_reg index_0
= suboffset(vec1(index
), 0);
659 struct brw_reg index_4
= suboffset(vec1(index
), 4);
661 brw_push_insn_state(p
);
662 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
663 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
665 brw_MOV(p
, m1_0
, index_0
);
667 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
668 index_4
.dw1
.ud
+= second_vertex_offset
;
669 brw_MOV(p
, m1_4
, index_4
);
671 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
674 brw_pop_insn_state(p
);
678 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
681 brw_push_insn_state(p
);
682 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
683 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
685 struct brw_reg flags
= brw_flag_reg(0, 0);
686 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
687 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
689 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
690 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
691 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
693 brw_pop_insn_state(p
);
697 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
699 struct brw_reg index
)
701 struct brw_reg header
= brw_vec8_grf(0, 0);
703 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
705 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
711 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
712 else if (brw
->gen
== 5 || brw
->is_g4x
)
713 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
715 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
717 /* Each of the 8 channel enables is considered for whether each
720 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
721 brw_set_dest(p
, send
, dst
);
722 brw_set_src0(p
, send
, header
);
724 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
725 brw_set_dp_read_message(p
, send
,
726 255, /* binding table index: stateless access */
727 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
729 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
731 true, /* header_present */
736 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
739 struct brw_reg index
)
741 struct brw_reg header
= brw_vec8_grf(0, 0);
744 /* If the instruction is predicated, we'll predicate the send, not
747 brw_set_default_predicate_control(p
, false);
749 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
751 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
755 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
756 retype(src
, BRW_REGISTER_TYPE_D
));
761 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
762 else if (brw
->gen
== 6)
763 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
765 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
767 brw_set_default_predicate_control(p
, inst
->predicate
);
769 /* Pre-gen6, we have to specify write commits to ensure ordering
770 * between reads and writes within a thread. Afterwards, that's
771 * guaranteed and write commits only matter for inter-thread
775 write_commit
= false;
777 /* The visitor set up our destination register to be g0. This
778 * means that when the next read comes along, we will end up
779 * reading from g0 and causing a block on the write commit. For
780 * write-after-read, we are relying on the value of the previous
781 * read being used (and thus blocking on completion) before our
782 * write is executed. This means we have to be careful in
783 * instruction scheduling to not violate this assumption.
788 /* Each of the 8 channel enables is considered for whether each
791 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
792 brw_set_dest(p
, send
, dst
);
793 brw_set_src0(p
, send
, header
);
795 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
796 brw_set_dp_write_message(p
, send
,
797 255, /* binding table index: stateless access */
798 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
801 true, /* header present */
802 false, /* not a render target write */
803 write_commit
, /* rlen */
809 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
811 struct brw_reg index
,
812 struct brw_reg offset
)
814 assert(brw
->gen
<= 7);
815 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
816 index
.type
== BRW_REGISTER_TYPE_UD
);
817 uint32_t surf_index
= index
.dw1
.ud
;
819 struct brw_reg header
= brw_vec8_grf(0, 0);
821 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
823 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
829 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
830 else if (brw
->gen
== 5 || brw
->is_g4x
)
831 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
833 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
835 /* Each of the 8 channel enables is considered for whether each
838 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
839 brw_set_dest(p
, send
, dst
);
840 brw_set_src0(p
, send
, header
);
842 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
843 brw_set_dp_read_message(p
, send
,
845 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
847 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
849 true, /* header_present */
852 brw_mark_surface_used(&prog_data
->base
, surf_index
);
856 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
858 struct brw_reg surf_index
,
859 struct brw_reg offset
)
861 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
862 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
864 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
865 brw_set_dest(p
, insn
, dst
);
866 brw_set_src0(p
, insn
, offset
);
867 brw_set_sampler_message(p
, insn
,
869 0, /* LD message ignores sampler unit */
870 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
873 false, /* no header */
874 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
877 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
881 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
883 struct brw_reg atomic_op
,
884 struct brw_reg surf_index
)
886 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
887 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
888 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
889 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
891 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
892 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
895 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
899 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
901 struct brw_reg surf_index
)
903 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
904 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
906 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
910 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
914 * Generate assembly for a Vec4 IR instruction.
916 * \param instruction The Vec4 IR instruction to generate code for.
917 * \param dst The destination register.
918 * \param src An array of up to three source registers.
921 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
925 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
927 if (dst
.width
== BRW_WIDTH_4
) {
928 /* This happens in attribute fixups for "dual instanced" geometry
929 * shaders, since they use attributes that are vec4's. Since the exec
930 * width is only 4, it's essential that the caller set
931 * force_writemask_all in order to make sure the instruction is executed
932 * regardless of which channels are enabled.
934 assert(inst
->force_writemask_all
);
936 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
937 * the following register region restrictions (from Graphics BSpec:
938 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
939 * > Register Region Restrictions)
941 * 1. ExecSize must be greater than or equal to Width.
943 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
944 * to Width * HorzStride."
946 for (int i
= 0; i
< 3; i
++) {
947 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
948 src
[i
] = stride(src
[i
], 4, 4, 1);
952 switch (inst
->opcode
) {
954 brw_MOV(p
, dst
, src
[0]);
957 brw_ADD(p
, dst
, src
[0], src
[1]);
960 brw_MUL(p
, dst
, src
[0], src
[1]);
962 case BRW_OPCODE_MACH
:
963 brw_MACH(p
, dst
, src
[0], src
[1]);
967 assert(brw
->gen
>= 6);
968 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
972 brw_FRC(p
, dst
, src
[0]);
974 case BRW_OPCODE_RNDD
:
975 brw_RNDD(p
, dst
, src
[0]);
977 case BRW_OPCODE_RNDE
:
978 brw_RNDE(p
, dst
, src
[0]);
980 case BRW_OPCODE_RNDZ
:
981 brw_RNDZ(p
, dst
, src
[0]);
985 brw_AND(p
, dst
, src
[0], src
[1]);
988 brw_OR(p
, dst
, src
[0], src
[1]);
991 brw_XOR(p
, dst
, src
[0], src
[1]);
994 brw_NOT(p
, dst
, src
[0]);
997 brw_ASR(p
, dst
, src
[0], src
[1]);
1000 brw_SHR(p
, dst
, src
[0], src
[1]);
1002 case BRW_OPCODE_SHL
:
1003 brw_SHL(p
, dst
, src
[0], src
[1]);
1006 case BRW_OPCODE_CMP
:
1007 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1009 case BRW_OPCODE_SEL
:
1010 brw_SEL(p
, dst
, src
[0], src
[1]);
1013 case BRW_OPCODE_DPH
:
1014 brw_DPH(p
, dst
, src
[0], src
[1]);
1017 case BRW_OPCODE_DP4
:
1018 brw_DP4(p
, dst
, src
[0], src
[1]);
1021 case BRW_OPCODE_DP3
:
1022 brw_DP3(p
, dst
, src
[0], src
[1]);
1025 case BRW_OPCODE_DP2
:
1026 brw_DP2(p
, dst
, src
[0], src
[1]);
1029 case BRW_OPCODE_F32TO16
:
1030 assert(brw
->gen
>= 7);
1031 brw_F32TO16(p
, dst
, src
[0]);
1034 case BRW_OPCODE_F16TO32
:
1035 assert(brw
->gen
>= 7);
1036 brw_F16TO32(p
, dst
, src
[0]);
1039 case BRW_OPCODE_LRP
:
1040 assert(brw
->gen
>= 6);
1041 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1044 case BRW_OPCODE_BFREV
:
1045 assert(brw
->gen
>= 7);
1046 /* BFREV only supports UD type for src and dst. */
1047 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1048 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1050 case BRW_OPCODE_FBH
:
1051 assert(brw
->gen
>= 7);
1052 /* FBH only supports UD type for dst. */
1053 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1055 case BRW_OPCODE_FBL
:
1056 assert(brw
->gen
>= 7);
1057 /* FBL only supports UD type for dst. */
1058 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1060 case BRW_OPCODE_CBIT
:
1061 assert(brw
->gen
>= 7);
1062 /* CBIT only supports UD type for dst. */
1063 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1065 case BRW_OPCODE_ADDC
:
1066 assert(brw
->gen
>= 7);
1067 brw_ADDC(p
, dst
, src
[0], src
[1]);
1069 case BRW_OPCODE_SUBB
:
1070 assert(brw
->gen
>= 7);
1071 brw_SUBB(p
, dst
, src
[0], src
[1]);
1073 case BRW_OPCODE_MAC
:
1074 brw_MAC(p
, dst
, src
[0], src
[1]);
1077 case BRW_OPCODE_BFE
:
1078 assert(brw
->gen
>= 7);
1079 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1082 case BRW_OPCODE_BFI1
:
1083 assert(brw
->gen
>= 7);
1084 brw_BFI1(p
, dst
, src
[0], src
[1]);
1086 case BRW_OPCODE_BFI2
:
1087 assert(brw
->gen
>= 7);
1088 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1092 if (inst
->src
[0].file
!= BAD_FILE
) {
1093 /* The instruction has an embedded compare (only allowed on gen6) */
1094 assert(brw
->gen
== 6);
1095 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1097 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1098 brw_inst
->header
.predicate_control
= inst
->predicate
;
1102 case BRW_OPCODE_ELSE
:
1105 case BRW_OPCODE_ENDIF
:
1110 brw_DO(p
, BRW_EXECUTE_8
);
1113 case BRW_OPCODE_BREAK
:
1115 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1117 case BRW_OPCODE_CONTINUE
:
1118 /* FINISHME: We need to write the loop instruction support still. */
1123 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1126 case BRW_OPCODE_WHILE
:
1130 case SHADER_OPCODE_RCP
:
1131 case SHADER_OPCODE_RSQ
:
1132 case SHADER_OPCODE_SQRT
:
1133 case SHADER_OPCODE_EXP2
:
1134 case SHADER_OPCODE_LOG2
:
1135 case SHADER_OPCODE_SIN
:
1136 case SHADER_OPCODE_COS
:
1137 if (brw
->gen
>= 7) {
1138 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1140 } else if (brw
->gen
== 6) {
1141 generate_math1_gen6(inst
, dst
, src
[0]);
1143 generate_math1_gen4(inst
, dst
, src
[0]);
1147 case SHADER_OPCODE_POW
:
1148 case SHADER_OPCODE_INT_QUOTIENT
:
1149 case SHADER_OPCODE_INT_REMAINDER
:
1150 if (brw
->gen
>= 7) {
1151 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1152 } else if (brw
->gen
== 6) {
1153 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1155 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1159 case SHADER_OPCODE_TEX
:
1160 case SHADER_OPCODE_TXD
:
1161 case SHADER_OPCODE_TXF
:
1162 case SHADER_OPCODE_TXF_CMS
:
1163 case SHADER_OPCODE_TXF_MCS
:
1164 case SHADER_OPCODE_TXL
:
1165 case SHADER_OPCODE_TXS
:
1166 case SHADER_OPCODE_TG4
:
1167 case SHADER_OPCODE_TG4_OFFSET
:
1168 generate_tex(inst
, dst
, src
[0]);
1171 case VS_OPCODE_URB_WRITE
:
1172 generate_vs_urb_write(inst
);
1175 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1176 generate_scratch_read(inst
, dst
, src
[0]);
1179 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1180 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1183 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1184 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1187 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1188 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1191 case GS_OPCODE_URB_WRITE
:
1192 generate_gs_urb_write(inst
);
1195 case GS_OPCODE_THREAD_END
:
1196 generate_gs_thread_end(inst
);
1199 case GS_OPCODE_SET_WRITE_OFFSET
:
1200 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1203 case GS_OPCODE_SET_VERTEX_COUNT
:
1204 generate_gs_set_vertex_count(dst
, src
[0]);
1207 case GS_OPCODE_SET_DWORD_2_IMMED
:
1208 generate_gs_set_dword_2_immed(dst
, src
[0]);
1211 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1212 generate_gs_prepare_channel_masks(dst
);
1215 case GS_OPCODE_SET_CHANNEL_MASKS
:
1216 generate_gs_set_channel_masks(dst
, src
[0]);
1219 case GS_OPCODE_GET_INSTANCE_ID
:
1220 generate_gs_get_instance_id(dst
);
1223 case SHADER_OPCODE_SHADER_TIME_ADD
:
1224 brw_shader_time_add(p
, src
[0],
1225 prog_data
->base
.binding_table
.shader_time_start
);
1226 brw_mark_surface_used(&prog_data
->base
,
1227 prog_data
->base
.binding_table
.shader_time_start
);
1230 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1231 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1234 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1235 generate_untyped_surface_read(inst
, dst
, src
[0]);
1238 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1239 generate_unpack_flags(inst
, dst
);
1243 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1244 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1245 opcode_descs
[inst
->opcode
].name
);
1247 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1254 vec4_generator::generate_code(exec_list
*instructions
)
1256 struct annotation_info annotation
;
1257 memset(&annotation
, 0, sizeof(annotation
));
1260 if (unlikely(debug_flag
))
1261 cfg
= new(mem_ctx
) cfg_t(instructions
);
1263 foreach_list(node
, instructions
) {
1264 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1265 struct brw_reg src
[3], dst
;
1267 if (unlikely(debug_flag
))
1268 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1270 for (unsigned int i
= 0; i
< 3; i
++) {
1271 src
[i
] = inst
->get_src(this->prog_data
, i
);
1273 dst
= inst
->get_dst();
1275 brw_set_default_predicate_control(p
, inst
->predicate
);
1276 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1277 brw_set_default_saturate(p
, inst
->saturate
);
1278 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1279 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1281 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1283 generate_vec4_instruction(inst
, dst
, src
);
1285 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1286 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1287 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1288 "emitting more than 1 instruction");
1290 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
1292 if (inst
->conditional_mod
)
1293 last
->header
.destreg__conditionalmod
= inst
->conditional_mod
;
1294 if (inst
->no_dd_clear
)
1295 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
1296 if (inst
->no_dd_check
)
1297 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
1302 annotation_finalize(&annotation
, p
->next_insn_offset
);
1304 int before_size
= p
->next_insn_offset
;
1305 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1306 int after_size
= p
->next_insn_offset
;
1308 if (unlikely(debug_flag
)) {
1310 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1311 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1314 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1316 fprintf(stderr
, "vec4 shader: %d instructions. Compacted %d to %d"
1317 " bytes (%.0f%%)\n",
1318 before_size
/ 16, before_size
, after_size
,
1319 100.0f
* (before_size
- after_size
) / before_size
);
1321 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
1322 brw
, prog
, brw_disassemble
);
1323 ralloc_free(annotation
.ann
);
1328 vec4_generator::generate_assembly(exec_list
*instructions
,
1329 unsigned *assembly_size
)
1331 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1332 generate_code(instructions
);
1334 return brw_get_program(p
, assembly_size
);
1337 } /* namespace brw */