1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 assert(!"not reached");
64 brw_reg
= brw_null_reg();
71 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
73 struct brw_reg brw_reg
;
75 switch (src
[i
].file
) {
77 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
78 brw_reg
= retype(brw_reg
, src
[i
].type
);
79 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
81 brw_reg
= brw_abs(brw_reg
);
83 brw_reg
= negate(brw_reg
);
87 switch (src
[i
].type
) {
88 case BRW_REGISTER_TYPE_F
:
89 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
91 case BRW_REGISTER_TYPE_D
:
92 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
94 case BRW_REGISTER_TYPE_UD
:
95 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
98 assert(!"not reached");
99 brw_reg
= brw_null_reg();
105 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
106 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
107 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
109 brw_reg
= retype(brw_reg
, src
[i
].type
);
110 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
112 brw_reg
= brw_abs(brw_reg
);
114 brw_reg
= negate(brw_reg
);
116 /* This should have been moved to pull constants. */
117 assert(!src
[i
].reladdr
);
121 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
122 brw_reg
= src
[i
].fixed_hw_reg
;
126 /* Probably unused. */
127 brw_reg
= brw_null_reg();
131 assert(!"not reached");
132 brw_reg
= brw_null_reg();
139 vec4_generator::vec4_generator(struct brw_context
*brw
,
140 struct gl_shader_program
*shader_prog
,
141 struct gl_program
*prog
,
142 struct brw_vec4_prog_data
*prog_data
,
145 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
146 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
148 p
= rzalloc(mem_ctx
, struct brw_compile
);
149 brw_init_compile(brw
, p
, mem_ctx
);
152 vec4_generator::~vec4_generator()
157 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
163 brw_math_function(inst
->opcode
),
166 BRW_MATH_DATA_VECTOR
,
167 BRW_MATH_PRECISION_FULL
);
171 check_gen6_math_src_arg(struct brw_reg src
)
173 /* Source swizzles are ignored. */
176 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
180 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
185 /* Can't do writemask because math can't be align16. */
186 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
187 /* Source swizzles are ignored. */
188 check_gen6_math_src_arg(src0
);
189 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
190 check_gen6_math_src_arg(src1
);
192 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
193 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
194 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
198 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
203 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
206 * "Operand0[7]. For the INT DIV functions, this operand is the
209 * "Operand1[7]. For the INT DIV functions, this operand is the
212 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
213 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
214 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
216 brw_push_insn_state(p
);
217 brw_set_default_saturate(p
, false);
218 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
219 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
220 brw_pop_insn_state(p
);
224 brw_math_function(inst
->opcode
),
227 BRW_MATH_DATA_VECTOR
,
228 BRW_MATH_PRECISION_FULL
);
232 vec4_generator::generate_tex(vec4_instruction
*inst
,
239 switch (inst
->opcode
) {
240 case SHADER_OPCODE_TEX
:
241 case SHADER_OPCODE_TXL
:
242 if (inst
->shadow_compare
) {
243 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
245 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
248 case SHADER_OPCODE_TXD
:
249 if (inst
->shadow_compare
) {
250 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
251 assert(brw
->gen
>= 8 || brw
->is_haswell
);
252 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
254 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
257 case SHADER_OPCODE_TXF
:
258 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
260 case SHADER_OPCODE_TXF_CMS
:
262 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
264 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
266 case SHADER_OPCODE_TXF_MCS
:
267 assert(brw
->gen
>= 7);
268 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
270 case SHADER_OPCODE_TXS
:
271 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
273 case SHADER_OPCODE_TG4
:
274 if (inst
->shadow_compare
) {
275 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
277 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
280 case SHADER_OPCODE_TG4_OFFSET
:
281 if (inst
->shadow_compare
) {
282 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
284 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
288 assert(!"should not get here: invalid vec4 texture opcode");
292 switch (inst
->opcode
) {
293 case SHADER_OPCODE_TEX
:
294 case SHADER_OPCODE_TXL
:
295 if (inst
->shadow_compare
) {
296 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
297 assert(inst
->mlen
== 3);
299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
300 assert(inst
->mlen
== 2);
303 case SHADER_OPCODE_TXD
:
304 /* There is no sample_d_c message; comparisons are done manually. */
305 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
306 assert(inst
->mlen
== 4);
308 case SHADER_OPCODE_TXF
:
309 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
310 assert(inst
->mlen
== 2);
312 case SHADER_OPCODE_TXS
:
313 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
314 assert(inst
->mlen
== 2);
317 assert(!"should not get here: invalid vec4 texture opcode");
322 assert(msg_type
!= -1);
324 /* Load the message header if present. If there's a texture offset, we need
325 * to set it up explicitly and load the offset bitfield. Otherwise, we can
326 * use an implied move from g0 to the first message register.
328 if (inst
->header_present
) {
329 if (brw
->gen
< 6 && !inst
->texture_offset
) {
330 /* Set up an implied move from g0 to the MRF. */
331 src
= brw_vec8_grf(0, 0);
333 struct brw_reg header
=
334 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
336 /* Explicitly set up the message header by copying g0 to the MRF. */
337 brw_push_insn_state(p
);
338 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
339 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
341 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
343 if (inst
->texture_offset
) {
344 /* Set the texel offset bits in DWord 2. */
345 brw_MOV(p
, get_element_ud(header
, 2),
346 brw_imm_ud(inst
->texture_offset
));
349 if (inst
->sampler
>= 16) {
350 /* The "Sampler Index" field can only store values between 0 and 15.
351 * However, we can add an offset to the "Sampler State Pointer"
352 * field, effectively selecting a different set of 16 samplers.
354 * The "Sampler State Pointer" needs to be aligned to a 32-byte
355 * offset, and each sampler state is only 16-bytes, so we can't
356 * exclusively use the offset - we have to use both.
358 assert(brw
->gen
>= 8 || brw
->is_haswell
);
360 get_element_ud(header
, 3),
361 get_element_ud(brw_vec8_grf(0, 0), 3),
362 brw_imm_ud(16 * (inst
->sampler
/ 16) *
363 sizeof(gen7_sampler_state
)));
365 brw_pop_insn_state(p
);
369 uint32_t return_format
;
372 case BRW_REGISTER_TYPE_D
:
373 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
375 case BRW_REGISTER_TYPE_UD
:
376 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
379 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
383 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
384 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
385 ? prog_data
->base
.binding_table
.gather_texture_start
386 : prog_data
->base
.binding_table
.texture_start
) + inst
->sampler
;
395 1, /* response length */
397 inst
->header_present
,
398 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
401 brw_mark_surface_used(&prog_data
->base
, surface_index
);
405 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
408 brw_null_reg(), /* dest */
409 inst
->base_mrf
, /* starting mrf reg nr */
410 brw_vec8_grf(0, 0), /* src */
411 inst
->urb_write_flags
,
413 0, /* response len */
414 inst
->offset
, /* urb destination offset */
415 BRW_URB_SWIZZLE_INTERLEAVE
);
419 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
421 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
423 brw_null_reg(), /* dest */
424 inst
->base_mrf
, /* starting mrf reg nr */
426 inst
->urb_write_flags
,
428 0, /* response len */
429 inst
->offset
, /* urb destination offset */
430 BRW_URB_SWIZZLE_INTERLEAVE
);
434 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
436 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
438 brw_null_reg(), /* dest */
439 inst
->base_mrf
, /* starting mrf reg nr */
443 0, /* response len */
444 0, /* urb destination offset */
445 BRW_URB_SWIZZLE_INTERLEAVE
);
449 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
453 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
456 * Slot 0 Offset. This field, after adding to the Global Offset field
457 * in the message descriptor, specifies the offset (in 256-bit units)
458 * from the start of the URB entry, as referenced by URB Handle 0, at
459 * which the data will be accessed.
461 * Similar text describes DWORD M0.4, which is slot 1 offset.
463 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
464 * of the register for geometry shader invocations 0 and 1) by the
465 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
467 * We can do this with the following EU instruction:
469 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
471 brw_push_insn_state(p
);
472 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
473 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
474 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
476 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
477 brw_pop_insn_state(p
);
481 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
484 brw_push_insn_state(p
);
485 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
486 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
488 /* If we think of the src and dst registers as composed of 8 DWORDs each,
489 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
490 * them to WORDs, and then pack them into DWORD 2 of dst.
492 * It's easier to get the EU to do this if we think of the src and dst
493 * registers as composed of 16 WORDS each; then, we want to pick up the
494 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
497 * We can do that by the following EU instruction:
499 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
501 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
502 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
503 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
504 brw_pop_insn_state(p
);
508 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
511 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
513 brw_push_insn_state(p
);
514 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
515 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
516 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
517 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
518 brw_pop_insn_state(p
);
522 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
524 /* We want to left shift just DWORD 4 (the x component belonging to the
525 * second geometry shader invocation) by 4 bits. So generate the
528 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
530 dst
= suboffset(vec1(dst
), 4);
531 brw_push_insn_state(p
);
532 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
533 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
534 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
535 brw_pop_insn_state(p
);
539 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
542 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
545 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
547 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
548 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
549 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
550 * channel enable to determine the final channel enable. For the
551 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
552 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
553 * in the writeback message. For the URB_WRITE_OWORD &
554 * URB_WRITE_HWORD messages, when final channel enable is 1 it
555 * indicates that Vertex 1 DATA [3] will be written to the surface.
557 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
558 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
560 * 14 Vertex 1 DATA [2] Channel Mask
561 * 13 Vertex 1 DATA [1] Channel Mask
562 * 12 Vertex 1 DATA [0] Channel Mask
563 * 11 Vertex 0 DATA [3] Channel Mask
564 * 10 Vertex 0 DATA [2] Channel Mask
565 * 9 Vertex 0 DATA [1] Channel Mask
566 * 8 Vertex 0 DATA [0] Channel Mask
568 * (This is from a section of the PRM that is agnostic to the particular
569 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
570 * geometry shader invocations 0 and 1, respectively). Since we have the
571 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
572 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
573 * DWORD 4, we just need to OR them together and store the result in bits
576 * It's easier to get the EU to do this if we think of the src and dst
577 * registers as composed of 32 bytes each; then, we want to pick up the
578 * contents of bytes 0 and 16 from src, OR them together, and store them in
581 * We can do that by the following EU instruction:
583 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
585 * Note: this relies on the source register having zeros in (a) bits 7:4 of
586 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
587 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
588 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
589 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
590 * contain valid channel mask values (which are in the range 0x0-0xf).
592 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
593 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
594 brw_push_insn_state(p
);
595 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
596 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
597 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
598 brw_pop_insn_state(p
);
602 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
604 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
605 * and store into dst.0 & dst.4. So generate the instruction:
607 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
609 brw_push_insn_state(p
);
610 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
611 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
612 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
613 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
614 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
615 brw_pop_insn_state(p
);
619 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
620 struct brw_reg index
)
622 int second_vertex_offset
;
625 second_vertex_offset
= 1;
627 second_vertex_offset
= 16;
629 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
631 /* Set up M1 (message payload). Only the block offsets in M1.0 and
632 * M1.4 are used, and the rest are ignored.
634 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
635 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
636 struct brw_reg index_0
= suboffset(vec1(index
), 0);
637 struct brw_reg index_4
= suboffset(vec1(index
), 4);
639 brw_push_insn_state(p
);
640 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
641 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
643 brw_MOV(p
, m1_0
, index_0
);
645 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
646 index_4
.dw1
.ud
+= second_vertex_offset
;
647 brw_MOV(p
, m1_4
, index_4
);
649 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
652 brw_pop_insn_state(p
);
656 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
659 brw_push_insn_state(p
);
660 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
661 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
663 struct brw_reg flags
= brw_flag_reg(0, 0);
664 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
665 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
667 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
668 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
669 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
671 brw_pop_insn_state(p
);
675 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
677 struct brw_reg index
)
679 struct brw_reg header
= brw_vec8_grf(0, 0);
681 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
683 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
689 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
690 else if (brw
->gen
== 5 || brw
->is_g4x
)
691 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
693 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
695 /* Each of the 8 channel enables is considered for whether each
698 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
699 brw_set_dest(p
, send
, dst
);
700 brw_set_src0(p
, send
, header
);
702 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
703 brw_set_dp_read_message(p
, send
,
704 255, /* binding table index: stateless access */
705 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
707 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
709 true, /* header_present */
714 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
717 struct brw_reg index
)
719 struct brw_reg header
= brw_vec8_grf(0, 0);
722 /* If the instruction is predicated, we'll predicate the send, not
725 brw_set_default_predicate_control(p
, false);
727 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
729 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
733 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
734 retype(src
, BRW_REGISTER_TYPE_D
));
739 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
740 else if (brw
->gen
== 6)
741 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
743 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
745 brw_set_default_predicate_control(p
, inst
->predicate
);
747 /* Pre-gen6, we have to specify write commits to ensure ordering
748 * between reads and writes within a thread. Afterwards, that's
749 * guaranteed and write commits only matter for inter-thread
753 write_commit
= false;
755 /* The visitor set up our destination register to be g0. This
756 * means that when the next read comes along, we will end up
757 * reading from g0 and causing a block on the write commit. For
758 * write-after-read, we are relying on the value of the previous
759 * read being used (and thus blocking on completion) before our
760 * write is executed. This means we have to be careful in
761 * instruction scheduling to not violate this assumption.
766 /* Each of the 8 channel enables is considered for whether each
769 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
770 brw_set_dest(p
, send
, dst
);
771 brw_set_src0(p
, send
, header
);
773 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
774 brw_set_dp_write_message(p
, send
,
775 255, /* binding table index: stateless access */
776 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
779 true, /* header present */
780 false, /* not a render target write */
781 write_commit
, /* rlen */
787 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
789 struct brw_reg index
,
790 struct brw_reg offset
)
792 assert(brw
->gen
<= 7);
793 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
794 index
.type
== BRW_REGISTER_TYPE_UD
);
795 uint32_t surf_index
= index
.dw1
.ud
;
797 struct brw_reg header
= brw_vec8_grf(0, 0);
799 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
801 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
807 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
808 else if (brw
->gen
== 5 || brw
->is_g4x
)
809 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
811 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
813 /* Each of the 8 channel enables is considered for whether each
816 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
817 brw_set_dest(p
, send
, dst
);
818 brw_set_src0(p
, send
, header
);
820 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
821 brw_set_dp_read_message(p
, send
,
823 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
825 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
827 true, /* header_present */
830 brw_mark_surface_used(&prog_data
->base
, surf_index
);
834 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
836 struct brw_reg surf_index
,
837 struct brw_reg offset
)
839 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
840 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
842 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
843 brw_set_dest(p
, insn
, dst
);
844 brw_set_src0(p
, insn
, offset
);
845 brw_set_sampler_message(p
, insn
,
847 0, /* LD message ignores sampler unit */
848 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
851 false, /* no header */
852 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
855 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
859 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
861 struct brw_reg atomic_op
,
862 struct brw_reg surf_index
)
864 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
865 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
866 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
867 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
869 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
870 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
873 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
877 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
879 struct brw_reg surf_index
)
881 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
882 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
884 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
888 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
892 * Generate assembly for a Vec4 IR instruction.
894 * \param instruction The Vec4 IR instruction to generate code for.
895 * \param dst The destination register.
896 * \param src An array of up to three source registers.
899 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
903 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
905 if (dst
.width
== BRW_WIDTH_4
) {
906 /* This happens in attribute fixups for "dual instanced" geometry
907 * shaders, since they use attributes that are vec4's. Since the exec
908 * width is only 4, it's essential that the caller set
909 * force_writemask_all in order to make sure the instruction is executed
910 * regardless of which channels are enabled.
912 assert(inst
->force_writemask_all
);
914 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
915 * the following register region restrictions (from Graphics BSpec:
916 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
917 * > Register Region Restrictions)
919 * 1. ExecSize must be greater than or equal to Width.
921 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
922 * to Width * HorzStride."
924 for (int i
= 0; i
< 3; i
++) {
925 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
926 src
[i
] = stride(src
[i
], 4, 4, 1);
930 switch (inst
->opcode
) {
932 brw_MOV(p
, dst
, src
[0]);
935 brw_ADD(p
, dst
, src
[0], src
[1]);
938 brw_MUL(p
, dst
, src
[0], src
[1]);
940 case BRW_OPCODE_MACH
:
941 brw_MACH(p
, dst
, src
[0], src
[1]);
945 assert(brw
->gen
>= 6);
946 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
950 brw_FRC(p
, dst
, src
[0]);
952 case BRW_OPCODE_RNDD
:
953 brw_RNDD(p
, dst
, src
[0]);
955 case BRW_OPCODE_RNDE
:
956 brw_RNDE(p
, dst
, src
[0]);
958 case BRW_OPCODE_RNDZ
:
959 brw_RNDZ(p
, dst
, src
[0]);
963 brw_AND(p
, dst
, src
[0], src
[1]);
966 brw_OR(p
, dst
, src
[0], src
[1]);
969 brw_XOR(p
, dst
, src
[0], src
[1]);
972 brw_NOT(p
, dst
, src
[0]);
975 brw_ASR(p
, dst
, src
[0], src
[1]);
978 brw_SHR(p
, dst
, src
[0], src
[1]);
981 brw_SHL(p
, dst
, src
[0], src
[1]);
985 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
988 brw_SEL(p
, dst
, src
[0], src
[1]);
992 brw_DPH(p
, dst
, src
[0], src
[1]);
996 brw_DP4(p
, dst
, src
[0], src
[1]);
1000 brw_DP3(p
, dst
, src
[0], src
[1]);
1003 case BRW_OPCODE_DP2
:
1004 brw_DP2(p
, dst
, src
[0], src
[1]);
1007 case BRW_OPCODE_F32TO16
:
1008 assert(brw
->gen
>= 7);
1009 brw_F32TO16(p
, dst
, src
[0]);
1012 case BRW_OPCODE_F16TO32
:
1013 assert(brw
->gen
>= 7);
1014 brw_F16TO32(p
, dst
, src
[0]);
1017 case BRW_OPCODE_LRP
:
1018 assert(brw
->gen
>= 6);
1019 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1022 case BRW_OPCODE_BFREV
:
1023 assert(brw
->gen
>= 7);
1024 /* BFREV only supports UD type for src and dst. */
1025 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1026 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1028 case BRW_OPCODE_FBH
:
1029 assert(brw
->gen
>= 7);
1030 /* FBH only supports UD type for dst. */
1031 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1033 case BRW_OPCODE_FBL
:
1034 assert(brw
->gen
>= 7);
1035 /* FBL only supports UD type for dst. */
1036 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1038 case BRW_OPCODE_CBIT
:
1039 assert(brw
->gen
>= 7);
1040 /* CBIT only supports UD type for dst. */
1041 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1043 case BRW_OPCODE_ADDC
:
1044 assert(brw
->gen
>= 7);
1045 brw_ADDC(p
, dst
, src
[0], src
[1]);
1047 case BRW_OPCODE_SUBB
:
1048 assert(brw
->gen
>= 7);
1049 brw_SUBB(p
, dst
, src
[0], src
[1]);
1051 case BRW_OPCODE_MAC
:
1052 brw_MAC(p
, dst
, src
[0], src
[1]);
1055 case BRW_OPCODE_BFE
:
1056 assert(brw
->gen
>= 7);
1057 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1060 case BRW_OPCODE_BFI1
:
1061 assert(brw
->gen
>= 7);
1062 brw_BFI1(p
, dst
, src
[0], src
[1]);
1064 case BRW_OPCODE_BFI2
:
1065 assert(brw
->gen
>= 7);
1066 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1070 if (inst
->src
[0].file
!= BAD_FILE
) {
1071 /* The instruction has an embedded compare (only allowed on gen6) */
1072 assert(brw
->gen
== 6);
1073 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1075 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1076 brw_inst_set_pred_control(brw
, if_inst
, inst
->predicate
);
1080 case BRW_OPCODE_ELSE
:
1083 case BRW_OPCODE_ENDIF
:
1088 brw_DO(p
, BRW_EXECUTE_8
);
1091 case BRW_OPCODE_BREAK
:
1093 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1095 case BRW_OPCODE_CONTINUE
:
1096 /* FINISHME: We need to write the loop instruction support still. */
1101 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1104 case BRW_OPCODE_WHILE
:
1108 case SHADER_OPCODE_RCP
:
1109 case SHADER_OPCODE_RSQ
:
1110 case SHADER_OPCODE_SQRT
:
1111 case SHADER_OPCODE_EXP2
:
1112 case SHADER_OPCODE_LOG2
:
1113 case SHADER_OPCODE_SIN
:
1114 case SHADER_OPCODE_COS
:
1115 if (brw
->gen
>= 7) {
1116 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1118 } else if (brw
->gen
== 6) {
1119 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1121 generate_math1_gen4(inst
, dst
, src
[0]);
1125 case SHADER_OPCODE_POW
:
1126 case SHADER_OPCODE_INT_QUOTIENT
:
1127 case SHADER_OPCODE_INT_REMAINDER
:
1128 if (brw
->gen
>= 7) {
1129 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1130 } else if (brw
->gen
== 6) {
1131 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1133 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1137 case SHADER_OPCODE_TEX
:
1138 case SHADER_OPCODE_TXD
:
1139 case SHADER_OPCODE_TXF
:
1140 case SHADER_OPCODE_TXF_CMS
:
1141 case SHADER_OPCODE_TXF_MCS
:
1142 case SHADER_OPCODE_TXL
:
1143 case SHADER_OPCODE_TXS
:
1144 case SHADER_OPCODE_TG4
:
1145 case SHADER_OPCODE_TG4_OFFSET
:
1146 generate_tex(inst
, dst
, src
[0]);
1149 case VS_OPCODE_URB_WRITE
:
1150 generate_vs_urb_write(inst
);
1153 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1154 generate_scratch_read(inst
, dst
, src
[0]);
1157 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1158 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1161 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1162 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1165 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1166 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1169 case GS_OPCODE_URB_WRITE
:
1170 generate_gs_urb_write(inst
);
1173 case GS_OPCODE_THREAD_END
:
1174 generate_gs_thread_end(inst
);
1177 case GS_OPCODE_SET_WRITE_OFFSET
:
1178 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1181 case GS_OPCODE_SET_VERTEX_COUNT
:
1182 generate_gs_set_vertex_count(dst
, src
[0]);
1185 case GS_OPCODE_SET_DWORD_2_IMMED
:
1186 generate_gs_set_dword_2_immed(dst
, src
[0]);
1189 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1190 generate_gs_prepare_channel_masks(dst
);
1193 case GS_OPCODE_SET_CHANNEL_MASKS
:
1194 generate_gs_set_channel_masks(dst
, src
[0]);
1197 case GS_OPCODE_GET_INSTANCE_ID
:
1198 generate_gs_get_instance_id(dst
);
1201 case SHADER_OPCODE_SHADER_TIME_ADD
:
1202 brw_shader_time_add(p
, src
[0],
1203 prog_data
->base
.binding_table
.shader_time_start
);
1204 brw_mark_surface_used(&prog_data
->base
,
1205 prog_data
->base
.binding_table
.shader_time_start
);
1208 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1209 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1212 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1213 generate_untyped_surface_read(inst
, dst
, src
[0]);
1216 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1217 generate_unpack_flags(inst
, dst
);
1221 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1222 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1223 opcode_descs
[inst
->opcode
].name
);
1225 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1232 vec4_generator::generate_code(exec_list
*instructions
)
1234 struct annotation_info annotation
;
1235 memset(&annotation
, 0, sizeof(annotation
));
1238 if (unlikely(debug_flag
))
1239 cfg
= new(mem_ctx
) cfg_t(instructions
);
1241 foreach_in_list(vec4_instruction
, inst
, instructions
) {
1242 struct brw_reg src
[3], dst
;
1244 if (unlikely(debug_flag
))
1245 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1247 for (unsigned int i
= 0; i
< 3; i
++) {
1248 src
[i
] = inst
->get_src(this->prog_data
, i
);
1250 dst
= inst
->get_dst();
1252 brw_set_default_predicate_control(p
, inst
->predicate
);
1253 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1254 brw_set_default_saturate(p
, inst
->saturate
);
1255 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1256 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1258 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1260 generate_vec4_instruction(inst
, dst
, src
);
1262 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1263 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1264 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1265 "emitting more than 1 instruction");
1267 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1269 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1270 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1271 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1276 annotation_finalize(&annotation
, p
->next_insn_offset
);
1278 int before_size
= p
->next_insn_offset
;
1279 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1280 int after_size
= p
->next_insn_offset
;
1282 if (unlikely(debug_flag
)) {
1284 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1285 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1288 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1290 fprintf(stderr
, "vec4 shader: %d instructions. Compacted %d to %d"
1291 " bytes (%.0f%%)\n",
1292 before_size
/ 16, before_size
, after_size
,
1293 100.0f
* (before_size
- after_size
) / before_size
);
1295 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
1296 ralloc_free(annotation
.ann
);
1301 vec4_generator::generate_assembly(exec_list
*instructions
,
1302 unsigned *assembly_size
)
1304 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1305 generate_code(instructions
);
1307 return brw_get_program(p
, assembly_size
);
1310 } /* namespace brw */