1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 brw_reg
= dst
.fixed_hw_reg
;
57 brw_reg
= brw_null_reg();
61 assert(!"not reached");
62 brw_reg
= brw_null_reg();
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 assert(!"not reached");
97 brw_reg
= brw_null_reg();
103 brw_reg
= stride(brw_vec4_grf(prog_data
->dispatch_grf_start_reg
+
104 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
105 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
107 brw_reg
= retype(brw_reg
, src
[i
].type
);
108 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
110 brw_reg
= brw_abs(brw_reg
);
112 brw_reg
= negate(brw_reg
);
114 /* This should have been moved to pull constants. */
115 assert(!src
[i
].reladdr
);
119 brw_reg
= src
[i
].fixed_hw_reg
;
123 /* Probably unused. */
124 brw_reg
= brw_null_reg();
128 assert(!"not reached");
129 brw_reg
= brw_null_reg();
136 vec4_generator::vec4_generator(struct brw_context
*brw
,
137 struct gl_shader_program
*shader_prog
,
138 struct gl_program
*prog
,
139 struct brw_vec4_prog_data
*prog_data
,
142 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
143 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
145 shader
= shader_prog
? shader_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
] : NULL
;
147 p
= rzalloc(mem_ctx
, struct brw_compile
);
148 brw_init_compile(brw
, p
, mem_ctx
);
151 vec4_generator::~vec4_generator()
156 vec4_generator::mark_surface_used(unsigned surf_index
)
158 assert(surf_index
< BRW_MAX_VEC4_SURFACES
);
160 prog_data
->binding_table_size
= MAX2(prog_data
->binding_table_size
,
165 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
171 brw_math_function(inst
->opcode
),
174 BRW_MATH_DATA_VECTOR
,
175 BRW_MATH_PRECISION_FULL
);
179 check_gen6_math_src_arg(struct brw_reg src
)
181 /* Source swizzles are ignored. */
184 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
188 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
192 /* Can't do writemask because math can't be align16. */
193 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
194 check_gen6_math_src_arg(src
);
196 brw_set_access_mode(p
, BRW_ALIGN_1
);
199 brw_math_function(inst
->opcode
),
202 BRW_MATH_DATA_SCALAR
,
203 BRW_MATH_PRECISION_FULL
);
204 brw_set_access_mode(p
, BRW_ALIGN_16
);
208 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
215 brw_math_function(inst
->opcode
),
220 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
225 /* Can't do writemask because math can't be align16. */
226 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0
);
229 check_gen6_math_src_arg(src1
);
231 brw_set_access_mode(p
, BRW_ALIGN_1
);
234 brw_math_function(inst
->opcode
),
236 brw_set_access_mode(p
, BRW_ALIGN_16
);
240 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
248 * "Operand0[7]. For the INT DIV functions, this operand is the
251 * "Operand1[7]. For the INT DIV functions, this operand is the
254 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
255 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
256 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
258 brw_push_insn_state(p
);
259 brw_set_saturate(p
, false);
260 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
262 brw_pop_insn_state(p
);
266 brw_math_function(inst
->opcode
),
269 BRW_MATH_DATA_VECTOR
,
270 BRW_MATH_PRECISION_FULL
);
274 vec4_generator::generate_tex(vec4_instruction
*inst
,
281 switch (inst
->opcode
) {
282 case SHADER_OPCODE_TEX
:
283 case SHADER_OPCODE_TXL
:
284 if (inst
->shadow_compare
) {
285 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
287 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
290 case SHADER_OPCODE_TXD
:
291 if (inst
->shadow_compare
) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw
->is_haswell
);
294 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
296 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
299 case SHADER_OPCODE_TXF
:
300 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
302 case SHADER_OPCODE_TXF_MS
:
304 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
306 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
308 case SHADER_OPCODE_TXS
:
309 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
312 assert(!"should not get here: invalid VS texture opcode");
316 switch (inst
->opcode
) {
317 case SHADER_OPCODE_TEX
:
318 case SHADER_OPCODE_TXL
:
319 if (inst
->shadow_compare
) {
320 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
321 assert(inst
->mlen
== 3);
323 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
324 assert(inst
->mlen
== 2);
327 case SHADER_OPCODE_TXD
:
328 /* There is no sample_d_c message; comparisons are done manually. */
329 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
330 assert(inst
->mlen
== 4);
332 case SHADER_OPCODE_TXF
:
333 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
334 assert(inst
->mlen
== 2);
336 case SHADER_OPCODE_TXS
:
337 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
338 assert(inst
->mlen
== 2);
341 assert(!"should not get here: invalid VS texture opcode");
346 assert(msg_type
!= -1);
348 /* Load the message header if present. If there's a texture offset, we need
349 * to set it up explicitly and load the offset bitfield. Otherwise, we can
350 * use an implied move from g0 to the first message register.
352 if (inst
->texture_offset
) {
353 /* Explicitly set up the message header by copying g0 to the MRF. */
354 brw_push_insn_state(p
);
355 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
356 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
359 /* Then set the offset bits in DWord 2. */
360 brw_set_access_mode(p
, BRW_ALIGN_1
);
362 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
363 BRW_REGISTER_TYPE_UD
),
364 brw_imm_uw(inst
->texture_offset
));
365 brw_pop_insn_state(p
);
366 } else if (inst
->header_present
) {
367 /* Set up an implied move from g0 to the MRF. */
368 src
= brw_vec8_grf(0, 0);
371 uint32_t return_format
;
374 case BRW_REGISTER_TYPE_D
:
375 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
377 case BRW_REGISTER_TYPE_UD
:
378 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
381 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
389 SURF_INDEX_VEC4_TEXTURE(inst
->sampler
),
392 1, /* response length */
394 inst
->header_present
,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
398 mark_surface_used(SURF_INDEX_VEC4_TEXTURE(inst
->sampler
));
402 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
405 brw_null_reg(), /* dest */
406 inst
->base_mrf
, /* starting mrf reg nr */
407 brw_vec8_grf(0, 0), /* src */
408 inst
->urb_write_flags
,
410 0, /* response len */
411 inst
->offset
, /* urb destination offset */
412 BRW_URB_SWIZZLE_INTERLEAVE
);
416 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
418 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
420 brw_null_reg(), /* dest */
421 inst
->base_mrf
, /* starting mrf reg nr */
423 inst
->urb_write_flags
,
425 0, /* response len */
426 inst
->offset
, /* urb destination offset */
427 BRW_URB_SWIZZLE_INTERLEAVE
);
431 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
433 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
435 brw_null_reg(), /* dest */
436 inst
->base_mrf
, /* starting mrf reg nr */
440 0, /* response len */
441 0, /* urb destination offset */
442 BRW_URB_SWIZZLE_INTERLEAVE
);
446 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
450 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
453 * Slot 0 Offset. This field, after adding to the Global Offset field
454 * in the message descriptor, specifies the offset (in 256-bit units)
455 * from the start of the URB entry, as referenced by URB Handle 0, at
456 * which the data will be accessed.
458 * Similar text describes DWORD M0.4, which is slot 1 offset.
460 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
461 * of the register for geometry shader invocations 0 and 1) by the
462 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
464 * We can do this with the following EU instruction:
466 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
468 brw_push_insn_state(p
);
469 brw_set_access_mode(p
, BRW_ALIGN_1
);
470 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
471 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
473 brw_set_access_mode(p
, BRW_ALIGN_16
);
474 brw_pop_insn_state(p
);
478 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
481 brw_push_insn_state(p
);
482 brw_set_access_mode(p
, BRW_ALIGN_1
);
483 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
485 /* If we think of the src and dst registers as composed of 8 DWORDs each,
486 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
487 * them to WORDs, and then pack them into DWORD 2 of dst.
489 * It's easier to get the EU to do this if we think of the src and dst
490 * registers as composed of 16 WORDS each; then, we want to pick up the
491 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
494 * We can do that by the following EU instruction:
496 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
498 brw_MOV(p
, suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
499 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
500 brw_set_access_mode(p
, BRW_ALIGN_16
);
501 brw_pop_insn_state(p
);
505 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
508 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
510 brw_push_insn_state(p
);
511 brw_set_access_mode(p
, BRW_ALIGN_1
);
512 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
513 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
514 brw_set_access_mode(p
, BRW_ALIGN_16
);
515 brw_pop_insn_state(p
);
519 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
521 /* We want to left shift just DWORD 4 (the x component belonging to the
522 * second geometry shader invocation) by 4 bits. So generate the
525 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
527 dst
= suboffset(vec1(dst
), 4);
528 brw_push_insn_state(p
);
529 brw_set_access_mode(p
, BRW_ALIGN_1
);
530 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
531 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
532 brw_pop_insn_state(p
);
536 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
539 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
542 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
544 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
545 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
546 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
547 * channel enable to determine the final channel enable. For the
548 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
549 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
550 * in the writeback message. For the URB_WRITE_OWORD &
551 * URB_WRITE_HWORD messages, when final channel enable is 1 it
552 * indicates that Vertex 1 DATA [3] will be written to the surface.
554 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
555 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
557 * 14 Vertex 1 DATA [2] Channel Mask
558 * 13 Vertex 1 DATA [1] Channel Mask
559 * 12 Vertex 1 DATA [0] Channel Mask
560 * 11 Vertex 0 DATA [3] Channel Mask
561 * 10 Vertex 0 DATA [2] Channel Mask
562 * 9 Vertex 0 DATA [1] Channel Mask
563 * 8 Vertex 0 DATA [0] Channel Mask
565 * (This is from a section of the PRM that is agnostic to the particular
566 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
567 * geometry shader invocations 0 and 1, respectively). Since we have the
568 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
569 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
570 * DWORD 4, we just need to OR them together and store the result in bits
573 * It's easier to get the EU to do this if we think of the src and dst
574 * registers as composed of 32 bytes each; then, we want to pick up the
575 * contents of bytes 0 and 16 from src, OR them together, and store them in
578 * We can do that by the following EU instruction:
580 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
582 * Note: this relies on the source register having zeros in (a) bits 7:4 of
583 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
584 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
585 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
586 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
587 * contain valid channel mask values (which are in the range 0x0-0xf).
589 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
590 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
591 brw_push_insn_state(p
);
592 brw_set_access_mode(p
, BRW_ALIGN_1
);
593 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
594 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
595 brw_pop_insn_state(p
);
599 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
600 struct brw_reg index
)
602 int second_vertex_offset
;
605 second_vertex_offset
= 1;
607 second_vertex_offset
= 16;
609 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
611 /* Set up M1 (message payload). Only the block offsets in M1.0 and
612 * M1.4 are used, and the rest are ignored.
614 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
615 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
616 struct brw_reg index_0
= suboffset(vec1(index
), 0);
617 struct brw_reg index_4
= suboffset(vec1(index
), 4);
619 brw_push_insn_state(p
);
620 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
621 brw_set_access_mode(p
, BRW_ALIGN_1
);
623 brw_MOV(p
, m1_0
, index_0
);
625 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
626 index_4
.dw1
.ud
+= second_vertex_offset
;
627 brw_MOV(p
, m1_4
, index_4
);
629 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
632 brw_pop_insn_state(p
);
636 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
639 brw_push_insn_state(p
);
640 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
641 brw_set_access_mode(p
, BRW_ALIGN_1
);
643 struct brw_reg flags
= brw_flag_reg(0, 0);
644 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
645 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
647 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
648 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
649 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
651 brw_pop_insn_state(p
);
655 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
657 struct brw_reg index
)
659 struct brw_reg header
= brw_vec8_grf(0, 0);
661 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
663 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
669 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
670 else if (brw
->gen
== 5 || brw
->is_g4x
)
671 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
673 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
675 /* Each of the 8 channel enables is considered for whether each
678 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
679 brw_set_dest(p
, send
, dst
);
680 brw_set_src0(p
, send
, header
);
682 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
683 brw_set_dp_read_message(p
, send
,
684 255, /* binding table index: stateless access */
685 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
687 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
689 true, /* header_present */
694 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
697 struct brw_reg index
)
699 struct brw_reg header
= brw_vec8_grf(0, 0);
702 /* If the instruction is predicated, we'll predicate the send, not
705 brw_set_predicate_control(p
, false);
707 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
709 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
713 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
714 retype(src
, BRW_REGISTER_TYPE_D
));
719 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
720 else if (brw
->gen
== 6)
721 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
723 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
725 brw_set_predicate_control(p
, inst
->predicate
);
727 /* Pre-gen6, we have to specify write commits to ensure ordering
728 * between reads and writes within a thread. Afterwards, that's
729 * guaranteed and write commits only matter for inter-thread
733 write_commit
= false;
735 /* The visitor set up our destination register to be g0. This
736 * means that when the next read comes along, we will end up
737 * reading from g0 and causing a block on the write commit. For
738 * write-after-read, we are relying on the value of the previous
739 * read being used (and thus blocking on completion) before our
740 * write is executed. This means we have to be careful in
741 * instruction scheduling to not violate this assumption.
746 /* Each of the 8 channel enables is considered for whether each
749 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
750 brw_set_dest(p
, send
, dst
);
751 brw_set_src0(p
, send
, header
);
753 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
754 brw_set_dp_write_message(p
, send
,
755 255, /* binding table index: stateless access */
756 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
759 true, /* header present */
760 false, /* not a render target write */
761 write_commit
, /* rlen */
767 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
769 struct brw_reg index
,
770 struct brw_reg offset
)
772 assert(brw
->gen
<= 7);
773 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
774 index
.type
== BRW_REGISTER_TYPE_UD
);
775 uint32_t surf_index
= index
.dw1
.ud
;
777 struct brw_reg header
= brw_vec8_grf(0, 0);
779 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
781 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
787 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
788 else if (brw
->gen
== 5 || brw
->is_g4x
)
789 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
791 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
793 /* Each of the 8 channel enables is considered for whether each
796 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
797 brw_set_dest(p
, send
, dst
);
798 brw_set_src0(p
, send
, header
);
800 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
801 brw_set_dp_read_message(p
, send
,
803 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
805 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
807 true, /* header_present */
810 mark_surface_used(surf_index
);
814 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
816 struct brw_reg surf_index
,
817 struct brw_reg offset
)
819 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
820 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
822 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
823 brw_set_dest(p
, insn
, dst
);
824 brw_set_src0(p
, insn
, offset
);
825 brw_set_sampler_message(p
, insn
,
827 0, /* LD message ignores sampler unit */
828 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
831 false, /* no header */
832 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
835 mark_surface_used(surf_index
.dw1
.ud
);
839 * Generate assembly for a Vec4 IR instruction.
841 * \param instruction The Vec4 IR instruction to generate code for.
842 * \param dst The destination register.
843 * \param src An array of up to three source registers.
846 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
850 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
852 switch (inst
->opcode
) {
854 brw_MOV(p
, dst
, src
[0]);
857 brw_ADD(p
, dst
, src
[0], src
[1]);
860 brw_MUL(p
, dst
, src
[0], src
[1]);
862 case BRW_OPCODE_MACH
:
863 brw_set_acc_write_control(p
, 1);
864 brw_MACH(p
, dst
, src
[0], src
[1]);
865 brw_set_acc_write_control(p
, 0);
869 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
873 brw_FRC(p
, dst
, src
[0]);
875 case BRW_OPCODE_RNDD
:
876 brw_RNDD(p
, dst
, src
[0]);
878 case BRW_OPCODE_RNDE
:
879 brw_RNDE(p
, dst
, src
[0]);
881 case BRW_OPCODE_RNDZ
:
882 brw_RNDZ(p
, dst
, src
[0]);
886 brw_AND(p
, dst
, src
[0], src
[1]);
889 brw_OR(p
, dst
, src
[0], src
[1]);
892 brw_XOR(p
, dst
, src
[0], src
[1]);
895 brw_NOT(p
, dst
, src
[0]);
898 brw_ASR(p
, dst
, src
[0], src
[1]);
901 brw_SHR(p
, dst
, src
[0], src
[1]);
904 brw_SHL(p
, dst
, src
[0], src
[1]);
908 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
911 brw_SEL(p
, dst
, src
[0], src
[1]);
915 brw_DPH(p
, dst
, src
[0], src
[1]);
919 brw_DP4(p
, dst
, src
[0], src
[1]);
923 brw_DP3(p
, dst
, src
[0], src
[1]);
927 brw_DP2(p
, dst
, src
[0], src
[1]);
930 case BRW_OPCODE_F32TO16
:
931 brw_F32TO16(p
, dst
, src
[0]);
934 case BRW_OPCODE_F16TO32
:
935 brw_F16TO32(p
, dst
, src
[0]);
939 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
942 case BRW_OPCODE_BFREV
:
943 /* BFREV only supports UD type for src and dst. */
944 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
945 retype(src
[0], BRW_REGISTER_TYPE_UD
));
948 /* FBH only supports UD type for dst. */
949 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
952 /* FBL only supports UD type for dst. */
953 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
955 case BRW_OPCODE_CBIT
:
956 /* CBIT only supports UD type for dst. */
957 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
961 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
964 case BRW_OPCODE_BFI1
:
965 brw_BFI1(p
, dst
, src
[0], src
[1]);
967 case BRW_OPCODE_BFI2
:
968 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
972 if (inst
->src
[0].file
!= BAD_FILE
) {
973 /* The instruction has an embedded compare (only allowed on gen6) */
974 assert(brw
->gen
== 6);
975 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
977 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
978 brw_inst
->header
.predicate_control
= inst
->predicate
;
982 case BRW_OPCODE_ELSE
:
985 case BRW_OPCODE_ENDIF
:
990 brw_DO(p
, BRW_EXECUTE_8
);
993 case BRW_OPCODE_BREAK
:
995 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
997 case BRW_OPCODE_CONTINUE
:
998 /* FINISHME: We need to write the loop instruction support still. */
1003 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1006 case BRW_OPCODE_WHILE
:
1010 case SHADER_OPCODE_RCP
:
1011 case SHADER_OPCODE_RSQ
:
1012 case SHADER_OPCODE_SQRT
:
1013 case SHADER_OPCODE_EXP2
:
1014 case SHADER_OPCODE_LOG2
:
1015 case SHADER_OPCODE_SIN
:
1016 case SHADER_OPCODE_COS
:
1017 if (brw
->gen
== 6) {
1018 generate_math1_gen6(inst
, dst
, src
[0]);
1020 /* Also works for Gen7. */
1021 generate_math1_gen4(inst
, dst
, src
[0]);
1025 case SHADER_OPCODE_POW
:
1026 case SHADER_OPCODE_INT_QUOTIENT
:
1027 case SHADER_OPCODE_INT_REMAINDER
:
1028 if (brw
->gen
>= 7) {
1029 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1030 } else if (brw
->gen
== 6) {
1031 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1033 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1037 case SHADER_OPCODE_TEX
:
1038 case SHADER_OPCODE_TXD
:
1039 case SHADER_OPCODE_TXF
:
1040 case SHADER_OPCODE_TXF_MS
:
1041 case SHADER_OPCODE_TXL
:
1042 case SHADER_OPCODE_TXS
:
1043 generate_tex(inst
, dst
, src
[0]);
1046 case VS_OPCODE_URB_WRITE
:
1047 generate_vs_urb_write(inst
);
1050 case VS_OPCODE_SCRATCH_READ
:
1051 generate_scratch_read(inst
, dst
, src
[0]);
1054 case VS_OPCODE_SCRATCH_WRITE
:
1055 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1058 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1059 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1062 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1063 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1066 case GS_OPCODE_URB_WRITE
:
1067 generate_gs_urb_write(inst
);
1070 case GS_OPCODE_THREAD_END
:
1071 generate_gs_thread_end(inst
);
1074 case GS_OPCODE_SET_WRITE_OFFSET
:
1075 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1078 case GS_OPCODE_SET_VERTEX_COUNT
:
1079 generate_gs_set_vertex_count(dst
, src
[0]);
1082 case GS_OPCODE_SET_DWORD_2_IMMED
:
1083 generate_gs_set_dword_2_immed(dst
, src
[0]);
1086 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1087 generate_gs_prepare_channel_masks(dst
);
1090 case GS_OPCODE_SET_CHANNEL_MASKS
:
1091 generate_gs_set_channel_masks(dst
, src
[0]);
1094 case SHADER_OPCODE_SHADER_TIME_ADD
:
1095 brw_shader_time_add(p
, src
[0], SURF_INDEX_VEC4_SHADER_TIME
);
1096 mark_surface_used(SURF_INDEX_VEC4_SHADER_TIME
);
1099 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1100 generate_unpack_flags(inst
, dst
);
1104 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1105 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in VS\n",
1106 opcode_descs
[inst
->opcode
].name
);
1108 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in VS", inst
->opcode
);
1115 vec4_generator::generate_code(exec_list
*instructions
)
1117 int last_native_insn_offset
= 0;
1118 const char *last_annotation_string
= NULL
;
1119 const void *last_annotation_ir
= NULL
;
1121 if (unlikely(debug_flag
)) {
1123 printf("Native code for vertex shader %d:\n", shader_prog
->Name
);
1125 printf("Native code for vertex program %d:\n", prog
->Id
);
1129 foreach_list(node
, instructions
) {
1130 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1131 struct brw_reg src
[3], dst
;
1133 if (unlikely(debug_flag
)) {
1134 if (last_annotation_ir
!= inst
->ir
) {
1135 last_annotation_ir
= inst
->ir
;
1136 if (last_annotation_ir
) {
1139 ((ir_instruction
*) last_annotation_ir
)->print();
1141 const prog_instruction
*vpi
;
1142 vpi
= (const prog_instruction
*) inst
->ir
;
1143 printf("%d: ", (int)(vpi
- prog
->Instructions
));
1144 _mesa_fprint_instruction_opt(stdout
, vpi
, 0,
1145 PROG_PRINT_DEBUG
, NULL
);
1150 if (last_annotation_string
!= inst
->annotation
) {
1151 last_annotation_string
= inst
->annotation
;
1152 if (last_annotation_string
)
1153 printf(" %s\n", last_annotation_string
);
1157 for (unsigned int i
= 0; i
< 3; i
++) {
1158 src
[i
] = inst
->get_src(this->prog_data
, i
);
1160 dst
= inst
->get_dst();
1162 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1163 brw_set_predicate_control(p
, inst
->predicate
);
1164 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1165 brw_set_saturate(p
, inst
->saturate
);
1166 brw_set_mask_control(p
, inst
->force_writemask_all
);
1168 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1170 generate_vec4_instruction(inst
, dst
, src
);
1172 if (inst
->no_dd_clear
|| inst
->no_dd_check
) {
1173 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1174 !"no_dd_check or no_dd_clear set for IR emitting more "
1175 "than 1 instruction");
1177 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
1179 if (inst
->no_dd_clear
)
1180 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
1181 if (inst
->no_dd_check
)
1182 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
1185 if (unlikely(debug_flag
)) {
1186 brw_dump_compile(p
, stdout
,
1187 last_native_insn_offset
, p
->next_insn_offset
);
1190 last_native_insn_offset
= p
->next_insn_offset
;
1193 if (unlikely(debug_flag
)) {
1199 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1200 * emit issues, it doesn't get the jump distances into the output,
1201 * which is often something we want to debug. So this is here in
1202 * case you're doing that.
1204 if (0 && unlikely(debug_flag
)) {
1205 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1210 vec4_generator::generate_assembly(exec_list
*instructions
,
1211 unsigned *assembly_size
)
1213 brw_set_access_mode(p
, BRW_ALIGN_16
);
1214 generate_code(instructions
);
1215 return brw_get_program(p
, assembly_size
);
1218 } /* namespace brw */