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i965/vec4/fs: Count loops in shader debug
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 default:
96 unreachable("not reached");
97 }
98 break;
99
100 case UNIFORM:
101 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
102 (src[i].reg + src[i].reg_offset) / 2,
103 ((src[i].reg + src[i].reg_offset) % 2) * 4),
104 0, 4, 1);
105 brw_reg = retype(brw_reg, src[i].type);
106 brw_reg.dw1.bits.swizzle = src[i].swizzle;
107 if (src[i].abs)
108 brw_reg = brw_abs(brw_reg);
109 if (src[i].negate)
110 brw_reg = negate(brw_reg);
111
112 /* This should have been moved to pull constants. */
113 assert(!src[i].reladdr);
114 break;
115
116 case HW_REG:
117 assert(src[i].type == src[i].fixed_hw_reg.type);
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 unreachable("not reached");
128 }
129
130 return brw_reg;
131 }
132
133 vec4_generator::vec4_generator(struct brw_context *brw,
134 struct gl_shader_program *shader_prog,
135 struct gl_program *prog,
136 struct brw_vec4_prog_data *prog_data,
137 void *mem_ctx,
138 bool debug_flag)
139 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
140 mem_ctx(mem_ctx), debug_flag(debug_flag)
141 {
142 p = rzalloc(mem_ctx, struct brw_compile);
143 brw_init_compile(brw, p, mem_ctx);
144 }
145
146 vec4_generator::~vec4_generator()
147 {
148 }
149
150 void
151 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
152 struct brw_reg dst,
153 struct brw_reg src)
154 {
155 gen4_math(p,
156 dst,
157 brw_math_function(inst->opcode),
158 inst->base_mrf,
159 src,
160 BRW_MATH_DATA_VECTOR,
161 BRW_MATH_PRECISION_FULL);
162 }
163
164 static void
165 check_gen6_math_src_arg(struct brw_reg src)
166 {
167 /* Source swizzles are ignored. */
168 assert(!src.abs);
169 assert(!src.negate);
170 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
171 }
172
173 void
174 vec4_generator::generate_math_gen6(vec4_instruction *inst,
175 struct brw_reg dst,
176 struct brw_reg src0,
177 struct brw_reg src1)
178 {
179 /* Can't do writemask because math can't be align16. */
180 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0);
183 if (src1.file == BRW_GENERAL_REGISTER_FILE)
184 check_gen6_math_src_arg(src1);
185
186 brw_set_default_access_mode(p, BRW_ALIGN_1);
187 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
188 brw_set_default_access_mode(p, BRW_ALIGN_16);
189 }
190
191 void
192 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
193 struct brw_reg dst,
194 struct brw_reg src0,
195 struct brw_reg src1)
196 {
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
198 * "Message Payload":
199 *
200 * "Operand0[7]. For the INT DIV functions, this operand is the
201 * denominator."
202 * ...
203 * "Operand1[7]. For the INT DIV functions, this operand is the
204 * numerator."
205 */
206 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
207 struct brw_reg &op0 = is_int_div ? src1 : src0;
208 struct brw_reg &op1 = is_int_div ? src0 : src1;
209
210 brw_push_insn_state(p);
211 brw_set_default_saturate(p, false);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
214 brw_pop_insn_state(p);
215
216 gen4_math(p,
217 dst,
218 brw_math_function(inst->opcode),
219 inst->base_mrf,
220 op0,
221 BRW_MATH_DATA_VECTOR,
222 BRW_MATH_PRECISION_FULL);
223 }
224
225 void
226 vec4_generator::generate_tex(vec4_instruction *inst,
227 struct brw_reg dst,
228 struct brw_reg src,
229 struct brw_reg sampler_index)
230 {
231 int msg_type = -1;
232
233 if (brw->gen >= 5) {
234 switch (inst->opcode) {
235 case SHADER_OPCODE_TEX:
236 case SHADER_OPCODE_TXL:
237 if (inst->shadow_compare) {
238 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
239 } else {
240 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
241 }
242 break;
243 case SHADER_OPCODE_TXD:
244 if (inst->shadow_compare) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw->gen >= 8 || brw->is_haswell);
247 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
248 } else {
249 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
250 }
251 break;
252 case SHADER_OPCODE_TXF:
253 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
254 break;
255 case SHADER_OPCODE_TXF_CMS:
256 if (brw->gen >= 7)
257 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
258 else
259 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
260 break;
261 case SHADER_OPCODE_TXF_MCS:
262 assert(brw->gen >= 7);
263 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
264 break;
265 case SHADER_OPCODE_TXS:
266 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
267 break;
268 case SHADER_OPCODE_TG4:
269 if (inst->shadow_compare) {
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
271 } else {
272 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
273 }
274 break;
275 case SHADER_OPCODE_TG4_OFFSET:
276 if (inst->shadow_compare) {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
278 } else {
279 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
280 }
281 break;
282 default:
283 unreachable("should not get here: invalid vec4 texture opcode");
284 }
285 } else {
286 switch (inst->opcode) {
287 case SHADER_OPCODE_TEX:
288 case SHADER_OPCODE_TXL:
289 if (inst->shadow_compare) {
290 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
291 assert(inst->mlen == 3);
292 } else {
293 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
294 assert(inst->mlen == 2);
295 }
296 break;
297 case SHADER_OPCODE_TXD:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
300 assert(inst->mlen == 4);
301 break;
302 case SHADER_OPCODE_TXF:
303 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
304 assert(inst->mlen == 2);
305 break;
306 case SHADER_OPCODE_TXS:
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
308 assert(inst->mlen == 2);
309 break;
310 default:
311 unreachable("should not get here: invalid vec4 texture opcode");
312 }
313 }
314
315 assert(msg_type != -1);
316
317 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
318
319 /* Load the message header if present. If there's a texture offset, we need
320 * to set it up explicitly and load the offset bitfield. Otherwise, we can
321 * use an implied move from g0 to the first message register.
322 */
323 if (inst->header_present) {
324 if (brw->gen < 6 && !inst->texture_offset) {
325 /* Set up an implied move from g0 to the MRF. */
326 src = brw_vec8_grf(0, 0);
327 } else {
328 struct brw_reg header =
329 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
330
331 /* Explicitly set up the message header by copying g0 to the MRF. */
332 brw_push_insn_state(p);
333 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
334 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
335
336 brw_set_default_access_mode(p, BRW_ALIGN_1);
337
338 if (inst->texture_offset) {
339 /* Set the texel offset bits in DWord 2. */
340 brw_MOV(p, get_element_ud(header, 2),
341 brw_imm_ud(inst->texture_offset));
342 }
343
344 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
345 brw_pop_insn_state(p);
346 }
347 }
348
349 uint32_t return_format;
350
351 switch (dst.type) {
352 case BRW_REGISTER_TYPE_D:
353 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
354 break;
355 case BRW_REGISTER_TYPE_UD:
356 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
357 break;
358 default:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
360 break;
361 }
362
363 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
364 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
365 ? prog_data->base.binding_table.gather_texture_start
366 : prog_data->base.binding_table.texture_start;
367
368 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
369 uint32_t sampler = sampler_index.dw1.ud;
370
371 brw_SAMPLE(p,
372 dst,
373 inst->base_mrf,
374 src,
375 sampler + base_binding_table_index,
376 sampler % 16,
377 msg_type,
378 1, /* response length */
379 inst->mlen,
380 inst->header_present,
381 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
382 return_format);
383
384 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
385 } else {
386 /* Non-constant sampler index. */
387 /* Note: this clobbers `dst` as a temporary before emitting the send */
388
389 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
390 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
391
392 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
393
394 brw_push_insn_state(p);
395 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
396 brw_set_default_access_mode(p, BRW_ALIGN_1);
397
398 /* Some care required: `sampler` and `temp` may alias:
399 * addr = sampler & 0xff
400 * temp = (sampler << 8) & 0xf00
401 * addr = addr | temp
402 */
403 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
404 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
405 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
406 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
407 brw_OR(p, addr, addr, temp);
408
409 /* a0.0 |= <descriptor> */
410 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
411 brw_set_sampler_message(p, insn_or,
412 0 /* surface */,
413 0 /* sampler */,
414 msg_type,
415 1 /* rlen */,
416 inst->mlen /* mlen */,
417 inst->header_present /* header */,
418 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
419 return_format);
420 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
421 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
422 brw_set_src0(p, insn_or, addr);
423 brw_set_dest(p, insn_or, addr);
424
425
426 /* dst = send(offset, a0.0) */
427 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
428 brw_set_dest(p, insn_send, dst);
429 brw_set_src0(p, insn_send, src);
430 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
431
432 brw_pop_insn_state(p);
433
434 /* visitor knows more than we do about the surface limit required,
435 * so has already done marking.
436 */
437 }
438 }
439
440 void
441 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
442 {
443 brw_urb_WRITE(p,
444 brw_null_reg(), /* dest */
445 inst->base_mrf, /* starting mrf reg nr */
446 brw_vec8_grf(0, 0), /* src */
447 inst->urb_write_flags,
448 inst->mlen,
449 0, /* response len */
450 inst->offset, /* urb destination offset */
451 BRW_URB_SWIZZLE_INTERLEAVE);
452 }
453
454 void
455 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
456 {
457 struct brw_reg src = brw_message_reg(inst->base_mrf);
458 brw_urb_WRITE(p,
459 brw_null_reg(), /* dest */
460 inst->base_mrf, /* starting mrf reg nr */
461 src,
462 inst->urb_write_flags,
463 inst->mlen,
464 0, /* response len */
465 inst->offset, /* urb destination offset */
466 BRW_URB_SWIZZLE_INTERLEAVE);
467 }
468
469 void
470 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
471 {
472 struct brw_reg src = brw_message_reg(inst->base_mrf);
473 brw_urb_WRITE(p,
474 brw_null_reg(), /* dest */
475 inst->base_mrf, /* starting mrf reg nr */
476 src,
477 BRW_URB_WRITE_EOT,
478 brw->gen >= 8 ? 2 : 1,/* message len */
479 0, /* response len */
480 0, /* urb destination offset */
481 BRW_URB_SWIZZLE_INTERLEAVE);
482 }
483
484 void
485 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
486 struct brw_reg src0,
487 struct brw_reg src1)
488 {
489 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
490 * Header: M0.3):
491 *
492 * Slot 0 Offset. This field, after adding to the Global Offset field
493 * in the message descriptor, specifies the offset (in 256-bit units)
494 * from the start of the URB entry, as referenced by URB Handle 0, at
495 * which the data will be accessed.
496 *
497 * Similar text describes DWORD M0.4, which is slot 1 offset.
498 *
499 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
500 * of the register for geometry shader invocations 0 and 1) by the
501 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
502 *
503 * We can do this with the following EU instruction:
504 *
505 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
506 */
507 brw_push_insn_state(p);
508 brw_set_default_access_mode(p, BRW_ALIGN_1);
509 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
510 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
511 src1);
512 brw_set_default_access_mode(p, BRW_ALIGN_16);
513 brw_pop_insn_state(p);
514 }
515
516 void
517 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
518 struct brw_reg src)
519 {
520 brw_push_insn_state(p);
521 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
522
523 if (brw->gen >= 8) {
524 /* Move the vertex count into the second MRF for the EOT write. */
525 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
526 src);
527 } else {
528 /* If we think of the src and dst registers as composed of 8 DWORDs each,
529 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
530 * them to WORDs, and then pack them into DWORD 2 of dst.
531 *
532 * It's easier to get the EU to do this if we think of the src and dst
533 * registers as composed of 16 WORDS each; then, we want to pick up the
534 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
535 * of dst.
536 *
537 * We can do that by the following EU instruction:
538 *
539 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
540 */
541 brw_set_default_access_mode(p, BRW_ALIGN_1);
542 brw_MOV(p,
543 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
544 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
545 brw_set_default_access_mode(p, BRW_ALIGN_16);
546 }
547 brw_pop_insn_state(p);
548 }
549
550 void
551 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
552 struct brw_reg src)
553 {
554 assert(src.file == BRW_IMMEDIATE_VALUE);
555
556 brw_push_insn_state(p);
557 brw_set_default_access_mode(p, BRW_ALIGN_1);
558 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
559 brw_MOV(p, suboffset(vec1(dst), 2), src);
560 brw_set_default_access_mode(p, BRW_ALIGN_16);
561 brw_pop_insn_state(p);
562 }
563
564 void
565 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
566 {
567 /* We want to left shift just DWORD 4 (the x component belonging to the
568 * second geometry shader invocation) by 4 bits. So generate the
569 * instruction:
570 *
571 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
572 */
573 dst = suboffset(vec1(dst), 4);
574 brw_push_insn_state(p);
575 brw_set_default_access_mode(p, BRW_ALIGN_1);
576 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
577 brw_SHL(p, dst, dst, brw_imm_ud(4));
578 brw_pop_insn_state(p);
579 }
580
581 void
582 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
583 struct brw_reg src)
584 {
585 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
586 * Header: M0.5):
587 *
588 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
589 *
590 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
591 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
592 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
593 * channel enable to determine the final channel enable. For the
594 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
595 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
596 * in the writeback message. For the URB_WRITE_OWORD &
597 * URB_WRITE_HWORD messages, when final channel enable is 1 it
598 * indicates that Vertex 1 DATA [3] will be written to the surface.
599 *
600 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
601 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
602 *
603 * 14 Vertex 1 DATA [2] Channel Mask
604 * 13 Vertex 1 DATA [1] Channel Mask
605 * 12 Vertex 1 DATA [0] Channel Mask
606 * 11 Vertex 0 DATA [3] Channel Mask
607 * 10 Vertex 0 DATA [2] Channel Mask
608 * 9 Vertex 0 DATA [1] Channel Mask
609 * 8 Vertex 0 DATA [0] Channel Mask
610 *
611 * (This is from a section of the PRM that is agnostic to the particular
612 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
613 * geometry shader invocations 0 and 1, respectively). Since we have the
614 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
615 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
616 * DWORD 4, we just need to OR them together and store the result in bits
617 * 15:8 of DWORD 5.
618 *
619 * It's easier to get the EU to do this if we think of the src and dst
620 * registers as composed of 32 bytes each; then, we want to pick up the
621 * contents of bytes 0 and 16 from src, OR them together, and store them in
622 * byte 21.
623 *
624 * We can do that by the following EU instruction:
625 *
626 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
627 *
628 * Note: this relies on the source register having zeros in (a) bits 7:4 of
629 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
630 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
631 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
632 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
633 * contain valid channel mask values (which are in the range 0x0-0xf).
634 */
635 dst = retype(dst, BRW_REGISTER_TYPE_UB);
636 src = retype(src, BRW_REGISTER_TYPE_UB);
637 brw_push_insn_state(p);
638 brw_set_default_access_mode(p, BRW_ALIGN_1);
639 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
640 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
641 brw_pop_insn_state(p);
642 }
643
644 void
645 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
646 {
647 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
648 * and store into dst.0 & dst.4. So generate the instruction:
649 *
650 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
651 */
652 brw_push_insn_state(p);
653 brw_set_default_access_mode(p, BRW_ALIGN_1);
654 dst = retype(dst, BRW_REGISTER_TYPE_UD);
655 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
656 brw_SHR(p, dst, stride(r0, 1, 4, 0),
657 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
658 brw_pop_insn_state(p);
659 }
660
661 void
662 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
663 struct brw_reg index)
664 {
665 int second_vertex_offset;
666
667 if (brw->gen >= 6)
668 second_vertex_offset = 1;
669 else
670 second_vertex_offset = 16;
671
672 m1 = retype(m1, BRW_REGISTER_TYPE_D);
673
674 /* Set up M1 (message payload). Only the block offsets in M1.0 and
675 * M1.4 are used, and the rest are ignored.
676 */
677 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
678 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
679 struct brw_reg index_0 = suboffset(vec1(index), 0);
680 struct brw_reg index_4 = suboffset(vec1(index), 4);
681
682 brw_push_insn_state(p);
683 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
684 brw_set_default_access_mode(p, BRW_ALIGN_1);
685
686 brw_MOV(p, m1_0, index_0);
687
688 if (index.file == BRW_IMMEDIATE_VALUE) {
689 index_4.dw1.ud += second_vertex_offset;
690 brw_MOV(p, m1_4, index_4);
691 } else {
692 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
693 }
694
695 brw_pop_insn_state(p);
696 }
697
698 void
699 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
700 struct brw_reg dst)
701 {
702 brw_push_insn_state(p);
703 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
704 brw_set_default_access_mode(p, BRW_ALIGN_1);
705
706 struct brw_reg flags = brw_flag_reg(0, 0);
707 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
708 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
709
710 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
711 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
712 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
713
714 brw_pop_insn_state(p);
715 }
716
717 void
718 vec4_generator::generate_scratch_read(vec4_instruction *inst,
719 struct brw_reg dst,
720 struct brw_reg index)
721 {
722 struct brw_reg header = brw_vec8_grf(0, 0);
723
724 gen6_resolve_implied_move(p, &header, inst->base_mrf);
725
726 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
727 index);
728
729 uint32_t msg_type;
730
731 if (brw->gen >= 6)
732 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
733 else if (brw->gen == 5 || brw->is_g4x)
734 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
735 else
736 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
737
738 /* Each of the 8 channel enables is considered for whether each
739 * dword is written.
740 */
741 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
742 brw_set_dest(p, send, dst);
743 brw_set_src0(p, send, header);
744 if (brw->gen < 6)
745 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
746 brw_set_dp_read_message(p, send,
747 255, /* binding table index: stateless access */
748 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
749 msg_type,
750 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
751 2, /* mlen */
752 true, /* header_present */
753 1 /* rlen */);
754 }
755
756 void
757 vec4_generator::generate_scratch_write(vec4_instruction *inst,
758 struct brw_reg dst,
759 struct brw_reg src,
760 struct brw_reg index)
761 {
762 struct brw_reg header = brw_vec8_grf(0, 0);
763 bool write_commit;
764
765 /* If the instruction is predicated, we'll predicate the send, not
766 * the header setup.
767 */
768 brw_set_default_predicate_control(p, false);
769
770 gen6_resolve_implied_move(p, &header, inst->base_mrf);
771
772 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
773 index);
774
775 brw_MOV(p,
776 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
777 retype(src, BRW_REGISTER_TYPE_D));
778
779 uint32_t msg_type;
780
781 if (brw->gen >= 7)
782 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
783 else if (brw->gen == 6)
784 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
785 else
786 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
787
788 brw_set_default_predicate_control(p, inst->predicate);
789
790 /* Pre-gen6, we have to specify write commits to ensure ordering
791 * between reads and writes within a thread. Afterwards, that's
792 * guaranteed and write commits only matter for inter-thread
793 * synchronization.
794 */
795 if (brw->gen >= 6) {
796 write_commit = false;
797 } else {
798 /* The visitor set up our destination register to be g0. This
799 * means that when the next read comes along, we will end up
800 * reading from g0 and causing a block on the write commit. For
801 * write-after-read, we are relying on the value of the previous
802 * read being used (and thus blocking on completion) before our
803 * write is executed. This means we have to be careful in
804 * instruction scheduling to not violate this assumption.
805 */
806 write_commit = true;
807 }
808
809 /* Each of the 8 channel enables is considered for whether each
810 * dword is written.
811 */
812 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
813 brw_set_dest(p, send, dst);
814 brw_set_src0(p, send, header);
815 if (brw->gen < 6)
816 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
817 brw_set_dp_write_message(p, send,
818 255, /* binding table index: stateless access */
819 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
820 msg_type,
821 3, /* mlen */
822 true, /* header present */
823 false, /* not a render target write */
824 write_commit, /* rlen */
825 false, /* eot */
826 write_commit);
827 }
828
829 void
830 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
831 struct brw_reg dst,
832 struct brw_reg index,
833 struct brw_reg offset)
834 {
835 assert(index.file == BRW_IMMEDIATE_VALUE &&
836 index.type == BRW_REGISTER_TYPE_UD);
837 uint32_t surf_index = index.dw1.ud;
838
839 struct brw_reg header = brw_vec8_grf(0, 0);
840
841 gen6_resolve_implied_move(p, &header, inst->base_mrf);
842
843 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
844 offset);
845
846 uint32_t msg_type;
847
848 if (brw->gen >= 6)
849 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
850 else if (brw->gen == 5 || brw->is_g4x)
851 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
852 else
853 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
854
855 /* Each of the 8 channel enables is considered for whether each
856 * dword is written.
857 */
858 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
859 brw_set_dest(p, send, dst);
860 brw_set_src0(p, send, header);
861 if (brw->gen < 6)
862 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
863 brw_set_dp_read_message(p, send,
864 surf_index,
865 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
866 msg_type,
867 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
868 2, /* mlen */
869 true, /* header_present */
870 1 /* rlen */);
871
872 brw_mark_surface_used(&prog_data->base, surf_index);
873 }
874
875 void
876 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
877 struct brw_reg dst,
878 struct brw_reg surf_index,
879 struct brw_reg offset)
880 {
881 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
882
883 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
884
885 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
886 brw_set_dest(p, insn, dst);
887 brw_set_src0(p, insn, offset);
888 brw_set_sampler_message(p, insn,
889 surf_index.dw1.ud,
890 0, /* LD message ignores sampler unit */
891 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
892 1, /* rlen */
893 1, /* mlen */
894 false, /* no header */
895 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
896 0);
897
898 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
899
900 } else {
901
902 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
903
904 brw_push_insn_state(p);
905 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
906 brw_set_default_access_mode(p, BRW_ALIGN_1);
907
908 /* a0.0 = surf_index & 0xff */
909 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
910 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
911 brw_set_dest(p, insn_and, addr);
912 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
913 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
914
915
916 /* a0.0 |= <descriptor> */
917 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
918 brw_set_sampler_message(p, insn_or,
919 0 /* surface */,
920 0 /* sampler */,
921 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
922 1 /* rlen */,
923 1 /* mlen */,
924 false /* header */,
925 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
926 0);
927 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
928 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
929 brw_set_src0(p, insn_or, addr);
930 brw_set_dest(p, insn_or, addr);
931
932
933 /* dst = send(offset, a0.0) */
934 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
935 brw_set_dest(p, insn_send, dst);
936 brw_set_src0(p, insn_send, offset);
937 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
938
939 brw_pop_insn_state(p);
940
941 /* visitor knows more than we do about the surface limit required,
942 * so has already done marking.
943 */
944 }
945 }
946
947 void
948 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
949 struct brw_reg dst,
950 struct brw_reg atomic_op,
951 struct brw_reg surf_index)
952 {
953 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
954 atomic_op.type == BRW_REGISTER_TYPE_UD &&
955 surf_index.file == BRW_IMMEDIATE_VALUE &&
956 surf_index.type == BRW_REGISTER_TYPE_UD);
957
958 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
959 atomic_op.dw1.ud, surf_index.dw1.ud,
960 inst->mlen, 1);
961
962 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
963 }
964
965 void
966 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
967 struct brw_reg dst,
968 struct brw_reg surf_index)
969 {
970 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
971 surf_index.type == BRW_REGISTER_TYPE_UD);
972
973 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
974 surf_index.dw1.ud,
975 inst->mlen, 1);
976
977 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
978 }
979
980 void
981 vec4_generator::generate_code(const cfg_t *cfg)
982 {
983 struct annotation_info annotation;
984 memset(&annotation, 0, sizeof(annotation));
985 int loop_count = 0;
986
987 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
988 struct brw_reg src[3], dst;
989
990 if (unlikely(debug_flag))
991 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
992
993 for (unsigned int i = 0; i < 3; i++) {
994 src[i] = inst->get_src(this->prog_data, i);
995 }
996 dst = inst->get_dst();
997
998 brw_set_default_predicate_control(p, inst->predicate);
999 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1000 brw_set_default_saturate(p, inst->saturate);
1001 brw_set_default_mask_control(p, inst->force_writemask_all);
1002 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1003
1004 unsigned pre_emit_nr_insn = p->nr_insn;
1005
1006 if (dst.width == BRW_WIDTH_4) {
1007 /* This happens in attribute fixups for "dual instanced" geometry
1008 * shaders, since they use attributes that are vec4's. Since the exec
1009 * width is only 4, it's essential that the caller set
1010 * force_writemask_all in order to make sure the instruction is executed
1011 * regardless of which channels are enabled.
1012 */
1013 assert(inst->force_writemask_all);
1014
1015 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1016 * the following register region restrictions (from Graphics BSpec:
1017 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1018 * > Register Region Restrictions)
1019 *
1020 * 1. ExecSize must be greater than or equal to Width.
1021 *
1022 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1023 * to Width * HorzStride."
1024 */
1025 for (int i = 0; i < 3; i++) {
1026 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1027 src[i] = stride(src[i], 4, 4, 1);
1028 }
1029 }
1030
1031 switch (inst->opcode) {
1032 case BRW_OPCODE_MOV:
1033 brw_MOV(p, dst, src[0]);
1034 break;
1035 case BRW_OPCODE_ADD:
1036 brw_ADD(p, dst, src[0], src[1]);
1037 break;
1038 case BRW_OPCODE_MUL:
1039 brw_MUL(p, dst, src[0], src[1]);
1040 break;
1041 case BRW_OPCODE_MACH:
1042 brw_MACH(p, dst, src[0], src[1]);
1043 break;
1044
1045 case BRW_OPCODE_MAD:
1046 assert(brw->gen >= 6);
1047 brw_MAD(p, dst, src[0], src[1], src[2]);
1048 break;
1049
1050 case BRW_OPCODE_FRC:
1051 brw_FRC(p, dst, src[0]);
1052 break;
1053 case BRW_OPCODE_RNDD:
1054 brw_RNDD(p, dst, src[0]);
1055 break;
1056 case BRW_OPCODE_RNDE:
1057 brw_RNDE(p, dst, src[0]);
1058 break;
1059 case BRW_OPCODE_RNDZ:
1060 brw_RNDZ(p, dst, src[0]);
1061 break;
1062
1063 case BRW_OPCODE_AND:
1064 brw_AND(p, dst, src[0], src[1]);
1065 break;
1066 case BRW_OPCODE_OR:
1067 brw_OR(p, dst, src[0], src[1]);
1068 break;
1069 case BRW_OPCODE_XOR:
1070 brw_XOR(p, dst, src[0], src[1]);
1071 break;
1072 case BRW_OPCODE_NOT:
1073 brw_NOT(p, dst, src[0]);
1074 break;
1075 case BRW_OPCODE_ASR:
1076 brw_ASR(p, dst, src[0], src[1]);
1077 break;
1078 case BRW_OPCODE_SHR:
1079 brw_SHR(p, dst, src[0], src[1]);
1080 break;
1081 case BRW_OPCODE_SHL:
1082 brw_SHL(p, dst, src[0], src[1]);
1083 break;
1084
1085 case BRW_OPCODE_CMP:
1086 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1087 break;
1088 case BRW_OPCODE_SEL:
1089 brw_SEL(p, dst, src[0], src[1]);
1090 break;
1091
1092 case BRW_OPCODE_DPH:
1093 brw_DPH(p, dst, src[0], src[1]);
1094 break;
1095
1096 case BRW_OPCODE_DP4:
1097 brw_DP4(p, dst, src[0], src[1]);
1098 break;
1099
1100 case BRW_OPCODE_DP3:
1101 brw_DP3(p, dst, src[0], src[1]);
1102 break;
1103
1104 case BRW_OPCODE_DP2:
1105 brw_DP2(p, dst, src[0], src[1]);
1106 break;
1107
1108 case BRW_OPCODE_F32TO16:
1109 assert(brw->gen >= 7);
1110 brw_F32TO16(p, dst, src[0]);
1111 break;
1112
1113 case BRW_OPCODE_F16TO32:
1114 assert(brw->gen >= 7);
1115 brw_F16TO32(p, dst, src[0]);
1116 break;
1117
1118 case BRW_OPCODE_LRP:
1119 assert(brw->gen >= 6);
1120 brw_LRP(p, dst, src[0], src[1], src[2]);
1121 break;
1122
1123 case BRW_OPCODE_BFREV:
1124 assert(brw->gen >= 7);
1125 /* BFREV only supports UD type for src and dst. */
1126 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1127 retype(src[0], BRW_REGISTER_TYPE_UD));
1128 break;
1129 case BRW_OPCODE_FBH:
1130 assert(brw->gen >= 7);
1131 /* FBH only supports UD type for dst. */
1132 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1133 break;
1134 case BRW_OPCODE_FBL:
1135 assert(brw->gen >= 7);
1136 /* FBL only supports UD type for dst. */
1137 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1138 break;
1139 case BRW_OPCODE_CBIT:
1140 assert(brw->gen >= 7);
1141 /* CBIT only supports UD type for dst. */
1142 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1143 break;
1144 case BRW_OPCODE_ADDC:
1145 assert(brw->gen >= 7);
1146 brw_ADDC(p, dst, src[0], src[1]);
1147 break;
1148 case BRW_OPCODE_SUBB:
1149 assert(brw->gen >= 7);
1150 brw_SUBB(p, dst, src[0], src[1]);
1151 break;
1152 case BRW_OPCODE_MAC:
1153 brw_MAC(p, dst, src[0], src[1]);
1154 break;
1155
1156 case BRW_OPCODE_BFE:
1157 assert(brw->gen >= 7);
1158 brw_BFE(p, dst, src[0], src[1], src[2]);
1159 break;
1160
1161 case BRW_OPCODE_BFI1:
1162 assert(brw->gen >= 7);
1163 brw_BFI1(p, dst, src[0], src[1]);
1164 break;
1165 case BRW_OPCODE_BFI2:
1166 assert(brw->gen >= 7);
1167 brw_BFI2(p, dst, src[0], src[1], src[2]);
1168 break;
1169
1170 case BRW_OPCODE_IF:
1171 if (inst->src[0].file != BAD_FILE) {
1172 /* The instruction has an embedded compare (only allowed on gen6) */
1173 assert(brw->gen == 6);
1174 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1175 } else {
1176 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1177 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1178 }
1179 break;
1180
1181 case BRW_OPCODE_ELSE:
1182 brw_ELSE(p);
1183 break;
1184 case BRW_OPCODE_ENDIF:
1185 brw_ENDIF(p);
1186 break;
1187
1188 case BRW_OPCODE_DO:
1189 brw_DO(p, BRW_EXECUTE_8);
1190 break;
1191
1192 case BRW_OPCODE_BREAK:
1193 brw_BREAK(p);
1194 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1195 break;
1196 case BRW_OPCODE_CONTINUE:
1197 brw_CONT(p);
1198 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1199 break;
1200
1201 case BRW_OPCODE_WHILE:
1202 brw_WHILE(p);
1203 loop_count++;
1204 break;
1205
1206 case SHADER_OPCODE_RCP:
1207 case SHADER_OPCODE_RSQ:
1208 case SHADER_OPCODE_SQRT:
1209 case SHADER_OPCODE_EXP2:
1210 case SHADER_OPCODE_LOG2:
1211 case SHADER_OPCODE_SIN:
1212 case SHADER_OPCODE_COS:
1213 if (brw->gen >= 7) {
1214 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1215 brw_null_reg());
1216 } else if (brw->gen == 6) {
1217 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1218 } else {
1219 generate_math1_gen4(inst, dst, src[0]);
1220 }
1221 break;
1222
1223 case SHADER_OPCODE_POW:
1224 case SHADER_OPCODE_INT_QUOTIENT:
1225 case SHADER_OPCODE_INT_REMAINDER:
1226 if (brw->gen >= 7) {
1227 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1228 } else if (brw->gen == 6) {
1229 generate_math_gen6(inst, dst, src[0], src[1]);
1230 } else {
1231 generate_math2_gen4(inst, dst, src[0], src[1]);
1232 }
1233 break;
1234
1235 case SHADER_OPCODE_TEX:
1236 case SHADER_OPCODE_TXD:
1237 case SHADER_OPCODE_TXF:
1238 case SHADER_OPCODE_TXF_CMS:
1239 case SHADER_OPCODE_TXF_MCS:
1240 case SHADER_OPCODE_TXL:
1241 case SHADER_OPCODE_TXS:
1242 case SHADER_OPCODE_TG4:
1243 case SHADER_OPCODE_TG4_OFFSET:
1244 generate_tex(inst, dst, src[0], src[1]);
1245 break;
1246
1247 case VS_OPCODE_URB_WRITE:
1248 generate_vs_urb_write(inst);
1249 break;
1250
1251 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1252 generate_scratch_read(inst, dst, src[0]);
1253 break;
1254
1255 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1256 generate_scratch_write(inst, dst, src[0], src[1]);
1257 break;
1258
1259 case VS_OPCODE_PULL_CONSTANT_LOAD:
1260 generate_pull_constant_load(inst, dst, src[0], src[1]);
1261 break;
1262
1263 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1264 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1265 break;
1266
1267 case GS_OPCODE_URB_WRITE:
1268 generate_gs_urb_write(inst);
1269 break;
1270
1271 case GS_OPCODE_THREAD_END:
1272 generate_gs_thread_end(inst);
1273 break;
1274
1275 case GS_OPCODE_SET_WRITE_OFFSET:
1276 generate_gs_set_write_offset(dst, src[0], src[1]);
1277 break;
1278
1279 case GS_OPCODE_SET_VERTEX_COUNT:
1280 generate_gs_set_vertex_count(dst, src[0]);
1281 break;
1282
1283 case GS_OPCODE_SET_DWORD_2_IMMED:
1284 generate_gs_set_dword_2_immed(dst, src[0]);
1285 break;
1286
1287 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1288 generate_gs_prepare_channel_masks(dst);
1289 break;
1290
1291 case GS_OPCODE_SET_CHANNEL_MASKS:
1292 generate_gs_set_channel_masks(dst, src[0]);
1293 break;
1294
1295 case GS_OPCODE_GET_INSTANCE_ID:
1296 generate_gs_get_instance_id(dst);
1297 break;
1298
1299 case SHADER_OPCODE_SHADER_TIME_ADD:
1300 brw_shader_time_add(p, src[0],
1301 prog_data->base.binding_table.shader_time_start);
1302 brw_mark_surface_used(&prog_data->base,
1303 prog_data->base.binding_table.shader_time_start);
1304 break;
1305
1306 case SHADER_OPCODE_UNTYPED_ATOMIC:
1307 generate_untyped_atomic(inst, dst, src[0], src[1]);
1308 break;
1309
1310 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1311 generate_untyped_surface_read(inst, dst, src[0]);
1312 break;
1313
1314 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1315 generate_unpack_flags(inst, dst);
1316 break;
1317
1318 default:
1319 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1320 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1321 opcode_descs[inst->opcode].name);
1322 } else {
1323 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1324 }
1325 abort();
1326 }
1327
1328 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1329 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1330 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1331 "emitting more than 1 instruction");
1332
1333 brw_inst *last = &p->store[pre_emit_nr_insn];
1334
1335 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1336 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1337 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1338 }
1339 }
1340
1341 brw_set_uip_jip(p);
1342 annotation_finalize(&annotation, p->next_insn_offset);
1343
1344 int before_size = p->next_insn_offset;
1345 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1346 int after_size = p->next_insn_offset;
1347
1348 if (unlikely(debug_flag)) {
1349 if (shader_prog) {
1350 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1351 shader_prog->Label ? shader_prog->Label : "unnamed",
1352 shader_prog->Name);
1353 } else {
1354 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1355 }
1356 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1357 " bytes (%.0f%%)\n",
1358 before_size / 16, loop_count, before_size, after_size,
1359 100.0f * (before_size - after_size) / before_size);
1360
1361 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1362 ralloc_free(annotation.ann);
1363 }
1364 }
1365
1366 const unsigned *
1367 vec4_generator::generate_assembly(const cfg_t *cfg,
1368 unsigned *assembly_size)
1369 {
1370 brw_set_default_access_mode(p, BRW_ALIGN_16);
1371 generate_code(cfg);
1372
1373 return brw_get_program(p, assembly_size);
1374 }
1375
1376 } /* namespace brw */