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i965: Clean up #includes in the compiler.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "glsl/glsl_parser_extras.h"
24 #include "brw_vec4.h"
25 #include "brw_cfg.h"
26 #include "brw_eu.h"
27 #include "brw_program.h"
28
29 using namespace brw;
30
31 static void
32 generate_math1_gen4(struct brw_codegen *p,
33 vec4_instruction *inst,
34 struct brw_reg dst,
35 struct brw_reg src)
36 {
37 gen4_math(p,
38 dst,
39 brw_math_function(inst->opcode),
40 inst->base_mrf,
41 src,
42 BRW_MATH_PRECISION_FULL);
43 }
44
45 static void
46 check_gen6_math_src_arg(struct brw_reg src)
47 {
48 /* Source swizzles are ignored. */
49 assert(!src.abs);
50 assert(!src.negate);
51 assert(src.swizzle == BRW_SWIZZLE_XYZW);
52 }
53
54 static void
55 generate_math_gen6(struct brw_codegen *p,
56 vec4_instruction *inst,
57 struct brw_reg dst,
58 struct brw_reg src0,
59 struct brw_reg src1)
60 {
61 /* Can't do writemask because math can't be align16. */
62 assert(dst.writemask == WRITEMASK_XYZW);
63 /* Source swizzles are ignored. */
64 check_gen6_math_src_arg(src0);
65 if (src1.file == BRW_GENERAL_REGISTER_FILE)
66 check_gen6_math_src_arg(src1);
67
68 brw_set_default_access_mode(p, BRW_ALIGN_1);
69 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
70 brw_set_default_access_mode(p, BRW_ALIGN_16);
71 }
72
73 static void
74 generate_math2_gen4(struct brw_codegen *p,
75 vec4_instruction *inst,
76 struct brw_reg dst,
77 struct brw_reg src0,
78 struct brw_reg src1)
79 {
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
81 * "Message Payload":
82 *
83 * "Operand0[7]. For the INT DIV functions, this operand is the
84 * denominator."
85 * ...
86 * "Operand1[7]. For the INT DIV functions, this operand is the
87 * numerator."
88 */
89 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
90 struct brw_reg &op0 = is_int_div ? src1 : src0;
91 struct brw_reg &op1 = is_int_div ? src0 : src1;
92
93 brw_push_insn_state(p);
94 brw_set_default_saturate(p, false);
95 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
96 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
97 brw_pop_insn_state(p);
98
99 gen4_math(p,
100 dst,
101 brw_math_function(inst->opcode),
102 inst->base_mrf,
103 op0,
104 BRW_MATH_PRECISION_FULL);
105 }
106
107 static void
108 generate_tex(struct brw_codegen *p,
109 struct brw_vue_prog_data *prog_data,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg sampler_index)
114 {
115 const struct brw_device_info *devinfo = p->devinfo;
116 int msg_type = -1;
117
118 if (devinfo->gen >= 5) {
119 switch (inst->opcode) {
120 case SHADER_OPCODE_TEX:
121 case SHADER_OPCODE_TXL:
122 if (inst->shadow_compare) {
123 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
124 } else {
125 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
126 }
127 break;
128 case SHADER_OPCODE_TXD:
129 if (inst->shadow_compare) {
130 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
131 assert(devinfo->gen >= 8 || devinfo->is_haswell);
132 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
133 } else {
134 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
135 }
136 break;
137 case SHADER_OPCODE_TXF:
138 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
139 break;
140 case SHADER_OPCODE_TXF_CMS_W:
141 assert(devinfo->gen >= 9);
142 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
143 break;
144 case SHADER_OPCODE_TXF_CMS:
145 if (devinfo->gen >= 7)
146 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
147 else
148 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
149 break;
150 case SHADER_OPCODE_TXF_MCS:
151 assert(devinfo->gen >= 7);
152 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
153 break;
154 case SHADER_OPCODE_TXS:
155 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
156 break;
157 case SHADER_OPCODE_TG4:
158 if (inst->shadow_compare) {
159 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
160 } else {
161 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
162 }
163 break;
164 case SHADER_OPCODE_TG4_OFFSET:
165 if (inst->shadow_compare) {
166 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
167 } else {
168 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
169 }
170 break;
171 case SHADER_OPCODE_SAMPLEINFO:
172 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
173 break;
174 default:
175 unreachable("should not get here: invalid vec4 texture opcode");
176 }
177 } else {
178 switch (inst->opcode) {
179 case SHADER_OPCODE_TEX:
180 case SHADER_OPCODE_TXL:
181 if (inst->shadow_compare) {
182 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
183 assert(inst->mlen == 3);
184 } else {
185 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
186 assert(inst->mlen == 2);
187 }
188 break;
189 case SHADER_OPCODE_TXD:
190 /* There is no sample_d_c message; comparisons are done manually. */
191 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
192 assert(inst->mlen == 4);
193 break;
194 case SHADER_OPCODE_TXF:
195 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
196 assert(inst->mlen == 2);
197 break;
198 case SHADER_OPCODE_TXS:
199 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
200 assert(inst->mlen == 2);
201 break;
202 default:
203 unreachable("should not get here: invalid vec4 texture opcode");
204 }
205 }
206
207 assert(msg_type != -1);
208
209 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
210
211 /* Load the message header if present. If there's a texture offset, we need
212 * to set it up explicitly and load the offset bitfield. Otherwise, we can
213 * use an implied move from g0 to the first message register.
214 */
215 if (inst->header_size != 0) {
216 if (devinfo->gen < 6 && !inst->offset) {
217 /* Set up an implied move from g0 to the MRF. */
218 src = brw_vec8_grf(0, 0);
219 } else {
220 struct brw_reg header =
221 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
222 uint32_t dw2 = 0;
223
224 /* Explicitly set up the message header by copying g0 to the MRF. */
225 brw_push_insn_state(p);
226 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
227 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
228
229 brw_set_default_access_mode(p, BRW_ALIGN_1);
230
231 if (inst->offset)
232 /* Set the texel offset bits in DWord 2. */
233 dw2 = inst->offset;
234
235 if (devinfo->gen >= 9)
236 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
237 * based on bit 22 in the header.
238 */
239 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
240
241 if (dw2)
242 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
243
244 brw_adjust_sampler_state_pointer(p, header, sampler_index);
245 brw_pop_insn_state(p);
246 }
247 }
248
249 uint32_t return_format;
250
251 switch (dst.type) {
252 case BRW_REGISTER_TYPE_D:
253 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
254 break;
255 case BRW_REGISTER_TYPE_UD:
256 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
257 break;
258 default:
259 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
260 break;
261 }
262
263 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
264 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
265 ? prog_data->base.binding_table.gather_texture_start
266 : prog_data->base.binding_table.texture_start;
267
268 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
269 uint32_t sampler = sampler_index.ud;
270
271 brw_SAMPLE(p,
272 dst,
273 inst->base_mrf,
274 src,
275 sampler + base_binding_table_index,
276 sampler % 16,
277 msg_type,
278 1, /* response length */
279 inst->mlen,
280 inst->header_size != 0,
281 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
282 return_format);
283
284 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
285 } else {
286 /* Non-constant sampler index. */
287
288 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
289 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
290
291 brw_push_insn_state(p);
292 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
293 brw_set_default_access_mode(p, BRW_ALIGN_1);
294
295 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
296 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
297 if (base_binding_table_index)
298 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
299 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
300
301 brw_pop_insn_state(p);
302
303 if (inst->base_mrf != -1)
304 gen6_resolve_implied_move(p, &src, inst->base_mrf);
305
306 /* dst = send(offset, a0.0 | <descriptor>) */
307 brw_inst *insn = brw_send_indirect_message(
308 p, BRW_SFID_SAMPLER, dst, src, addr);
309 brw_set_sampler_message(p, insn,
310 0 /* surface */,
311 0 /* sampler */,
312 msg_type,
313 1 /* rlen */,
314 inst->mlen /* mlen */,
315 inst->header_size != 0 /* header */,
316 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
317 return_format);
318
319 /* visitor knows more than we do about the surface limit required,
320 * so has already done marking.
321 */
322 }
323 }
324
325 static void
326 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
327 {
328 brw_urb_WRITE(p,
329 brw_null_reg(), /* dest */
330 inst->base_mrf, /* starting mrf reg nr */
331 brw_vec8_grf(0, 0), /* src */
332 inst->urb_write_flags,
333 inst->mlen,
334 0, /* response len */
335 inst->offset, /* urb destination offset */
336 BRW_URB_SWIZZLE_INTERLEAVE);
337 }
338
339 static void
340 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
341 {
342 struct brw_reg src = brw_message_reg(inst->base_mrf);
343 brw_urb_WRITE(p,
344 brw_null_reg(), /* dest */
345 inst->base_mrf, /* starting mrf reg nr */
346 src,
347 inst->urb_write_flags,
348 inst->mlen,
349 0, /* response len */
350 inst->offset, /* urb destination offset */
351 BRW_URB_SWIZZLE_INTERLEAVE);
352 }
353
354 static void
355 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
356 {
357 struct brw_reg src = brw_message_reg(inst->base_mrf);
358
359 /* We pass the temporary passed in src0 as the writeback register */
360 brw_urb_WRITE(p,
361 inst->src[0].as_brw_reg(), /* dest */
362 inst->base_mrf, /* starting mrf reg nr */
363 src,
364 BRW_URB_WRITE_ALLOCATE_COMPLETE,
365 inst->mlen,
366 1, /* response len */
367 inst->offset, /* urb destination offset */
368 BRW_URB_SWIZZLE_INTERLEAVE);
369
370 /* Now put allocated urb handle in dst.0 */
371 brw_push_insn_state(p);
372 brw_set_default_access_mode(p, BRW_ALIGN_1);
373 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
374 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
375 get_element_ud(inst->src[0].as_brw_reg(), 0));
376 brw_pop_insn_state(p);
377 }
378
379 static void
380 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
381 {
382 struct brw_reg src = brw_message_reg(inst->base_mrf);
383 brw_urb_WRITE(p,
384 brw_null_reg(), /* dest */
385 inst->base_mrf, /* starting mrf reg nr */
386 src,
387 BRW_URB_WRITE_EOT | inst->urb_write_flags,
388 inst->mlen,
389 0, /* response len */
390 0, /* urb destination offset */
391 BRW_URB_SWIZZLE_INTERLEAVE);
392 }
393
394 static void
395 generate_gs_set_write_offset(struct brw_codegen *p,
396 struct brw_reg dst,
397 struct brw_reg src0,
398 struct brw_reg src1)
399 {
400 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
401 * Header: M0.3):
402 *
403 * Slot 0 Offset. This field, after adding to the Global Offset field
404 * in the message descriptor, specifies the offset (in 256-bit units)
405 * from the start of the URB entry, as referenced by URB Handle 0, at
406 * which the data will be accessed.
407 *
408 * Similar text describes DWORD M0.4, which is slot 1 offset.
409 *
410 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
411 * of the register for geometry shader invocations 0 and 1) by the
412 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
413 *
414 * We can do this with the following EU instruction:
415 *
416 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
417 */
418 brw_push_insn_state(p);
419 brw_set_default_access_mode(p, BRW_ALIGN_1);
420 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
421 assert(p->devinfo->gen >= 7 &&
422 src1.file == BRW_IMMEDIATE_VALUE &&
423 src1.type == BRW_REGISTER_TYPE_UD &&
424 src1.ud <= USHRT_MAX);
425 if (src0.file == BRW_IMMEDIATE_VALUE) {
426 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
427 brw_imm_ud(src0.ud * src1.ud));
428 } else {
429 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
430 retype(src1, BRW_REGISTER_TYPE_UW));
431 }
432 brw_pop_insn_state(p);
433 }
434
435 static void
436 generate_gs_set_vertex_count(struct brw_codegen *p,
437 struct brw_reg dst,
438 struct brw_reg src)
439 {
440 brw_push_insn_state(p);
441 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
442
443 if (p->devinfo->gen >= 8) {
444 /* Move the vertex count into the second MRF for the EOT write. */
445 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
446 src);
447 } else {
448 /* If we think of the src and dst registers as composed of 8 DWORDs each,
449 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
450 * them to WORDs, and then pack them into DWORD 2 of dst.
451 *
452 * It's easier to get the EU to do this if we think of the src and dst
453 * registers as composed of 16 WORDS each; then, we want to pick up the
454 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
455 * of dst.
456 *
457 * We can do that by the following EU instruction:
458 *
459 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
460 */
461 brw_set_default_access_mode(p, BRW_ALIGN_1);
462 brw_MOV(p,
463 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
464 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
465 }
466 brw_pop_insn_state(p);
467 }
468
469 static void
470 generate_gs_svb_write(struct brw_codegen *p,
471 struct brw_vue_prog_data *prog_data,
472 vec4_instruction *inst,
473 struct brw_reg dst,
474 struct brw_reg src0,
475 struct brw_reg src1)
476 {
477 int binding = inst->sol_binding;
478 bool final_write = inst->sol_final_write;
479
480 brw_push_insn_state(p);
481 /* Copy Vertex data into M0.x */
482 brw_MOV(p, stride(dst, 4, 4, 1),
483 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
484
485 /* Send SVB Write */
486 brw_svb_write(p,
487 final_write ? src1 : brw_null_reg(), /* dest == src1 */
488 1, /* msg_reg_nr */
489 dst, /* src0 == previous dst */
490 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
491 final_write); /* send_commit_msg */
492
493 /* Finally, wait for the write commit to occur so that we can proceed to
494 * other things safely.
495 *
496 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
497 *
498 * The write commit does not modify the destination register, but
499 * merely clears the dependency associated with the destination
500 * register. Thus, a simple “mov” instruction using the register as a
501 * source is sufficient to wait for the write commit to occur.
502 */
503 if (final_write) {
504 brw_MOV(p, src1, src1);
505 }
506 brw_pop_insn_state(p);
507 }
508
509 static void
510 generate_gs_svb_set_destination_index(struct brw_codegen *p,
511 vec4_instruction *inst,
512 struct brw_reg dst,
513 struct brw_reg src)
514 {
515 int vertex = inst->sol_vertex;
516 brw_push_insn_state(p);
517 brw_set_default_access_mode(p, BRW_ALIGN_1);
518 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
519 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
520 brw_pop_insn_state(p);
521 }
522
523 static void
524 generate_gs_set_dword_2(struct brw_codegen *p,
525 struct brw_reg dst,
526 struct brw_reg src)
527 {
528 brw_push_insn_state(p);
529 brw_set_default_access_mode(p, BRW_ALIGN_1);
530 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
531 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
532 brw_pop_insn_state(p);
533 }
534
535 static void
536 generate_gs_prepare_channel_masks(struct brw_codegen *p,
537 struct brw_reg dst)
538 {
539 /* We want to left shift just DWORD 4 (the x component belonging to the
540 * second geometry shader invocation) by 4 bits. So generate the
541 * instruction:
542 *
543 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
544 */
545 dst = suboffset(vec1(dst), 4);
546 brw_push_insn_state(p);
547 brw_set_default_access_mode(p, BRW_ALIGN_1);
548 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
549 brw_SHL(p, dst, dst, brw_imm_ud(4));
550 brw_pop_insn_state(p);
551 }
552
553 static void
554 generate_gs_set_channel_masks(struct brw_codegen *p,
555 struct brw_reg dst,
556 struct brw_reg src)
557 {
558 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
559 * Header: M0.5):
560 *
561 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
562 *
563 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
564 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
565 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
566 * channel enable to determine the final channel enable. For the
567 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
568 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
569 * in the writeback message. For the URB_WRITE_OWORD &
570 * URB_WRITE_HWORD messages, when final channel enable is 1 it
571 * indicates that Vertex 1 DATA [3] will be written to the surface.
572 *
573 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
574 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
575 *
576 * 14 Vertex 1 DATA [2] Channel Mask
577 * 13 Vertex 1 DATA [1] Channel Mask
578 * 12 Vertex 1 DATA [0] Channel Mask
579 * 11 Vertex 0 DATA [3] Channel Mask
580 * 10 Vertex 0 DATA [2] Channel Mask
581 * 9 Vertex 0 DATA [1] Channel Mask
582 * 8 Vertex 0 DATA [0] Channel Mask
583 *
584 * (This is from a section of the PRM that is agnostic to the particular
585 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
586 * geometry shader invocations 0 and 1, respectively). Since we have the
587 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
588 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
589 * DWORD 4, we just need to OR them together and store the result in bits
590 * 15:8 of DWORD 5.
591 *
592 * It's easier to get the EU to do this if we think of the src and dst
593 * registers as composed of 32 bytes each; then, we want to pick up the
594 * contents of bytes 0 and 16 from src, OR them together, and store them in
595 * byte 21.
596 *
597 * We can do that by the following EU instruction:
598 *
599 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
600 *
601 * Note: this relies on the source register having zeros in (a) bits 7:4 of
602 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
603 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
604 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
605 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
606 * contain valid channel mask values (which are in the range 0x0-0xf).
607 */
608 dst = retype(dst, BRW_REGISTER_TYPE_UB);
609 src = retype(src, BRW_REGISTER_TYPE_UB);
610 brw_push_insn_state(p);
611 brw_set_default_access_mode(p, BRW_ALIGN_1);
612 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
613 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
614 brw_pop_insn_state(p);
615 }
616
617 static void
618 generate_gs_get_instance_id(struct brw_codegen *p,
619 struct brw_reg dst)
620 {
621 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
622 * and store into dst.0 & dst.4. So generate the instruction:
623 *
624 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
625 */
626 brw_push_insn_state(p);
627 brw_set_default_access_mode(p, BRW_ALIGN_1);
628 dst = retype(dst, BRW_REGISTER_TYPE_UD);
629 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
630 brw_SHR(p, dst, stride(r0, 1, 4, 0),
631 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
632 brw_pop_insn_state(p);
633 }
634
635 static void
636 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
637 struct brw_reg dst,
638 struct brw_reg src0,
639 struct brw_reg src1,
640 struct brw_reg src2)
641 {
642 brw_push_insn_state(p);
643 brw_set_default_access_mode(p, BRW_ALIGN_1);
644 /* Save src0 data in 16:31 bits of dst.0 */
645 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
646 brw_imm_ud(0xffffu));
647 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
648 /* Save src1 data in 0:15 bits of dst.0 */
649 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
650 brw_imm_ud(0xffffu));
651 brw_OR(p, suboffset(vec1(dst), 0),
652 suboffset(vec1(dst), 0),
653 suboffset(vec1(src2), 0));
654 brw_pop_insn_state(p);
655 }
656
657 static void
658 generate_gs_ff_sync(struct brw_codegen *p,
659 vec4_instruction *inst,
660 struct brw_reg dst,
661 struct brw_reg src0,
662 struct brw_reg src1)
663 {
664 /* This opcode uses an implied MRF register for:
665 * - the header of the ff_sync message. And as such it is expected to be
666 * initialized to r0 before calling here.
667 * - the destination where we will write the allocated URB handle.
668 */
669 struct brw_reg header =
670 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
671
672 /* Overwrite dword 0 of the header (SO vertices to write) and
673 * dword 1 (number of primitives written).
674 */
675 brw_push_insn_state(p);
676 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
677 brw_set_default_access_mode(p, BRW_ALIGN_1);
678 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
679 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
680 brw_pop_insn_state(p);
681
682 /* Allocate URB handle in dst */
683 brw_ff_sync(p,
684 dst,
685 0,
686 header,
687 1, /* allocate */
688 1, /* response length */
689 0 /* eot */);
690
691 /* Now put allocated urb handle in header.0 */
692 brw_push_insn_state(p);
693 brw_set_default_access_mode(p, BRW_ALIGN_1);
694 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
695 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
696
697 /* src1 is not an immediate when we use transform feedback */
698 if (src1.file != BRW_IMMEDIATE_VALUE)
699 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
700
701 brw_pop_insn_state(p);
702 }
703
704 static void
705 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
706 {
707 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
708 struct brw_reg src = brw_vec8_grf(0, 0);
709 brw_push_insn_state(p);
710 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
711 brw_set_default_access_mode(p, BRW_ALIGN_1);
712 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
713 brw_pop_insn_state(p);
714 }
715
716 static void
717 generate_oword_dual_block_offsets(struct brw_codegen *p,
718 struct brw_reg m1,
719 struct brw_reg index)
720 {
721 int second_vertex_offset;
722
723 if (p->devinfo->gen >= 6)
724 second_vertex_offset = 1;
725 else
726 second_vertex_offset = 16;
727
728 m1 = retype(m1, BRW_REGISTER_TYPE_D);
729
730 /* Set up M1 (message payload). Only the block offsets in M1.0 and
731 * M1.4 are used, and the rest are ignored.
732 */
733 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
734 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
735 struct brw_reg index_0 = suboffset(vec1(index), 0);
736 struct brw_reg index_4 = suboffset(vec1(index), 4);
737
738 brw_push_insn_state(p);
739 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
740 brw_set_default_access_mode(p, BRW_ALIGN_1);
741
742 brw_MOV(p, m1_0, index_0);
743
744 if (index.file == BRW_IMMEDIATE_VALUE) {
745 index_4.ud += second_vertex_offset;
746 brw_MOV(p, m1_4, index_4);
747 } else {
748 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
749 }
750
751 brw_pop_insn_state(p);
752 }
753
754 static void
755 generate_unpack_flags(struct brw_codegen *p,
756 struct brw_reg dst)
757 {
758 brw_push_insn_state(p);
759 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
760 brw_set_default_access_mode(p, BRW_ALIGN_1);
761
762 struct brw_reg flags = brw_flag_reg(0, 0);
763 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
764 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
765
766 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
767 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
768 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
769
770 brw_pop_insn_state(p);
771 }
772
773 static void
774 generate_scratch_read(struct brw_codegen *p,
775 vec4_instruction *inst,
776 struct brw_reg dst,
777 struct brw_reg index)
778 {
779 const struct brw_device_info *devinfo = p->devinfo;
780 struct brw_reg header = brw_vec8_grf(0, 0);
781
782 gen6_resolve_implied_move(p, &header, inst->base_mrf);
783
784 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
785 index);
786
787 uint32_t msg_type;
788
789 if (devinfo->gen >= 6)
790 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
791 else if (devinfo->gen == 5 || devinfo->is_g4x)
792 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
793 else
794 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
795
796 /* Each of the 8 channel enables is considered for whether each
797 * dword is written.
798 */
799 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
800 brw_set_dest(p, send, dst);
801 brw_set_src0(p, send, header);
802 if (devinfo->gen < 6)
803 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
804 brw_set_dp_read_message(p, send,
805 255, /* binding table index: stateless access */
806 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
807 msg_type,
808 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
809 2, /* mlen */
810 true, /* header_present */
811 1 /* rlen */);
812 }
813
814 static void
815 generate_scratch_write(struct brw_codegen *p,
816 vec4_instruction *inst,
817 struct brw_reg dst,
818 struct brw_reg src,
819 struct brw_reg index)
820 {
821 const struct brw_device_info *devinfo = p->devinfo;
822 struct brw_reg header = brw_vec8_grf(0, 0);
823 bool write_commit;
824
825 /* If the instruction is predicated, we'll predicate the send, not
826 * the header setup.
827 */
828 brw_set_default_predicate_control(p, false);
829
830 gen6_resolve_implied_move(p, &header, inst->base_mrf);
831
832 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
833 index);
834
835 brw_MOV(p,
836 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
837 retype(src, BRW_REGISTER_TYPE_D));
838
839 uint32_t msg_type;
840
841 if (devinfo->gen >= 7)
842 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
843 else if (devinfo->gen == 6)
844 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
845 else
846 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
847
848 brw_set_default_predicate_control(p, inst->predicate);
849
850 /* Pre-gen6, we have to specify write commits to ensure ordering
851 * between reads and writes within a thread. Afterwards, that's
852 * guaranteed and write commits only matter for inter-thread
853 * synchronization.
854 */
855 if (devinfo->gen >= 6) {
856 write_commit = false;
857 } else {
858 /* The visitor set up our destination register to be g0. This
859 * means that when the next read comes along, we will end up
860 * reading from g0 and causing a block on the write commit. For
861 * write-after-read, we are relying on the value of the previous
862 * read being used (and thus blocking on completion) before our
863 * write is executed. This means we have to be careful in
864 * instruction scheduling to not violate this assumption.
865 */
866 write_commit = true;
867 }
868
869 /* Each of the 8 channel enables is considered for whether each
870 * dword is written.
871 */
872 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
873 brw_set_dest(p, send, dst);
874 brw_set_src0(p, send, header);
875 if (devinfo->gen < 6)
876 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
877 brw_set_dp_write_message(p, send,
878 255, /* binding table index: stateless access */
879 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
880 msg_type,
881 3, /* mlen */
882 true, /* header present */
883 false, /* not a render target write */
884 write_commit, /* rlen */
885 false, /* eot */
886 write_commit);
887 }
888
889 static void
890 generate_pull_constant_load(struct brw_codegen *p,
891 struct brw_vue_prog_data *prog_data,
892 vec4_instruction *inst,
893 struct brw_reg dst,
894 struct brw_reg index,
895 struct brw_reg offset)
896 {
897 const struct brw_device_info *devinfo = p->devinfo;
898 assert(index.file == BRW_IMMEDIATE_VALUE &&
899 index.type == BRW_REGISTER_TYPE_UD);
900 uint32_t surf_index = index.ud;
901
902 struct brw_reg header = brw_vec8_grf(0, 0);
903
904 gen6_resolve_implied_move(p, &header, inst->base_mrf);
905
906 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
907 offset);
908
909 uint32_t msg_type;
910
911 if (devinfo->gen >= 6)
912 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
913 else if (devinfo->gen == 5 || devinfo->is_g4x)
914 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
915 else
916 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
917
918 /* Each of the 8 channel enables is considered for whether each
919 * dword is written.
920 */
921 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
922 brw_set_dest(p, send, dst);
923 brw_set_src0(p, send, header);
924 if (devinfo->gen < 6)
925 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
926 brw_set_dp_read_message(p, send,
927 surf_index,
928 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
929 msg_type,
930 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
931 2, /* mlen */
932 true, /* header_present */
933 1 /* rlen */);
934 }
935
936 static void
937 generate_get_buffer_size(struct brw_codegen *p,
938 struct brw_vue_prog_data *prog_data,
939 vec4_instruction *inst,
940 struct brw_reg dst,
941 struct brw_reg src,
942 struct brw_reg surf_index)
943 {
944 assert(p->devinfo->gen >= 7);
945 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
946 surf_index.file == BRW_IMMEDIATE_VALUE);
947
948 brw_SAMPLE(p,
949 dst,
950 inst->base_mrf,
951 src,
952 surf_index.ud,
953 0,
954 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
955 1, /* response length */
956 inst->mlen,
957 inst->header_size > 0,
958 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
959 BRW_SAMPLER_RETURN_FORMAT_SINT32);
960
961 brw_mark_surface_used(&prog_data->base, surf_index.ud);
962 }
963
964 static void
965 generate_pull_constant_load_gen7(struct brw_codegen *p,
966 struct brw_vue_prog_data *prog_data,
967 vec4_instruction *inst,
968 struct brw_reg dst,
969 struct brw_reg surf_index,
970 struct brw_reg offset)
971 {
972 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
973
974 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
975
976 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
977 brw_set_dest(p, insn, dst);
978 brw_set_src0(p, insn, offset);
979 brw_set_sampler_message(p, insn,
980 surf_index.ud,
981 0, /* LD message ignores sampler unit */
982 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
983 1, /* rlen */
984 inst->mlen,
985 inst->header_size != 0,
986 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
987 0);
988
989 brw_mark_surface_used(&prog_data->base, surf_index.ud);
990
991 } else {
992
993 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
994
995 brw_push_insn_state(p);
996 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
997 brw_set_default_access_mode(p, BRW_ALIGN_1);
998
999 /* a0.0 = surf_index & 0xff */
1000 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1001 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1002 brw_set_dest(p, insn_and, addr);
1003 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1004 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1005
1006 brw_pop_insn_state(p);
1007
1008 /* dst = send(offset, a0.0 | <descriptor>) */
1009 brw_inst *insn = brw_send_indirect_message(
1010 p, BRW_SFID_SAMPLER, dst, offset, addr);
1011 brw_set_sampler_message(p, insn,
1012 0 /* surface */,
1013 0 /* sampler */,
1014 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1015 1 /* rlen */,
1016 inst->mlen,
1017 inst->header_size != 0,
1018 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1019 0);
1020 }
1021 }
1022
1023 static void
1024 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1025 vec4_instruction *inst,
1026 struct brw_reg dst)
1027 {
1028 brw_push_insn_state(p);
1029 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1030
1031 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1032 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1033
1034 brw_set_default_access_mode(p, BRW_ALIGN_1);
1035 brw_MOV(p, get_element_ud(dst, 2),
1036 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1037
1038 brw_pop_insn_state(p);
1039 }
1040
1041 static void
1042 generate_code(struct brw_codegen *p,
1043 const struct brw_compiler *compiler,
1044 void *log_data,
1045 const nir_shader *nir,
1046 struct brw_vue_prog_data *prog_data,
1047 const struct cfg_t *cfg)
1048 {
1049 const struct brw_device_info *devinfo = p->devinfo;
1050 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
1051 bool debug_flag = INTEL_DEBUG &
1052 intel_debug_flag_for_shader_stage(nir->stage);
1053 struct annotation_info annotation;
1054 memset(&annotation, 0, sizeof(annotation));
1055 int loop_count = 0;
1056
1057 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1058 struct brw_reg src[3], dst;
1059
1060 if (unlikely(debug_flag))
1061 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1062
1063 for (unsigned int i = 0; i < 3; i++) {
1064 src[i] = inst->src[i].as_brw_reg();
1065 }
1066 dst = inst->dst.as_brw_reg();
1067
1068 brw_set_default_predicate_control(p, inst->predicate);
1069 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1070 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1071 brw_set_default_saturate(p, inst->saturate);
1072 brw_set_default_mask_control(p, inst->force_writemask_all);
1073 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1074
1075 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1076 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1077
1078 unsigned pre_emit_nr_insn = p->nr_insn;
1079
1080 if (dst.width == BRW_WIDTH_4) {
1081 /* This happens in attribute fixups for "dual instanced" geometry
1082 * shaders, since they use attributes that are vec4's. Since the exec
1083 * width is only 4, it's essential that the caller set
1084 * force_writemask_all in order to make sure the instruction is executed
1085 * regardless of which channels are enabled.
1086 */
1087 assert(inst->force_writemask_all);
1088
1089 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1090 * the following register region restrictions (from Graphics BSpec:
1091 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1092 * > Register Region Restrictions)
1093 *
1094 * 1. ExecSize must be greater than or equal to Width.
1095 *
1096 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1097 * to Width * HorzStride."
1098 */
1099 for (int i = 0; i < 3; i++) {
1100 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1101 src[i] = stride(src[i], 4, 4, 1);
1102 }
1103 }
1104
1105 switch (inst->opcode) {
1106 case VEC4_OPCODE_UNPACK_UNIFORM:
1107 case BRW_OPCODE_MOV:
1108 brw_MOV(p, dst, src[0]);
1109 break;
1110 case BRW_OPCODE_ADD:
1111 brw_ADD(p, dst, src[0], src[1]);
1112 break;
1113 case BRW_OPCODE_MUL:
1114 brw_MUL(p, dst, src[0], src[1]);
1115 break;
1116 case BRW_OPCODE_MACH:
1117 brw_MACH(p, dst, src[0], src[1]);
1118 break;
1119
1120 case BRW_OPCODE_MAD:
1121 assert(devinfo->gen >= 6);
1122 brw_MAD(p, dst, src[0], src[1], src[2]);
1123 break;
1124
1125 case BRW_OPCODE_FRC:
1126 brw_FRC(p, dst, src[0]);
1127 break;
1128 case BRW_OPCODE_RNDD:
1129 brw_RNDD(p, dst, src[0]);
1130 break;
1131 case BRW_OPCODE_RNDE:
1132 brw_RNDE(p, dst, src[0]);
1133 break;
1134 case BRW_OPCODE_RNDZ:
1135 brw_RNDZ(p, dst, src[0]);
1136 break;
1137
1138 case BRW_OPCODE_AND:
1139 brw_AND(p, dst, src[0], src[1]);
1140 break;
1141 case BRW_OPCODE_OR:
1142 brw_OR(p, dst, src[0], src[1]);
1143 break;
1144 case BRW_OPCODE_XOR:
1145 brw_XOR(p, dst, src[0], src[1]);
1146 break;
1147 case BRW_OPCODE_NOT:
1148 brw_NOT(p, dst, src[0]);
1149 break;
1150 case BRW_OPCODE_ASR:
1151 brw_ASR(p, dst, src[0], src[1]);
1152 break;
1153 case BRW_OPCODE_SHR:
1154 brw_SHR(p, dst, src[0], src[1]);
1155 break;
1156 case BRW_OPCODE_SHL:
1157 brw_SHL(p, dst, src[0], src[1]);
1158 break;
1159
1160 case BRW_OPCODE_CMP:
1161 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1162 break;
1163 case BRW_OPCODE_SEL:
1164 brw_SEL(p, dst, src[0], src[1]);
1165 break;
1166
1167 case BRW_OPCODE_DPH:
1168 brw_DPH(p, dst, src[0], src[1]);
1169 break;
1170
1171 case BRW_OPCODE_DP4:
1172 brw_DP4(p, dst, src[0], src[1]);
1173 break;
1174
1175 case BRW_OPCODE_DP3:
1176 brw_DP3(p, dst, src[0], src[1]);
1177 break;
1178
1179 case BRW_OPCODE_DP2:
1180 brw_DP2(p, dst, src[0], src[1]);
1181 break;
1182
1183 case BRW_OPCODE_F32TO16:
1184 assert(devinfo->gen >= 7);
1185 brw_F32TO16(p, dst, src[0]);
1186 break;
1187
1188 case BRW_OPCODE_F16TO32:
1189 assert(devinfo->gen >= 7);
1190 brw_F16TO32(p, dst, src[0]);
1191 break;
1192
1193 case BRW_OPCODE_LRP:
1194 assert(devinfo->gen >= 6);
1195 brw_LRP(p, dst, src[0], src[1], src[2]);
1196 break;
1197
1198 case BRW_OPCODE_BFREV:
1199 assert(devinfo->gen >= 7);
1200 /* BFREV only supports UD type for src and dst. */
1201 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1202 retype(src[0], BRW_REGISTER_TYPE_UD));
1203 break;
1204 case BRW_OPCODE_FBH:
1205 assert(devinfo->gen >= 7);
1206 /* FBH only supports UD type for dst. */
1207 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1208 break;
1209 case BRW_OPCODE_FBL:
1210 assert(devinfo->gen >= 7);
1211 /* FBL only supports UD type for dst. */
1212 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1213 break;
1214 case BRW_OPCODE_CBIT:
1215 assert(devinfo->gen >= 7);
1216 /* CBIT only supports UD type for dst. */
1217 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1218 break;
1219 case BRW_OPCODE_ADDC:
1220 assert(devinfo->gen >= 7);
1221 brw_ADDC(p, dst, src[0], src[1]);
1222 break;
1223 case BRW_OPCODE_SUBB:
1224 assert(devinfo->gen >= 7);
1225 brw_SUBB(p, dst, src[0], src[1]);
1226 break;
1227 case BRW_OPCODE_MAC:
1228 brw_MAC(p, dst, src[0], src[1]);
1229 break;
1230
1231 case BRW_OPCODE_BFE:
1232 assert(devinfo->gen >= 7);
1233 brw_BFE(p, dst, src[0], src[1], src[2]);
1234 break;
1235
1236 case BRW_OPCODE_BFI1:
1237 assert(devinfo->gen >= 7);
1238 brw_BFI1(p, dst, src[0], src[1]);
1239 break;
1240 case BRW_OPCODE_BFI2:
1241 assert(devinfo->gen >= 7);
1242 brw_BFI2(p, dst, src[0], src[1], src[2]);
1243 break;
1244
1245 case BRW_OPCODE_IF:
1246 if (!inst->src[0].is_null()) {
1247 /* The instruction has an embedded compare (only allowed on gen6) */
1248 assert(devinfo->gen == 6);
1249 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1250 } else {
1251 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1252 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1253 }
1254 break;
1255
1256 case BRW_OPCODE_ELSE:
1257 brw_ELSE(p);
1258 break;
1259 case BRW_OPCODE_ENDIF:
1260 brw_ENDIF(p);
1261 break;
1262
1263 case BRW_OPCODE_DO:
1264 brw_DO(p, BRW_EXECUTE_8);
1265 break;
1266
1267 case BRW_OPCODE_BREAK:
1268 brw_BREAK(p);
1269 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1270 break;
1271 case BRW_OPCODE_CONTINUE:
1272 brw_CONT(p);
1273 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1274 break;
1275
1276 case BRW_OPCODE_WHILE:
1277 brw_WHILE(p);
1278 loop_count++;
1279 break;
1280
1281 case SHADER_OPCODE_RCP:
1282 case SHADER_OPCODE_RSQ:
1283 case SHADER_OPCODE_SQRT:
1284 case SHADER_OPCODE_EXP2:
1285 case SHADER_OPCODE_LOG2:
1286 case SHADER_OPCODE_SIN:
1287 case SHADER_OPCODE_COS:
1288 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1289 if (devinfo->gen >= 7) {
1290 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1291 brw_null_reg());
1292 } else if (devinfo->gen == 6) {
1293 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1294 } else {
1295 generate_math1_gen4(p, inst, dst, src[0]);
1296 }
1297 break;
1298
1299 case SHADER_OPCODE_POW:
1300 case SHADER_OPCODE_INT_QUOTIENT:
1301 case SHADER_OPCODE_INT_REMAINDER:
1302 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1303 if (devinfo->gen >= 7) {
1304 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1305 } else if (devinfo->gen == 6) {
1306 generate_math_gen6(p, inst, dst, src[0], src[1]);
1307 } else {
1308 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1309 }
1310 break;
1311
1312 case SHADER_OPCODE_TEX:
1313 case SHADER_OPCODE_TXD:
1314 case SHADER_OPCODE_TXF:
1315 case SHADER_OPCODE_TXF_CMS:
1316 case SHADER_OPCODE_TXF_CMS_W:
1317 case SHADER_OPCODE_TXF_MCS:
1318 case SHADER_OPCODE_TXL:
1319 case SHADER_OPCODE_TXS:
1320 case SHADER_OPCODE_TG4:
1321 case SHADER_OPCODE_TG4_OFFSET:
1322 case SHADER_OPCODE_SAMPLEINFO:
1323 generate_tex(p, prog_data, inst, dst, src[0], src[1]);
1324 break;
1325
1326 case VS_OPCODE_URB_WRITE:
1327 generate_vs_urb_write(p, inst);
1328 break;
1329
1330 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1331 generate_scratch_read(p, inst, dst, src[0]);
1332 break;
1333
1334 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1335 generate_scratch_write(p, inst, dst, src[0], src[1]);
1336 break;
1337
1338 case VS_OPCODE_PULL_CONSTANT_LOAD:
1339 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1340 break;
1341
1342 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1343 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1344 break;
1345
1346 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1347 generate_set_simd4x2_header_gen9(p, inst, dst);
1348 break;
1349
1350
1351 case VS_OPCODE_GET_BUFFER_SIZE:
1352 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1353 break;
1354
1355 case GS_OPCODE_URB_WRITE:
1356 generate_gs_urb_write(p, inst);
1357 break;
1358
1359 case GS_OPCODE_URB_WRITE_ALLOCATE:
1360 generate_gs_urb_write_allocate(p, inst);
1361 break;
1362
1363 case GS_OPCODE_SVB_WRITE:
1364 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1365 break;
1366
1367 case GS_OPCODE_SVB_SET_DST_INDEX:
1368 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1369 break;
1370
1371 case GS_OPCODE_THREAD_END:
1372 generate_gs_thread_end(p, inst);
1373 break;
1374
1375 case GS_OPCODE_SET_WRITE_OFFSET:
1376 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1377 break;
1378
1379 case GS_OPCODE_SET_VERTEX_COUNT:
1380 generate_gs_set_vertex_count(p, dst, src[0]);
1381 break;
1382
1383 case GS_OPCODE_FF_SYNC:
1384 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1385 break;
1386
1387 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1388 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1389 break;
1390
1391 case GS_OPCODE_SET_PRIMITIVE_ID:
1392 generate_gs_set_primitive_id(p, dst);
1393 break;
1394
1395 case GS_OPCODE_SET_DWORD_2:
1396 generate_gs_set_dword_2(p, dst, src[0]);
1397 break;
1398
1399 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1400 generate_gs_prepare_channel_masks(p, dst);
1401 break;
1402
1403 case GS_OPCODE_SET_CHANNEL_MASKS:
1404 generate_gs_set_channel_masks(p, dst, src[0]);
1405 break;
1406
1407 case GS_OPCODE_GET_INSTANCE_ID:
1408 generate_gs_get_instance_id(p, dst);
1409 break;
1410
1411 case SHADER_OPCODE_SHADER_TIME_ADD:
1412 brw_shader_time_add(p, src[0],
1413 prog_data->base.binding_table.shader_time_start);
1414 brw_mark_surface_used(&prog_data->base,
1415 prog_data->base.binding_table.shader_time_start);
1416 break;
1417
1418 case SHADER_OPCODE_UNTYPED_ATOMIC:
1419 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1420 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1421 !inst->dst.is_null());
1422 break;
1423
1424 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1425 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1426 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1427 src[2].ud);
1428 break;
1429
1430 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1431 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1432 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1433 src[2].ud);
1434 break;
1435
1436 case SHADER_OPCODE_TYPED_ATOMIC:
1437 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1438 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1439 !inst->dst.is_null());
1440 break;
1441
1442 case SHADER_OPCODE_TYPED_SURFACE_READ:
1443 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1444 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1445 src[2].ud);
1446 break;
1447
1448 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1449 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1450 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1451 src[2].ud);
1452 break;
1453
1454 case SHADER_OPCODE_MEMORY_FENCE:
1455 brw_memory_fence(p, dst);
1456 break;
1457
1458 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1459 brw_find_live_channel(p, dst);
1460 break;
1461
1462 case SHADER_OPCODE_BROADCAST:
1463 brw_broadcast(p, dst, src[0], src[1]);
1464 break;
1465
1466 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1467 generate_unpack_flags(p, dst);
1468 break;
1469
1470 case VEC4_OPCODE_MOV_BYTES: {
1471 /* Moves the low byte from each channel, using an Align1 access mode
1472 * and a <4,1,0> source region.
1473 */
1474 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1475 src[0].type == BRW_REGISTER_TYPE_B);
1476
1477 brw_set_default_access_mode(p, BRW_ALIGN_1);
1478 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1479 src[0].width = BRW_WIDTH_1;
1480 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1481 brw_MOV(p, dst, src[0]);
1482 brw_set_default_access_mode(p, BRW_ALIGN_16);
1483 break;
1484 }
1485
1486 case VEC4_OPCODE_PACK_BYTES: {
1487 /* Is effectively:
1488 *
1489 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1490 *
1491 * but destinations' only regioning is horizontal stride, so instead we
1492 * have to use two instructions:
1493 *
1494 * mov(4) dst<1>:UB src<4,1,0>:UB
1495 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1496 *
1497 * where they pack the four bytes from the low and high four DW.
1498 */
1499 assert(_mesa_is_pow_two(dst.writemask) &&
1500 dst.writemask != 0);
1501 unsigned offset = __builtin_ctz(dst.writemask);
1502
1503 dst.type = BRW_REGISTER_TYPE_UB;
1504
1505 brw_set_default_access_mode(p, BRW_ALIGN_1);
1506
1507 src[0].type = BRW_REGISTER_TYPE_UB;
1508 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1509 src[0].width = BRW_WIDTH_1;
1510 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1511 dst.subnr = offset * 4;
1512 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1513 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1514 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1515 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1516
1517 src[0].subnr = 16;
1518 dst.subnr = 16 + offset * 4;
1519 insn = brw_MOV(p, dst, src[0]);
1520 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1521 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1522 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1523
1524 brw_set_default_access_mode(p, BRW_ALIGN_16);
1525 break;
1526 }
1527
1528 default:
1529 unreachable("Unsupported opcode");
1530 }
1531
1532 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1533 /* Handled dependency hints in the generator. */
1534
1535 assert(!inst->conditional_mod);
1536 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1537 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1538 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1539 "emitting more than 1 instruction");
1540
1541 brw_inst *last = &p->store[pre_emit_nr_insn];
1542
1543 if (inst->conditional_mod)
1544 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1545 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1546 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1547 }
1548 }
1549
1550 brw_set_uip_jip(p);
1551 annotation_finalize(&annotation, p->next_insn_offset);
1552
1553 #ifndef NDEBUG
1554 bool validated = brw_validate_instructions(p, 0, &annotation);
1555 #else
1556 if (unlikely(debug_flag))
1557 brw_validate_instructions(p, 0, &annotation);
1558 #endif
1559
1560 int before_size = p->next_insn_offset;
1561 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1562 int after_size = p->next_insn_offset;
1563
1564 if (unlikely(debug_flag)) {
1565 fprintf(stderr, "Native code for %s %s shader %s:\n",
1566 nir->info.label ? nir->info.label : "unnamed",
1567 _mesa_shader_stage_to_string(nir->stage), nir->info.name);
1568
1569 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles."
1570 "Compacted %d to %d bytes (%.0f%%)\n",
1571 stage_abbrev,
1572 before_size / 16, loop_count, cfg->cycle_count, before_size, after_size,
1573 100.0f * (before_size - after_size) / before_size);
1574
1575 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1576 p->devinfo);
1577 ralloc_free(annotation.mem_ctx);
1578 }
1579 assert(validated);
1580
1581 compiler->shader_debug_log(log_data,
1582 "%s vec4 shader: %d inst, %d loops, %u cycles, "
1583 "compacted %d to %d bytes.\n",
1584 stage_abbrev, before_size / 16,
1585 loop_count, cfg->cycle_count,
1586 before_size, after_size);
1587 }
1588
1589 extern "C" const unsigned *
1590 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
1591 void *log_data,
1592 void *mem_ctx,
1593 const nir_shader *nir,
1594 struct brw_vue_prog_data *prog_data,
1595 const struct cfg_t *cfg,
1596 unsigned *out_assembly_size)
1597 {
1598 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
1599 brw_init_codegen(compiler->devinfo, p, mem_ctx);
1600 brw_set_default_access_mode(p, BRW_ALIGN_16);
1601
1602 generate_code(p, compiler, log_data, nir, prog_data, cfg);
1603
1604 return brw_get_program(p, out_assembly_size);
1605 }