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i965: Assert that math instructions don't have conditional mod.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 default:
96 unreachable("not reached");
97 }
98 break;
99
100 case UNIFORM:
101 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
102 (src[i].reg + src[i].reg_offset) / 2,
103 ((src[i].reg + src[i].reg_offset) % 2) * 4),
104 0, 4, 1);
105 brw_reg = retype(brw_reg, src[i].type);
106 brw_reg.dw1.bits.swizzle = src[i].swizzle;
107 if (src[i].abs)
108 brw_reg = brw_abs(brw_reg);
109 if (src[i].negate)
110 brw_reg = negate(brw_reg);
111
112 /* This should have been moved to pull constants. */
113 assert(!src[i].reladdr);
114 break;
115
116 case HW_REG:
117 assert(src[i].type == src[i].fixed_hw_reg.type);
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 unreachable("not reached");
128 }
129
130 return brw_reg;
131 }
132
133 vec4_generator::vec4_generator(struct brw_context *brw,
134 struct gl_shader_program *shader_prog,
135 struct gl_program *prog,
136 struct brw_vec4_prog_data *prog_data,
137 void *mem_ctx,
138 bool debug_flag)
139 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
140 mem_ctx(mem_ctx), debug_flag(debug_flag)
141 {
142 p = rzalloc(mem_ctx, struct brw_compile);
143 brw_init_compile(brw, p, mem_ctx);
144 }
145
146 vec4_generator::~vec4_generator()
147 {
148 }
149
150 void
151 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
152 struct brw_reg dst,
153 struct brw_reg src)
154 {
155 gen4_math(p,
156 dst,
157 brw_math_function(inst->opcode),
158 inst->base_mrf,
159 src,
160 BRW_MATH_PRECISION_FULL);
161 }
162
163 static void
164 check_gen6_math_src_arg(struct brw_reg src)
165 {
166 /* Source swizzles are ignored. */
167 assert(!src.abs);
168 assert(!src.negate);
169 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
170 }
171
172 void
173 vec4_generator::generate_math_gen6(vec4_instruction *inst,
174 struct brw_reg dst,
175 struct brw_reg src0,
176 struct brw_reg src1)
177 {
178 /* Can't do writemask because math can't be align16. */
179 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
180 /* Source swizzles are ignored. */
181 check_gen6_math_src_arg(src0);
182 if (src1.file == BRW_GENERAL_REGISTER_FILE)
183 check_gen6_math_src_arg(src1);
184
185 brw_set_default_access_mode(p, BRW_ALIGN_1);
186 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
187 brw_set_default_access_mode(p, BRW_ALIGN_16);
188 }
189
190 void
191 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
192 struct brw_reg dst,
193 struct brw_reg src0,
194 struct brw_reg src1)
195 {
196 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
197 * "Message Payload":
198 *
199 * "Operand0[7]. For the INT DIV functions, this operand is the
200 * denominator."
201 * ...
202 * "Operand1[7]. For the INT DIV functions, this operand is the
203 * numerator."
204 */
205 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
206 struct brw_reg &op0 = is_int_div ? src1 : src0;
207 struct brw_reg &op1 = is_int_div ? src0 : src1;
208
209 brw_push_insn_state(p);
210 brw_set_default_saturate(p, false);
211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
212 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
213 brw_pop_insn_state(p);
214
215 gen4_math(p,
216 dst,
217 brw_math_function(inst->opcode),
218 inst->base_mrf,
219 op0,
220 BRW_MATH_PRECISION_FULL);
221 }
222
223 void
224 vec4_generator::generate_tex(vec4_instruction *inst,
225 struct brw_reg dst,
226 struct brw_reg src,
227 struct brw_reg sampler_index)
228 {
229 int msg_type = -1;
230
231 if (brw->gen >= 5) {
232 switch (inst->opcode) {
233 case SHADER_OPCODE_TEX:
234 case SHADER_OPCODE_TXL:
235 if (inst->shadow_compare) {
236 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
237 } else {
238 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
239 }
240 break;
241 case SHADER_OPCODE_TXD:
242 if (inst->shadow_compare) {
243 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
244 assert(brw->gen >= 8 || brw->is_haswell);
245 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
246 } else {
247 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
248 }
249 break;
250 case SHADER_OPCODE_TXF:
251 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
252 break;
253 case SHADER_OPCODE_TXF_CMS:
254 if (brw->gen >= 7)
255 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
256 else
257 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
258 break;
259 case SHADER_OPCODE_TXF_MCS:
260 assert(brw->gen >= 7);
261 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
262 break;
263 case SHADER_OPCODE_TXS:
264 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
265 break;
266 case SHADER_OPCODE_TG4:
267 if (inst->shadow_compare) {
268 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
269 } else {
270 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
271 }
272 break;
273 case SHADER_OPCODE_TG4_OFFSET:
274 if (inst->shadow_compare) {
275 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
276 } else {
277 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
278 }
279 break;
280 default:
281 unreachable("should not get here: invalid vec4 texture opcode");
282 }
283 } else {
284 switch (inst->opcode) {
285 case SHADER_OPCODE_TEX:
286 case SHADER_OPCODE_TXL:
287 if (inst->shadow_compare) {
288 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
289 assert(inst->mlen == 3);
290 } else {
291 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
292 assert(inst->mlen == 2);
293 }
294 break;
295 case SHADER_OPCODE_TXD:
296 /* There is no sample_d_c message; comparisons are done manually. */
297 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
298 assert(inst->mlen == 4);
299 break;
300 case SHADER_OPCODE_TXF:
301 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
302 assert(inst->mlen == 2);
303 break;
304 case SHADER_OPCODE_TXS:
305 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
306 assert(inst->mlen == 2);
307 break;
308 default:
309 unreachable("should not get here: invalid vec4 texture opcode");
310 }
311 }
312
313 assert(msg_type != -1);
314
315 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
316
317 /* Load the message header if present. If there's a texture offset, we need
318 * to set it up explicitly and load the offset bitfield. Otherwise, we can
319 * use an implied move from g0 to the first message register.
320 */
321 if (inst->header_present) {
322 if (brw->gen < 6 && !inst->offset) {
323 /* Set up an implied move from g0 to the MRF. */
324 src = brw_vec8_grf(0, 0);
325 } else {
326 struct brw_reg header =
327 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
328
329 /* Explicitly set up the message header by copying g0 to the MRF. */
330 brw_push_insn_state(p);
331 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
332 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
333
334 brw_set_default_access_mode(p, BRW_ALIGN_1);
335
336 if (inst->offset) {
337 /* Set the texel offset bits in DWord 2. */
338 brw_MOV(p, get_element_ud(header, 2),
339 brw_imm_ud(inst->offset));
340 }
341
342 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
343 brw_pop_insn_state(p);
344 }
345 }
346
347 uint32_t return_format;
348
349 switch (dst.type) {
350 case BRW_REGISTER_TYPE_D:
351 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
352 break;
353 case BRW_REGISTER_TYPE_UD:
354 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
355 break;
356 default:
357 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
358 break;
359 }
360
361 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
362 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
363 ? prog_data->base.binding_table.gather_texture_start
364 : prog_data->base.binding_table.texture_start;
365
366 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
367 uint32_t sampler = sampler_index.dw1.ud;
368
369 brw_SAMPLE(p,
370 dst,
371 inst->base_mrf,
372 src,
373 sampler + base_binding_table_index,
374 sampler % 16,
375 msg_type,
376 1, /* response length */
377 inst->mlen,
378 inst->header_present,
379 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
380 return_format);
381
382 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
383 } else {
384 /* Non-constant sampler index. */
385 /* Note: this clobbers `dst` as a temporary before emitting the send */
386
387 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
388 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
389
390 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
391
392 brw_push_insn_state(p);
393 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
394 brw_set_default_access_mode(p, BRW_ALIGN_1);
395
396 /* Some care required: `sampler` and `temp` may alias:
397 * addr = sampler & 0xff
398 * temp = (sampler << 8) & 0xf00
399 * addr = addr | temp
400 */
401 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
402 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
403 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
404 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
405 brw_OR(p, addr, addr, temp);
406
407 /* a0.0 |= <descriptor> */
408 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
409 brw_set_sampler_message(p, insn_or,
410 0 /* surface */,
411 0 /* sampler */,
412 msg_type,
413 1 /* rlen */,
414 inst->mlen /* mlen */,
415 inst->header_present /* header */,
416 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
417 return_format);
418 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
419 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
420 brw_set_src0(p, insn_or, addr);
421 brw_set_dest(p, insn_or, addr);
422
423
424 /* dst = send(offset, a0.0) */
425 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
426 brw_set_dest(p, insn_send, dst);
427 brw_set_src0(p, insn_send, src);
428 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
429
430 brw_pop_insn_state(p);
431
432 /* visitor knows more than we do about the surface limit required,
433 * so has already done marking.
434 */
435 }
436 }
437
438 void
439 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
440 {
441 brw_urb_WRITE(p,
442 brw_null_reg(), /* dest */
443 inst->base_mrf, /* starting mrf reg nr */
444 brw_vec8_grf(0, 0), /* src */
445 inst->urb_write_flags,
446 inst->mlen,
447 0, /* response len */
448 inst->offset, /* urb destination offset */
449 BRW_URB_SWIZZLE_INTERLEAVE);
450 }
451
452 void
453 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
454 {
455 struct brw_reg src = brw_message_reg(inst->base_mrf);
456 brw_urb_WRITE(p,
457 brw_null_reg(), /* dest */
458 inst->base_mrf, /* starting mrf reg nr */
459 src,
460 inst->urb_write_flags,
461 inst->mlen,
462 0, /* response len */
463 inst->offset, /* urb destination offset */
464 BRW_URB_SWIZZLE_INTERLEAVE);
465 }
466
467 void
468 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
469 {
470 struct brw_reg src = brw_message_reg(inst->base_mrf);
471
472 /* We pass the temporary passed in src0 as the writeback register */
473 brw_urb_WRITE(p,
474 inst->get_src(this->prog_data, 0), /* dest */
475 inst->base_mrf, /* starting mrf reg nr */
476 src,
477 BRW_URB_WRITE_ALLOCATE_COMPLETE,
478 inst->mlen,
479 1, /* response len */
480 inst->offset, /* urb destination offset */
481 BRW_URB_SWIZZLE_INTERLEAVE);
482
483 /* Now put allocated urb handle in dst.0 */
484 brw_push_insn_state(p);
485 brw_set_default_access_mode(p, BRW_ALIGN_1);
486 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
487 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
488 get_element_ud(inst->get_src(this->prog_data, 0), 0));
489 brw_set_default_access_mode(p, BRW_ALIGN_16);
490 brw_pop_insn_state(p);
491 }
492
493 void
494 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
495 {
496 struct brw_reg src = brw_message_reg(inst->base_mrf);
497 brw_urb_WRITE(p,
498 brw_null_reg(), /* dest */
499 inst->base_mrf, /* starting mrf reg nr */
500 src,
501 BRW_URB_WRITE_EOT | inst->urb_write_flags,
502 brw->gen >= 8 ? 2 : 1,/* message len */
503 0, /* response len */
504 0, /* urb destination offset */
505 BRW_URB_SWIZZLE_INTERLEAVE);
506 }
507
508 void
509 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
510 struct brw_reg src0,
511 struct brw_reg src1)
512 {
513 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
514 * Header: M0.3):
515 *
516 * Slot 0 Offset. This field, after adding to the Global Offset field
517 * in the message descriptor, specifies the offset (in 256-bit units)
518 * from the start of the URB entry, as referenced by URB Handle 0, at
519 * which the data will be accessed.
520 *
521 * Similar text describes DWORD M0.4, which is slot 1 offset.
522 *
523 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
524 * of the register for geometry shader invocations 0 and 1) by the
525 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
526 *
527 * We can do this with the following EU instruction:
528 *
529 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
530 */
531 brw_push_insn_state(p);
532 brw_set_default_access_mode(p, BRW_ALIGN_1);
533 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
534 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
535 src1);
536 brw_set_default_access_mode(p, BRW_ALIGN_16);
537 brw_pop_insn_state(p);
538 }
539
540 void
541 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
542 struct brw_reg src)
543 {
544 brw_push_insn_state(p);
545 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
546
547 if (brw->gen >= 8) {
548 /* Move the vertex count into the second MRF for the EOT write. */
549 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
550 src);
551 } else {
552 /* If we think of the src and dst registers as composed of 8 DWORDs each,
553 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
554 * them to WORDs, and then pack them into DWORD 2 of dst.
555 *
556 * It's easier to get the EU to do this if we think of the src and dst
557 * registers as composed of 16 WORDS each; then, we want to pick up the
558 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
559 * of dst.
560 *
561 * We can do that by the following EU instruction:
562 *
563 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
564 */
565 brw_set_default_access_mode(p, BRW_ALIGN_1);
566 brw_MOV(p,
567 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
568 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
569 brw_set_default_access_mode(p, BRW_ALIGN_16);
570 }
571 brw_pop_insn_state(p);
572 }
573
574 void
575 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
576 struct brw_reg dst,
577 struct brw_reg src0,
578 struct brw_reg src1)
579 {
580 int binding = inst->sol_binding;
581 bool final_write = inst->sol_final_write;
582
583 brw_push_insn_state(p);
584 /* Copy Vertex data into M0.x */
585 brw_MOV(p, stride(dst, 4, 4, 1),
586 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
587
588 /* Send SVB Write */
589 brw_svb_write(p,
590 final_write ? src1 : brw_null_reg(), /* dest == src1 */
591 1, /* msg_reg_nr */
592 dst, /* src0 == previous dst */
593 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
594 final_write); /* send_commit_msg */
595
596 /* Finally, wait for the write commit to occur so that we can proceed to
597 * other things safely.
598 *
599 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
600 *
601 * The write commit does not modify the destination register, but
602 * merely clears the dependency associated with the destination
603 * register. Thus, a simple “mov” instruction using the register as a
604 * source is sufficient to wait for the write commit to occur.
605 */
606 if (final_write) {
607 brw_MOV(p, src1, src1);
608 }
609 brw_pop_insn_state(p);
610 }
611
612 void
613 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
614 struct brw_reg dst,
615 struct brw_reg src)
616 {
617
618 int vertex = inst->sol_vertex;
619 brw_push_insn_state(p);
620 brw_set_default_access_mode(p, BRW_ALIGN_1);
621 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
622 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
623 brw_pop_insn_state(p);
624 }
625
626 void
627 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
628 {
629 brw_push_insn_state(p);
630 brw_set_default_access_mode(p, BRW_ALIGN_1);
631 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
632 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
633 brw_pop_insn_state(p);
634 }
635
636 void
637 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
638 {
639 /* We want to left shift just DWORD 4 (the x component belonging to the
640 * second geometry shader invocation) by 4 bits. So generate the
641 * instruction:
642 *
643 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
644 */
645 dst = suboffset(vec1(dst), 4);
646 brw_push_insn_state(p);
647 brw_set_default_access_mode(p, BRW_ALIGN_1);
648 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
649 brw_SHL(p, dst, dst, brw_imm_ud(4));
650 brw_pop_insn_state(p);
651 }
652
653 void
654 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
655 struct brw_reg src)
656 {
657 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
658 * Header: M0.5):
659 *
660 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
661 *
662 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
663 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
664 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
665 * channel enable to determine the final channel enable. For the
666 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
667 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
668 * in the writeback message. For the URB_WRITE_OWORD &
669 * URB_WRITE_HWORD messages, when final channel enable is 1 it
670 * indicates that Vertex 1 DATA [3] will be written to the surface.
671 *
672 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
673 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
674 *
675 * 14 Vertex 1 DATA [2] Channel Mask
676 * 13 Vertex 1 DATA [1] Channel Mask
677 * 12 Vertex 1 DATA [0] Channel Mask
678 * 11 Vertex 0 DATA [3] Channel Mask
679 * 10 Vertex 0 DATA [2] Channel Mask
680 * 9 Vertex 0 DATA [1] Channel Mask
681 * 8 Vertex 0 DATA [0] Channel Mask
682 *
683 * (This is from a section of the PRM that is agnostic to the particular
684 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
685 * geometry shader invocations 0 and 1, respectively). Since we have the
686 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
687 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
688 * DWORD 4, we just need to OR them together and store the result in bits
689 * 15:8 of DWORD 5.
690 *
691 * It's easier to get the EU to do this if we think of the src and dst
692 * registers as composed of 32 bytes each; then, we want to pick up the
693 * contents of bytes 0 and 16 from src, OR them together, and store them in
694 * byte 21.
695 *
696 * We can do that by the following EU instruction:
697 *
698 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
699 *
700 * Note: this relies on the source register having zeros in (a) bits 7:4 of
701 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
702 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
703 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
704 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
705 * contain valid channel mask values (which are in the range 0x0-0xf).
706 */
707 dst = retype(dst, BRW_REGISTER_TYPE_UB);
708 src = retype(src, BRW_REGISTER_TYPE_UB);
709 brw_push_insn_state(p);
710 brw_set_default_access_mode(p, BRW_ALIGN_1);
711 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
712 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
713 brw_pop_insn_state(p);
714 }
715
716 void
717 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
718 {
719 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
720 * and store into dst.0 & dst.4. So generate the instruction:
721 *
722 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
723 */
724 brw_push_insn_state(p);
725 brw_set_default_access_mode(p, BRW_ALIGN_1);
726 dst = retype(dst, BRW_REGISTER_TYPE_UD);
727 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
728 brw_SHR(p, dst, stride(r0, 1, 4, 0),
729 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
730 brw_pop_insn_state(p);
731 }
732
733 void
734 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
735 struct brw_reg src0,
736 struct brw_reg src1,
737 struct brw_reg src2)
738 {
739 brw_push_insn_state(p);
740 brw_set_default_access_mode(p, BRW_ALIGN_1);
741 /* Save src0 data in 16:31 bits of dst.0 */
742 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
743 brw_imm_ud(0xffffu));
744 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
745 /* Save src1 data in 0:15 bits of dst.0 */
746 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
747 brw_imm_ud(0xffffu));
748 brw_OR(p, suboffset(vec1(dst), 0),
749 suboffset(vec1(dst), 0),
750 suboffset(vec1(src2), 0));
751 brw_pop_insn_state(p);
752 }
753
754 void
755 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
756 struct brw_reg dst,
757 struct brw_reg src0,
758 struct brw_reg src1)
759 {
760 /* This opcode uses an implied MRF register for:
761 * - the header of the ff_sync message. And as such it is expected to be
762 * initialized to r0 before calling here.
763 * - the destination where we will write the allocated URB handle.
764 */
765 struct brw_reg header =
766 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
767
768 /* Overwrite dword 0 of the header (SO vertices to write) and
769 * dword 1 (number of primitives written).
770 */
771 brw_push_insn_state(p);
772 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
773 brw_set_default_access_mode(p, BRW_ALIGN_1);
774 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
775 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
776 brw_pop_insn_state(p);
777
778 /* Allocate URB handle in dst */
779 brw_ff_sync(p,
780 dst,
781 0,
782 header,
783 1, /* allocate */
784 1, /* response length */
785 0 /* eot */);
786
787 /* Now put allocated urb handle in header.0 */
788 brw_push_insn_state(p);
789 brw_set_default_access_mode(p, BRW_ALIGN_1);
790 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
791 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
792
793 /* src1 is not an immediate when we use transform feedback */
794 if (src1.file != BRW_IMMEDIATE_VALUE)
795 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
796
797 brw_pop_insn_state(p);
798 }
799
800 void
801 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
802 {
803 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
804 struct brw_reg src = brw_vec8_grf(0, 0);
805 brw_push_insn_state(p);
806 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
807 brw_set_default_access_mode(p, BRW_ALIGN_1);
808 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
809 brw_pop_insn_state(p);
810 }
811
812 void
813 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
814 struct brw_reg index)
815 {
816 int second_vertex_offset;
817
818 if (brw->gen >= 6)
819 second_vertex_offset = 1;
820 else
821 second_vertex_offset = 16;
822
823 m1 = retype(m1, BRW_REGISTER_TYPE_D);
824
825 /* Set up M1 (message payload). Only the block offsets in M1.0 and
826 * M1.4 are used, and the rest are ignored.
827 */
828 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
829 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
830 struct brw_reg index_0 = suboffset(vec1(index), 0);
831 struct brw_reg index_4 = suboffset(vec1(index), 4);
832
833 brw_push_insn_state(p);
834 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
835 brw_set_default_access_mode(p, BRW_ALIGN_1);
836
837 brw_MOV(p, m1_0, index_0);
838
839 if (index.file == BRW_IMMEDIATE_VALUE) {
840 index_4.dw1.ud += second_vertex_offset;
841 brw_MOV(p, m1_4, index_4);
842 } else {
843 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
844 }
845
846 brw_pop_insn_state(p);
847 }
848
849 void
850 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
851 struct brw_reg dst)
852 {
853 brw_push_insn_state(p);
854 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
855 brw_set_default_access_mode(p, BRW_ALIGN_1);
856
857 struct brw_reg flags = brw_flag_reg(0, 0);
858 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
859 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
860
861 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
862 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
863 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
864
865 brw_pop_insn_state(p);
866 }
867
868 void
869 vec4_generator::generate_scratch_read(vec4_instruction *inst,
870 struct brw_reg dst,
871 struct brw_reg index)
872 {
873 struct brw_reg header = brw_vec8_grf(0, 0);
874
875 gen6_resolve_implied_move(p, &header, inst->base_mrf);
876
877 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
878 index);
879
880 uint32_t msg_type;
881
882 if (brw->gen >= 6)
883 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
884 else if (brw->gen == 5 || brw->is_g4x)
885 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
886 else
887 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
888
889 /* Each of the 8 channel enables is considered for whether each
890 * dword is written.
891 */
892 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
893 brw_set_dest(p, send, dst);
894 brw_set_src0(p, send, header);
895 if (brw->gen < 6)
896 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
897 brw_set_dp_read_message(p, send,
898 255, /* binding table index: stateless access */
899 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
900 msg_type,
901 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
902 2, /* mlen */
903 true, /* header_present */
904 1 /* rlen */);
905 }
906
907 void
908 vec4_generator::generate_scratch_write(vec4_instruction *inst,
909 struct brw_reg dst,
910 struct brw_reg src,
911 struct brw_reg index)
912 {
913 struct brw_reg header = brw_vec8_grf(0, 0);
914 bool write_commit;
915
916 /* If the instruction is predicated, we'll predicate the send, not
917 * the header setup.
918 */
919 brw_set_default_predicate_control(p, false);
920
921 gen6_resolve_implied_move(p, &header, inst->base_mrf);
922
923 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
924 index);
925
926 brw_MOV(p,
927 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
928 retype(src, BRW_REGISTER_TYPE_D));
929
930 uint32_t msg_type;
931
932 if (brw->gen >= 7)
933 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
934 else if (brw->gen == 6)
935 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
936 else
937 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
938
939 brw_set_default_predicate_control(p, inst->predicate);
940
941 /* Pre-gen6, we have to specify write commits to ensure ordering
942 * between reads and writes within a thread. Afterwards, that's
943 * guaranteed and write commits only matter for inter-thread
944 * synchronization.
945 */
946 if (brw->gen >= 6) {
947 write_commit = false;
948 } else {
949 /* The visitor set up our destination register to be g0. This
950 * means that when the next read comes along, we will end up
951 * reading from g0 and causing a block on the write commit. For
952 * write-after-read, we are relying on the value of the previous
953 * read being used (and thus blocking on completion) before our
954 * write is executed. This means we have to be careful in
955 * instruction scheduling to not violate this assumption.
956 */
957 write_commit = true;
958 }
959
960 /* Each of the 8 channel enables is considered for whether each
961 * dword is written.
962 */
963 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
964 brw_set_dest(p, send, dst);
965 brw_set_src0(p, send, header);
966 if (brw->gen < 6)
967 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
968 brw_set_dp_write_message(p, send,
969 255, /* binding table index: stateless access */
970 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
971 msg_type,
972 3, /* mlen */
973 true, /* header present */
974 false, /* not a render target write */
975 write_commit, /* rlen */
976 false, /* eot */
977 write_commit);
978 }
979
980 void
981 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
982 struct brw_reg dst,
983 struct brw_reg index,
984 struct brw_reg offset)
985 {
986 assert(index.file == BRW_IMMEDIATE_VALUE &&
987 index.type == BRW_REGISTER_TYPE_UD);
988 uint32_t surf_index = index.dw1.ud;
989
990 struct brw_reg header = brw_vec8_grf(0, 0);
991
992 gen6_resolve_implied_move(p, &header, inst->base_mrf);
993
994 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
995 offset);
996
997 uint32_t msg_type;
998
999 if (brw->gen >= 6)
1000 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1001 else if (brw->gen == 5 || brw->is_g4x)
1002 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1003 else
1004 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1005
1006 /* Each of the 8 channel enables is considered for whether each
1007 * dword is written.
1008 */
1009 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1010 brw_set_dest(p, send, dst);
1011 brw_set_src0(p, send, header);
1012 if (brw->gen < 6)
1013 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
1014 brw_set_dp_read_message(p, send,
1015 surf_index,
1016 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1017 msg_type,
1018 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1019 2, /* mlen */
1020 true, /* header_present */
1021 1 /* rlen */);
1022
1023 brw_mark_surface_used(&prog_data->base, surf_index);
1024 }
1025
1026 void
1027 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1028 struct brw_reg dst,
1029 struct brw_reg surf_index,
1030 struct brw_reg offset)
1031 {
1032 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1033
1034 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1035
1036 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1037 brw_set_dest(p, insn, dst);
1038 brw_set_src0(p, insn, offset);
1039 brw_set_sampler_message(p, insn,
1040 surf_index.dw1.ud,
1041 0, /* LD message ignores sampler unit */
1042 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1043 1, /* rlen */
1044 1, /* mlen */
1045 false, /* no header */
1046 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1047 0);
1048
1049 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1050
1051 } else {
1052
1053 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1054
1055 brw_push_insn_state(p);
1056 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1057 brw_set_default_access_mode(p, BRW_ALIGN_1);
1058
1059 /* a0.0 = surf_index & 0xff */
1060 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1061 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1062 brw_set_dest(p, insn_and, addr);
1063 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1064 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1065
1066
1067 /* a0.0 |= <descriptor> */
1068 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1069 brw_set_sampler_message(p, insn_or,
1070 0 /* surface */,
1071 0 /* sampler */,
1072 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1073 1 /* rlen */,
1074 1 /* mlen */,
1075 false /* header */,
1076 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1077 0);
1078 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1079 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1080 brw_set_src0(p, insn_or, addr);
1081 brw_set_dest(p, insn_or, addr);
1082
1083
1084 /* dst = send(offset, a0.0) */
1085 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1086 brw_set_dest(p, insn_send, dst);
1087 brw_set_src0(p, insn_send, offset);
1088 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1089
1090 brw_pop_insn_state(p);
1091
1092 /* visitor knows more than we do about the surface limit required,
1093 * so has already done marking.
1094 */
1095 }
1096 }
1097
1098 void
1099 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1100 struct brw_reg dst,
1101 struct brw_reg atomic_op,
1102 struct brw_reg surf_index)
1103 {
1104 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1105 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1106 surf_index.file == BRW_IMMEDIATE_VALUE &&
1107 surf_index.type == BRW_REGISTER_TYPE_UD);
1108
1109 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1110 atomic_op.dw1.ud, surf_index.dw1.ud,
1111 inst->mlen, 1);
1112
1113 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1114 }
1115
1116 void
1117 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1118 struct brw_reg dst,
1119 struct brw_reg surf_index)
1120 {
1121 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1122 surf_index.type == BRW_REGISTER_TYPE_UD);
1123
1124 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1125 surf_index.dw1.ud,
1126 inst->mlen, 1);
1127
1128 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1129 }
1130
1131 void
1132 vec4_generator::generate_code(const cfg_t *cfg)
1133 {
1134 struct annotation_info annotation;
1135 memset(&annotation, 0, sizeof(annotation));
1136 int loop_count = 0;
1137
1138 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1139 struct brw_reg src[3], dst;
1140
1141 if (unlikely(debug_flag))
1142 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1143
1144 for (unsigned int i = 0; i < 3; i++) {
1145 src[i] = inst->get_src(this->prog_data, i);
1146 }
1147 dst = inst->get_dst();
1148
1149 brw_set_default_predicate_control(p, inst->predicate);
1150 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1151 brw_set_default_saturate(p, inst->saturate);
1152 brw_set_default_mask_control(p, inst->force_writemask_all);
1153 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1154
1155 unsigned pre_emit_nr_insn = p->nr_insn;
1156
1157 if (dst.width == BRW_WIDTH_4) {
1158 /* This happens in attribute fixups for "dual instanced" geometry
1159 * shaders, since they use attributes that are vec4's. Since the exec
1160 * width is only 4, it's essential that the caller set
1161 * force_writemask_all in order to make sure the instruction is executed
1162 * regardless of which channels are enabled.
1163 */
1164 assert(inst->force_writemask_all);
1165
1166 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1167 * the following register region restrictions (from Graphics BSpec:
1168 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1169 * > Register Region Restrictions)
1170 *
1171 * 1. ExecSize must be greater than or equal to Width.
1172 *
1173 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1174 * to Width * HorzStride."
1175 */
1176 for (int i = 0; i < 3; i++) {
1177 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1178 src[i] = stride(src[i], 4, 4, 1);
1179 }
1180 }
1181
1182 switch (inst->opcode) {
1183 case BRW_OPCODE_MOV:
1184 brw_MOV(p, dst, src[0]);
1185 break;
1186 case BRW_OPCODE_ADD:
1187 brw_ADD(p, dst, src[0], src[1]);
1188 break;
1189 case BRW_OPCODE_MUL:
1190 brw_MUL(p, dst, src[0], src[1]);
1191 break;
1192 case BRW_OPCODE_MACH:
1193 brw_MACH(p, dst, src[0], src[1]);
1194 break;
1195
1196 case BRW_OPCODE_MAD:
1197 assert(brw->gen >= 6);
1198 brw_MAD(p, dst, src[0], src[1], src[2]);
1199 break;
1200
1201 case BRW_OPCODE_FRC:
1202 brw_FRC(p, dst, src[0]);
1203 break;
1204 case BRW_OPCODE_RNDD:
1205 brw_RNDD(p, dst, src[0]);
1206 break;
1207 case BRW_OPCODE_RNDE:
1208 brw_RNDE(p, dst, src[0]);
1209 break;
1210 case BRW_OPCODE_RNDZ:
1211 brw_RNDZ(p, dst, src[0]);
1212 break;
1213
1214 case BRW_OPCODE_AND:
1215 brw_AND(p, dst, src[0], src[1]);
1216 break;
1217 case BRW_OPCODE_OR:
1218 brw_OR(p, dst, src[0], src[1]);
1219 break;
1220 case BRW_OPCODE_XOR:
1221 brw_XOR(p, dst, src[0], src[1]);
1222 break;
1223 case BRW_OPCODE_NOT:
1224 brw_NOT(p, dst, src[0]);
1225 break;
1226 case BRW_OPCODE_ASR:
1227 brw_ASR(p, dst, src[0], src[1]);
1228 break;
1229 case BRW_OPCODE_SHR:
1230 brw_SHR(p, dst, src[0], src[1]);
1231 break;
1232 case BRW_OPCODE_SHL:
1233 brw_SHL(p, dst, src[0], src[1]);
1234 break;
1235
1236 case BRW_OPCODE_CMP:
1237 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1238 break;
1239 case BRW_OPCODE_SEL:
1240 brw_SEL(p, dst, src[0], src[1]);
1241 break;
1242
1243 case BRW_OPCODE_DPH:
1244 brw_DPH(p, dst, src[0], src[1]);
1245 break;
1246
1247 case BRW_OPCODE_DP4:
1248 brw_DP4(p, dst, src[0], src[1]);
1249 break;
1250
1251 case BRW_OPCODE_DP3:
1252 brw_DP3(p, dst, src[0], src[1]);
1253 break;
1254
1255 case BRW_OPCODE_DP2:
1256 brw_DP2(p, dst, src[0], src[1]);
1257 break;
1258
1259 case BRW_OPCODE_F32TO16:
1260 assert(brw->gen >= 7);
1261 brw_F32TO16(p, dst, src[0]);
1262 break;
1263
1264 case BRW_OPCODE_F16TO32:
1265 assert(brw->gen >= 7);
1266 brw_F16TO32(p, dst, src[0]);
1267 break;
1268
1269 case BRW_OPCODE_LRP:
1270 assert(brw->gen >= 6);
1271 brw_LRP(p, dst, src[0], src[1], src[2]);
1272 break;
1273
1274 case BRW_OPCODE_BFREV:
1275 assert(brw->gen >= 7);
1276 /* BFREV only supports UD type for src and dst. */
1277 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1278 retype(src[0], BRW_REGISTER_TYPE_UD));
1279 break;
1280 case BRW_OPCODE_FBH:
1281 assert(brw->gen >= 7);
1282 /* FBH only supports UD type for dst. */
1283 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1284 break;
1285 case BRW_OPCODE_FBL:
1286 assert(brw->gen >= 7);
1287 /* FBL only supports UD type for dst. */
1288 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1289 break;
1290 case BRW_OPCODE_CBIT:
1291 assert(brw->gen >= 7);
1292 /* CBIT only supports UD type for dst. */
1293 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1294 break;
1295 case BRW_OPCODE_ADDC:
1296 assert(brw->gen >= 7);
1297 brw_ADDC(p, dst, src[0], src[1]);
1298 break;
1299 case BRW_OPCODE_SUBB:
1300 assert(brw->gen >= 7);
1301 brw_SUBB(p, dst, src[0], src[1]);
1302 break;
1303 case BRW_OPCODE_MAC:
1304 brw_MAC(p, dst, src[0], src[1]);
1305 break;
1306
1307 case BRW_OPCODE_BFE:
1308 assert(brw->gen >= 7);
1309 brw_BFE(p, dst, src[0], src[1], src[2]);
1310 break;
1311
1312 case BRW_OPCODE_BFI1:
1313 assert(brw->gen >= 7);
1314 brw_BFI1(p, dst, src[0], src[1]);
1315 break;
1316 case BRW_OPCODE_BFI2:
1317 assert(brw->gen >= 7);
1318 brw_BFI2(p, dst, src[0], src[1], src[2]);
1319 break;
1320
1321 case BRW_OPCODE_IF:
1322 if (inst->src[0].file != BAD_FILE) {
1323 /* The instruction has an embedded compare (only allowed on gen6) */
1324 assert(brw->gen == 6);
1325 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1326 } else {
1327 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1328 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1329 }
1330 break;
1331
1332 case BRW_OPCODE_ELSE:
1333 brw_ELSE(p);
1334 break;
1335 case BRW_OPCODE_ENDIF:
1336 brw_ENDIF(p);
1337 break;
1338
1339 case BRW_OPCODE_DO:
1340 brw_DO(p, BRW_EXECUTE_8);
1341 break;
1342
1343 case BRW_OPCODE_BREAK:
1344 brw_BREAK(p);
1345 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1346 break;
1347 case BRW_OPCODE_CONTINUE:
1348 brw_CONT(p);
1349 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1350 break;
1351
1352 case BRW_OPCODE_WHILE:
1353 brw_WHILE(p);
1354 loop_count++;
1355 break;
1356
1357 case SHADER_OPCODE_RCP:
1358 case SHADER_OPCODE_RSQ:
1359 case SHADER_OPCODE_SQRT:
1360 case SHADER_OPCODE_EXP2:
1361 case SHADER_OPCODE_LOG2:
1362 case SHADER_OPCODE_SIN:
1363 case SHADER_OPCODE_COS:
1364 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1365 if (brw->gen >= 7) {
1366 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1367 brw_null_reg());
1368 } else if (brw->gen == 6) {
1369 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1370 } else {
1371 generate_math1_gen4(inst, dst, src[0]);
1372 }
1373 break;
1374
1375 case SHADER_OPCODE_POW:
1376 case SHADER_OPCODE_INT_QUOTIENT:
1377 case SHADER_OPCODE_INT_REMAINDER:
1378 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1379 if (brw->gen >= 7) {
1380 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1381 } else if (brw->gen == 6) {
1382 generate_math_gen6(inst, dst, src[0], src[1]);
1383 } else {
1384 generate_math2_gen4(inst, dst, src[0], src[1]);
1385 }
1386 break;
1387
1388 case SHADER_OPCODE_TEX:
1389 case SHADER_OPCODE_TXD:
1390 case SHADER_OPCODE_TXF:
1391 case SHADER_OPCODE_TXF_CMS:
1392 case SHADER_OPCODE_TXF_MCS:
1393 case SHADER_OPCODE_TXL:
1394 case SHADER_OPCODE_TXS:
1395 case SHADER_OPCODE_TG4:
1396 case SHADER_OPCODE_TG4_OFFSET:
1397 generate_tex(inst, dst, src[0], src[1]);
1398 break;
1399
1400 case VS_OPCODE_URB_WRITE:
1401 generate_vs_urb_write(inst);
1402 break;
1403
1404 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1405 generate_scratch_read(inst, dst, src[0]);
1406 break;
1407
1408 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1409 generate_scratch_write(inst, dst, src[0], src[1]);
1410 break;
1411
1412 case VS_OPCODE_PULL_CONSTANT_LOAD:
1413 generate_pull_constant_load(inst, dst, src[0], src[1]);
1414 break;
1415
1416 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1417 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1418 break;
1419
1420 case GS_OPCODE_URB_WRITE:
1421 generate_gs_urb_write(inst);
1422 break;
1423
1424 case GS_OPCODE_URB_WRITE_ALLOCATE:
1425 generate_gs_urb_write_allocate(inst);
1426 break;
1427
1428 case GS_OPCODE_SVB_WRITE:
1429 generate_gs_svb_write(inst, dst, src[0], src[1]);
1430 break;
1431
1432 case GS_OPCODE_SVB_SET_DST_INDEX:
1433 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1434 break;
1435
1436 case GS_OPCODE_THREAD_END:
1437 generate_gs_thread_end(inst);
1438 break;
1439
1440 case GS_OPCODE_SET_WRITE_OFFSET:
1441 generate_gs_set_write_offset(dst, src[0], src[1]);
1442 break;
1443
1444 case GS_OPCODE_SET_VERTEX_COUNT:
1445 generate_gs_set_vertex_count(dst, src[0]);
1446 break;
1447
1448 case GS_OPCODE_FF_SYNC:
1449 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1450 break;
1451
1452 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1453 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1454 break;
1455
1456 case GS_OPCODE_SET_PRIMITIVE_ID:
1457 generate_gs_set_primitive_id(dst);
1458 break;
1459
1460 case GS_OPCODE_SET_DWORD_2:
1461 generate_gs_set_dword_2(dst, src[0]);
1462 break;
1463
1464 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1465 generate_gs_prepare_channel_masks(dst);
1466 break;
1467
1468 case GS_OPCODE_SET_CHANNEL_MASKS:
1469 generate_gs_set_channel_masks(dst, src[0]);
1470 break;
1471
1472 case GS_OPCODE_GET_INSTANCE_ID:
1473 generate_gs_get_instance_id(dst);
1474 break;
1475
1476 case SHADER_OPCODE_SHADER_TIME_ADD:
1477 brw_shader_time_add(p, src[0],
1478 prog_data->base.binding_table.shader_time_start);
1479 brw_mark_surface_used(&prog_data->base,
1480 prog_data->base.binding_table.shader_time_start);
1481 break;
1482
1483 case SHADER_OPCODE_UNTYPED_ATOMIC:
1484 generate_untyped_atomic(inst, dst, src[0], src[1]);
1485 break;
1486
1487 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1488 generate_untyped_surface_read(inst, dst, src[0]);
1489 break;
1490
1491 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1492 generate_unpack_flags(inst, dst);
1493 break;
1494
1495 default:
1496 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1497 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1498 opcode_descs[inst->opcode].name);
1499 } else {
1500 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1501 }
1502 abort();
1503 }
1504
1505 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1506 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1507 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1508 "emitting more than 1 instruction");
1509
1510 brw_inst *last = &p->store[pre_emit_nr_insn];
1511
1512 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1513 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1514 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1515 }
1516 }
1517
1518 brw_set_uip_jip(p);
1519 annotation_finalize(&annotation, p->next_insn_offset);
1520
1521 int before_size = p->next_insn_offset;
1522 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1523 int after_size = p->next_insn_offset;
1524
1525 if (unlikely(debug_flag)) {
1526 if (shader_prog) {
1527 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1528 shader_prog->Label ? shader_prog->Label : "unnamed",
1529 shader_prog->Name);
1530 } else {
1531 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1532 }
1533 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1534 " bytes (%.0f%%)\n",
1535 before_size / 16, loop_count, before_size, after_size,
1536 100.0f * (before_size - after_size) / before_size);
1537
1538 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1539 ralloc_free(annotation.ann);
1540 }
1541 }
1542
1543 const unsigned *
1544 vec4_generator::generate_assembly(const cfg_t *cfg,
1545 unsigned *assembly_size)
1546 {
1547 brw_set_default_access_mode(p, BRW_ALIGN_16);
1548 generate_code(cfg);
1549
1550 return brw_get_program(p, assembly_size);
1551 }
1552
1553 } /* namespace brw */