1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
36 vec4_instruction::get_dst(void)
38 struct brw_reg brw_reg
;
42 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
43 brw_reg
= retype(brw_reg
, dst
.type
);
44 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
48 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
49 brw_reg
= retype(brw_reg
, dst
.type
);
50 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
54 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
55 brw_reg
= dst
.fixed_hw_reg
;
59 brw_reg
= brw_null_reg();
63 unreachable("not reached");
69 vec4_instruction::get_src(const struct brw_vec4_prog_data
*prog_data
, int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].fixed_hw_reg
.dw1
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].fixed_hw_reg
.dw1
.d
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].fixed_hw_reg
.dw1
.ud
);
96 unreachable("not reached");
101 brw_reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
102 (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
103 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
105 brw_reg
= retype(brw_reg
, src
[i
].type
);
106 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
108 brw_reg
= brw_abs(brw_reg
);
110 brw_reg
= negate(brw_reg
);
112 /* This should have been moved to pull constants. */
113 assert(!src
[i
].reladdr
);
117 assert(src
[i
].type
== src
[i
].fixed_hw_reg
.type
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 unreachable("not reached");
133 vec4_generator::vec4_generator(struct brw_context
*brw
,
134 struct gl_shader_program
*shader_prog
,
135 struct gl_program
*prog
,
136 struct brw_vec4_prog_data
*prog_data
,
139 : brw(brw
), shader_prog(shader_prog
), prog(prog
), prog_data(prog_data
),
140 mem_ctx(mem_ctx
), debug_flag(debug_flag
)
142 p
= rzalloc(mem_ctx
, struct brw_compile
);
143 brw_init_compile(brw
, p
, mem_ctx
);
146 vec4_generator::~vec4_generator()
151 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
157 brw_math_function(inst
->opcode
),
160 BRW_MATH_DATA_VECTOR
,
161 BRW_MATH_PRECISION_FULL
);
165 check_gen6_math_src_arg(struct brw_reg src
)
167 /* Source swizzles are ignored. */
170 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
174 vec4_generator::generate_math_gen6(vec4_instruction
*inst
,
179 /* Can't do writemask because math can't be align16. */
180 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
181 /* Source swizzles are ignored. */
182 check_gen6_math_src_arg(src0
);
183 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
184 check_gen6_math_src_arg(src1
);
186 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
187 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
188 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
192 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
197 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * "Operand1[7]. For the INT DIV functions, this operand is the
206 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
207 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
208 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
210 brw_push_insn_state(p
);
211 brw_set_default_saturate(p
, false);
212 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
213 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
214 brw_pop_insn_state(p
);
218 brw_math_function(inst
->opcode
),
221 BRW_MATH_DATA_VECTOR
,
222 BRW_MATH_PRECISION_FULL
);
226 vec4_generator::generate_tex(vec4_instruction
*inst
,
229 struct brw_reg sampler_index
)
234 switch (inst
->opcode
) {
235 case SHADER_OPCODE_TEX
:
236 case SHADER_OPCODE_TXL
:
237 if (inst
->shadow_compare
) {
238 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
240 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
243 case SHADER_OPCODE_TXD
:
244 if (inst
->shadow_compare
) {
245 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
246 assert(brw
->gen
>= 8 || brw
->is_haswell
);
247 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
249 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
252 case SHADER_OPCODE_TXF
:
253 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
255 case SHADER_OPCODE_TXF_CMS
:
257 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
259 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
261 case SHADER_OPCODE_TXF_MCS
:
262 assert(brw
->gen
>= 7);
263 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
265 case SHADER_OPCODE_TXS
:
266 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
268 case SHADER_OPCODE_TG4
:
269 if (inst
->shadow_compare
) {
270 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
272 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
275 case SHADER_OPCODE_TG4_OFFSET
:
276 if (inst
->shadow_compare
) {
277 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
279 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
283 unreachable("should not get here: invalid vec4 texture opcode");
286 switch (inst
->opcode
) {
287 case SHADER_OPCODE_TEX
:
288 case SHADER_OPCODE_TXL
:
289 if (inst
->shadow_compare
) {
290 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
291 assert(inst
->mlen
== 3);
293 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
294 assert(inst
->mlen
== 2);
297 case SHADER_OPCODE_TXD
:
298 /* There is no sample_d_c message; comparisons are done manually. */
299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
300 assert(inst
->mlen
== 4);
302 case SHADER_OPCODE_TXF
:
303 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
304 assert(inst
->mlen
== 2);
306 case SHADER_OPCODE_TXS
:
307 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
308 assert(inst
->mlen
== 2);
311 unreachable("should not get here: invalid vec4 texture opcode");
315 assert(msg_type
!= -1);
317 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
318 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
320 uint32_t sampler
= sampler_index
.dw1
.ud
;
322 /* Load the message header if present. If there's a texture offset, we need
323 * to set it up explicitly and load the offset bitfield. Otherwise, we can
324 * use an implied move from g0 to the first message register.
326 if (inst
->header_present
) {
327 if (brw
->gen
< 6 && !inst
->texture_offset
) {
328 /* Set up an implied move from g0 to the MRF. */
329 src
= brw_vec8_grf(0, 0);
331 struct brw_reg header
=
332 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
334 /* Explicitly set up the message header by copying g0 to the MRF. */
335 brw_push_insn_state(p
);
336 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
337 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
339 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
341 if (inst
->texture_offset
) {
342 /* Set the texel offset bits in DWord 2. */
343 brw_MOV(p
, get_element_ud(header
, 2),
344 brw_imm_ud(inst
->texture_offset
));
348 /* The "Sampler Index" field can only store values between 0 and 15.
349 * However, we can add an offset to the "Sampler State Pointer"
350 * field, effectively selecting a different set of 16 samplers.
352 * The "Sampler State Pointer" needs to be aligned to a 32-byte
353 * offset, and each sampler state is only 16-bytes, so we can't
354 * exclusively use the offset - we have to use both.
356 const int sampler_state_size
= 16; /* 16 bytes */
357 assert(brw
->gen
>= 8 || brw
->is_haswell
);
359 get_element_ud(header
, 3),
360 get_element_ud(brw_vec8_grf(0, 0), 3),
361 brw_imm_ud(16 * (sampler
/ 16) * sampler_state_size
));
363 brw_pop_insn_state(p
);
367 uint32_t return_format
;
370 case BRW_REGISTER_TYPE_D
:
371 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
373 case BRW_REGISTER_TYPE_UD
:
374 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
377 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
381 uint32_t surface_index
= ((inst
->opcode
== SHADER_OPCODE_TG4
||
382 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
383 ? prog_data
->base
.binding_table
.gather_texture_start
384 : prog_data
->base
.binding_table
.texture_start
) + sampler
;
393 1, /* response length */
395 inst
->header_present
,
396 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
399 brw_mark_surface_used(&prog_data
->base
, surface_index
);
403 vec4_generator::generate_vs_urb_write(vec4_instruction
*inst
)
406 brw_null_reg(), /* dest */
407 inst
->base_mrf
, /* starting mrf reg nr */
408 brw_vec8_grf(0, 0), /* src */
409 inst
->urb_write_flags
,
411 0, /* response len */
412 inst
->offset
, /* urb destination offset */
413 BRW_URB_SWIZZLE_INTERLEAVE
);
417 vec4_generator::generate_gs_urb_write(vec4_instruction
*inst
)
419 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
421 brw_null_reg(), /* dest */
422 inst
->base_mrf
, /* starting mrf reg nr */
424 inst
->urb_write_flags
,
426 0, /* response len */
427 inst
->offset
, /* urb destination offset */
428 BRW_URB_SWIZZLE_INTERLEAVE
);
432 vec4_generator::generate_gs_thread_end(vec4_instruction
*inst
)
434 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
436 brw_null_reg(), /* dest */
437 inst
->base_mrf
, /* starting mrf reg nr */
440 brw
->gen
>= 8 ? 2 : 1,/* message len */
441 0, /* response len */
442 0, /* urb destination offset */
443 BRW_URB_SWIZZLE_INTERLEAVE
);
447 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst
,
451 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
454 * Slot 0 Offset. This field, after adding to the Global Offset field
455 * in the message descriptor, specifies the offset (in 256-bit units)
456 * from the start of the URB entry, as referenced by URB Handle 0, at
457 * which the data will be accessed.
459 * Similar text describes DWORD M0.4, which is slot 1 offset.
461 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
462 * of the register for geometry shader invocations 0 and 1) by the
463 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
465 * We can do this with the following EU instruction:
467 * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
469 brw_push_insn_state(p
);
470 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
471 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
472 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
474 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
475 brw_pop_insn_state(p
);
479 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst
,
482 brw_push_insn_state(p
);
483 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
486 /* Move the vertex count into the second MRF for the EOT write. */
487 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
490 /* If we think of the src and dst registers as composed of 8 DWORDs each,
491 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
492 * them to WORDs, and then pack them into DWORD 2 of dst.
494 * It's easier to get the EU to do this if we think of the src and dst
495 * registers as composed of 16 WORDS each; then, we want to pick up the
496 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
499 * We can do that by the following EU instruction:
501 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
503 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
505 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
506 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
507 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
509 brw_pop_insn_state(p
);
513 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst
,
516 assert(src
.file
== BRW_IMMEDIATE_VALUE
);
518 brw_push_insn_state(p
);
519 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
520 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
521 brw_MOV(p
, suboffset(vec1(dst
), 2), src
);
522 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
523 brw_pop_insn_state(p
);
527 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst
)
529 /* We want to left shift just DWORD 4 (the x component belonging to the
530 * second geometry shader invocation) by 4 bits. So generate the
533 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
535 dst
= suboffset(vec1(dst
), 4);
536 brw_push_insn_state(p
);
537 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
538 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
539 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
540 brw_pop_insn_state(p
);
544 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst
,
547 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
550 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
552 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
553 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
554 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
555 * channel enable to determine the final channel enable. For the
556 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
557 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
558 * in the writeback message. For the URB_WRITE_OWORD &
559 * URB_WRITE_HWORD messages, when final channel enable is 1 it
560 * indicates that Vertex 1 DATA [3] will be written to the surface.
562 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
563 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
565 * 14 Vertex 1 DATA [2] Channel Mask
566 * 13 Vertex 1 DATA [1] Channel Mask
567 * 12 Vertex 1 DATA [0] Channel Mask
568 * 11 Vertex 0 DATA [3] Channel Mask
569 * 10 Vertex 0 DATA [2] Channel Mask
570 * 9 Vertex 0 DATA [1] Channel Mask
571 * 8 Vertex 0 DATA [0] Channel Mask
573 * (This is from a section of the PRM that is agnostic to the particular
574 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
575 * geometry shader invocations 0 and 1, respectively). Since we have the
576 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
577 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
578 * DWORD 4, we just need to OR them together and store the result in bits
581 * It's easier to get the EU to do this if we think of the src and dst
582 * registers as composed of 32 bytes each; then, we want to pick up the
583 * contents of bytes 0 and 16 from src, OR them together, and store them in
586 * We can do that by the following EU instruction:
588 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
590 * Note: this relies on the source register having zeros in (a) bits 7:4 of
591 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
592 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
593 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
594 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
595 * contain valid channel mask values (which are in the range 0x0-0xf).
597 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
598 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
599 brw_push_insn_state(p
);
600 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
601 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
602 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
603 brw_pop_insn_state(p
);
607 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst
)
609 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
610 * and store into dst.0 & dst.4. So generate the instruction:
612 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
614 brw_push_insn_state(p
);
615 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
616 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
617 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
618 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
619 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
620 brw_pop_insn_state(p
);
624 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
625 struct brw_reg index
)
627 int second_vertex_offset
;
630 second_vertex_offset
= 1;
632 second_vertex_offset
= 16;
634 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
636 /* Set up M1 (message payload). Only the block offsets in M1.0 and
637 * M1.4 are used, and the rest are ignored.
639 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
640 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
641 struct brw_reg index_0
= suboffset(vec1(index
), 0);
642 struct brw_reg index_4
= suboffset(vec1(index
), 4);
644 brw_push_insn_state(p
);
645 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
646 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
648 brw_MOV(p
, m1_0
, index_0
);
650 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
651 index_4
.dw1
.ud
+= second_vertex_offset
;
652 brw_MOV(p
, m1_4
, index_4
);
654 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
657 brw_pop_insn_state(p
);
661 vec4_generator::generate_unpack_flags(vec4_instruction
*inst
,
664 brw_push_insn_state(p
);
665 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
666 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
668 struct brw_reg flags
= brw_flag_reg(0, 0);
669 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
670 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
672 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
673 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
674 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
676 brw_pop_insn_state(p
);
680 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
682 struct brw_reg index
)
684 struct brw_reg header
= brw_vec8_grf(0, 0);
686 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
688 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
694 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
695 else if (brw
->gen
== 5 || brw
->is_g4x
)
696 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
698 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
700 /* Each of the 8 channel enables is considered for whether each
703 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
704 brw_set_dest(p
, send
, dst
);
705 brw_set_src0(p
, send
, header
);
707 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
708 brw_set_dp_read_message(p
, send
,
709 255, /* binding table index: stateless access */
710 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
712 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
714 true, /* header_present */
719 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
722 struct brw_reg index
)
724 struct brw_reg header
= brw_vec8_grf(0, 0);
727 /* If the instruction is predicated, we'll predicate the send, not
730 brw_set_default_predicate_control(p
, false);
732 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
734 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
738 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
739 retype(src
, BRW_REGISTER_TYPE_D
));
744 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
745 else if (brw
->gen
== 6)
746 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
748 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
750 brw_set_default_predicate_control(p
, inst
->predicate
);
752 /* Pre-gen6, we have to specify write commits to ensure ordering
753 * between reads and writes within a thread. Afterwards, that's
754 * guaranteed and write commits only matter for inter-thread
758 write_commit
= false;
760 /* The visitor set up our destination register to be g0. This
761 * means that when the next read comes along, we will end up
762 * reading from g0 and causing a block on the write commit. For
763 * write-after-read, we are relying on the value of the previous
764 * read being used (and thus blocking on completion) before our
765 * write is executed. This means we have to be careful in
766 * instruction scheduling to not violate this assumption.
771 /* Each of the 8 channel enables is considered for whether each
774 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
775 brw_set_dest(p
, send
, dst
);
776 brw_set_src0(p
, send
, header
);
778 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
779 brw_set_dp_write_message(p
, send
,
780 255, /* binding table index: stateless access */
781 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
784 true, /* header present */
785 false, /* not a render target write */
786 write_commit
, /* rlen */
792 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
794 struct brw_reg index
,
795 struct brw_reg offset
)
797 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
798 index
.type
== BRW_REGISTER_TYPE_UD
);
799 uint32_t surf_index
= index
.dw1
.ud
;
801 struct brw_reg header
= brw_vec8_grf(0, 0);
803 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
805 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
811 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
812 else if (brw
->gen
== 5 || brw
->is_g4x
)
813 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
815 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
817 /* Each of the 8 channel enables is considered for whether each
820 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
821 brw_set_dest(p
, send
, dst
);
822 brw_set_src0(p
, send
, header
);
824 brw_inst_set_cond_modifier(brw
, send
, inst
->base_mrf
);
825 brw_set_dp_read_message(p
, send
,
827 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
829 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
831 true, /* header_present */
834 brw_mark_surface_used(&prog_data
->base
, surf_index
);
838 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
840 struct brw_reg surf_index
,
841 struct brw_reg offset
)
843 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
844 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
846 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
847 brw_set_dest(p
, insn
, dst
);
848 brw_set_src0(p
, insn
, offset
);
849 brw_set_sampler_message(p
, insn
,
851 0, /* LD message ignores sampler unit */
852 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
855 false, /* no header */
856 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
859 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
863 vec4_generator::generate_untyped_atomic(vec4_instruction
*inst
,
865 struct brw_reg atomic_op
,
866 struct brw_reg surf_index
)
868 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
869 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
870 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
871 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
873 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
874 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
877 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
881 vec4_generator::generate_untyped_surface_read(vec4_instruction
*inst
,
883 struct brw_reg surf_index
)
885 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
886 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
888 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
892 brw_mark_surface_used(&prog_data
->base
, surf_index
.dw1
.ud
);
896 * Generate assembly for a Vec4 IR instruction.
898 * \param instruction The Vec4 IR instruction to generate code for.
899 * \param dst The destination register.
900 * \param src An array of up to three source registers.
903 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
907 vec4_instruction
*inst
= (vec4_instruction
*) instruction
;
909 if (dst
.width
== BRW_WIDTH_4
) {
910 /* This happens in attribute fixups for "dual instanced" geometry
911 * shaders, since they use attributes that are vec4's. Since the exec
912 * width is only 4, it's essential that the caller set
913 * force_writemask_all in order to make sure the instruction is executed
914 * regardless of which channels are enabled.
916 assert(inst
->force_writemask_all
);
918 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
919 * the following register region restrictions (from Graphics BSpec:
920 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
921 * > Register Region Restrictions)
923 * 1. ExecSize must be greater than or equal to Width.
925 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
926 * to Width * HorzStride."
928 for (int i
= 0; i
< 3; i
++) {
929 if (src
[i
].file
== BRW_GENERAL_REGISTER_FILE
)
930 src
[i
] = stride(src
[i
], 4, 4, 1);
934 switch (inst
->opcode
) {
936 brw_MOV(p
, dst
, src
[0]);
939 brw_ADD(p
, dst
, src
[0], src
[1]);
942 brw_MUL(p
, dst
, src
[0], src
[1]);
944 case BRW_OPCODE_MACH
:
945 brw_MACH(p
, dst
, src
[0], src
[1]);
949 assert(brw
->gen
>= 6);
950 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
954 brw_FRC(p
, dst
, src
[0]);
956 case BRW_OPCODE_RNDD
:
957 brw_RNDD(p
, dst
, src
[0]);
959 case BRW_OPCODE_RNDE
:
960 brw_RNDE(p
, dst
, src
[0]);
962 case BRW_OPCODE_RNDZ
:
963 brw_RNDZ(p
, dst
, src
[0]);
967 brw_AND(p
, dst
, src
[0], src
[1]);
970 brw_OR(p
, dst
, src
[0], src
[1]);
973 brw_XOR(p
, dst
, src
[0], src
[1]);
976 brw_NOT(p
, dst
, src
[0]);
979 brw_ASR(p
, dst
, src
[0], src
[1]);
982 brw_SHR(p
, dst
, src
[0], src
[1]);
985 brw_SHL(p
, dst
, src
[0], src
[1]);
989 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
992 brw_SEL(p
, dst
, src
[0], src
[1]);
996 brw_DPH(p
, dst
, src
[0], src
[1]);
1000 brw_DP4(p
, dst
, src
[0], src
[1]);
1003 case BRW_OPCODE_DP3
:
1004 brw_DP3(p
, dst
, src
[0], src
[1]);
1007 case BRW_OPCODE_DP2
:
1008 brw_DP2(p
, dst
, src
[0], src
[1]);
1011 case BRW_OPCODE_F32TO16
:
1012 assert(brw
->gen
>= 7);
1013 brw_F32TO16(p
, dst
, src
[0]);
1016 case BRW_OPCODE_F16TO32
:
1017 assert(brw
->gen
>= 7);
1018 brw_F16TO32(p
, dst
, src
[0]);
1021 case BRW_OPCODE_LRP
:
1022 assert(brw
->gen
>= 6);
1023 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1026 case BRW_OPCODE_BFREV
:
1027 assert(brw
->gen
>= 7);
1028 /* BFREV only supports UD type for src and dst. */
1029 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1030 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1032 case BRW_OPCODE_FBH
:
1033 assert(brw
->gen
>= 7);
1034 /* FBH only supports UD type for dst. */
1035 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1037 case BRW_OPCODE_FBL
:
1038 assert(brw
->gen
>= 7);
1039 /* FBL only supports UD type for dst. */
1040 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1042 case BRW_OPCODE_CBIT
:
1043 assert(brw
->gen
>= 7);
1044 /* CBIT only supports UD type for dst. */
1045 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1047 case BRW_OPCODE_ADDC
:
1048 assert(brw
->gen
>= 7);
1049 brw_ADDC(p
, dst
, src
[0], src
[1]);
1051 case BRW_OPCODE_SUBB
:
1052 assert(brw
->gen
>= 7);
1053 brw_SUBB(p
, dst
, src
[0], src
[1]);
1055 case BRW_OPCODE_MAC
:
1056 brw_MAC(p
, dst
, src
[0], src
[1]);
1059 case BRW_OPCODE_BFE
:
1060 assert(brw
->gen
>= 7);
1061 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1064 case BRW_OPCODE_BFI1
:
1065 assert(brw
->gen
>= 7);
1066 brw_BFI1(p
, dst
, src
[0], src
[1]);
1068 case BRW_OPCODE_BFI2
:
1069 assert(brw
->gen
>= 7);
1070 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1074 if (inst
->src
[0].file
!= BAD_FILE
) {
1075 /* The instruction has an embedded compare (only allowed on gen6) */
1076 assert(brw
->gen
== 6);
1077 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1079 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1080 brw_inst_set_pred_control(brw
, if_inst
, inst
->predicate
);
1084 case BRW_OPCODE_ELSE
:
1087 case BRW_OPCODE_ENDIF
:
1092 brw_DO(p
, BRW_EXECUTE_8
);
1095 case BRW_OPCODE_BREAK
:
1097 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1099 case BRW_OPCODE_CONTINUE
:
1101 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1104 case BRW_OPCODE_WHILE
:
1108 case SHADER_OPCODE_RCP
:
1109 case SHADER_OPCODE_RSQ
:
1110 case SHADER_OPCODE_SQRT
:
1111 case SHADER_OPCODE_EXP2
:
1112 case SHADER_OPCODE_LOG2
:
1113 case SHADER_OPCODE_SIN
:
1114 case SHADER_OPCODE_COS
:
1115 if (brw
->gen
>= 7) {
1116 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1118 } else if (brw
->gen
== 6) {
1119 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1121 generate_math1_gen4(inst
, dst
, src
[0]);
1125 case SHADER_OPCODE_POW
:
1126 case SHADER_OPCODE_INT_QUOTIENT
:
1127 case SHADER_OPCODE_INT_REMAINDER
:
1128 if (brw
->gen
>= 7) {
1129 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1130 } else if (brw
->gen
== 6) {
1131 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1133 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
1137 case SHADER_OPCODE_TEX
:
1138 case SHADER_OPCODE_TXD
:
1139 case SHADER_OPCODE_TXF
:
1140 case SHADER_OPCODE_TXF_CMS
:
1141 case SHADER_OPCODE_TXF_MCS
:
1142 case SHADER_OPCODE_TXL
:
1143 case SHADER_OPCODE_TXS
:
1144 case SHADER_OPCODE_TG4
:
1145 case SHADER_OPCODE_TG4_OFFSET
:
1146 generate_tex(inst
, dst
, src
[0], src
[1]);
1149 case VS_OPCODE_URB_WRITE
:
1150 generate_vs_urb_write(inst
);
1153 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1154 generate_scratch_read(inst
, dst
, src
[0]);
1157 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1158 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
1161 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1162 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1165 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1166 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1169 case GS_OPCODE_URB_WRITE
:
1170 generate_gs_urb_write(inst
);
1173 case GS_OPCODE_THREAD_END
:
1174 generate_gs_thread_end(inst
);
1177 case GS_OPCODE_SET_WRITE_OFFSET
:
1178 generate_gs_set_write_offset(dst
, src
[0], src
[1]);
1181 case GS_OPCODE_SET_VERTEX_COUNT
:
1182 generate_gs_set_vertex_count(dst
, src
[0]);
1185 case GS_OPCODE_SET_DWORD_2_IMMED
:
1186 generate_gs_set_dword_2_immed(dst
, src
[0]);
1189 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1190 generate_gs_prepare_channel_masks(dst
);
1193 case GS_OPCODE_SET_CHANNEL_MASKS
:
1194 generate_gs_set_channel_masks(dst
, src
[0]);
1197 case GS_OPCODE_GET_INSTANCE_ID
:
1198 generate_gs_get_instance_id(dst
);
1201 case SHADER_OPCODE_SHADER_TIME_ADD
:
1202 brw_shader_time_add(p
, src
[0],
1203 prog_data
->base
.binding_table
.shader_time_start
);
1204 brw_mark_surface_used(&prog_data
->base
,
1205 prog_data
->base
.binding_table
.shader_time_start
);
1208 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1209 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1212 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1213 generate_untyped_surface_read(inst
, dst
, src
[0]);
1216 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1217 generate_unpack_flags(inst
, dst
);
1221 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1222 _mesa_problem(&brw
->ctx
, "Unsupported opcode in `%s' in vec4\n",
1223 opcode_descs
[inst
->opcode
].name
);
1225 _mesa_problem(&brw
->ctx
, "Unsupported opcode %d in vec4", inst
->opcode
);
1232 vec4_generator::generate_code(exec_list
*instructions
)
1234 struct annotation_info annotation
;
1235 memset(&annotation
, 0, sizeof(annotation
));
1238 if (unlikely(debug_flag
))
1239 cfg
= new(mem_ctx
) cfg_t(instructions
);
1241 foreach_in_list(vec4_instruction
, inst
, instructions
) {
1242 struct brw_reg src
[3], dst
;
1244 if (unlikely(debug_flag
))
1245 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1247 for (unsigned int i
= 0; i
< 3; i
++) {
1248 src
[i
] = inst
->get_src(this->prog_data
, i
);
1250 dst
= inst
->get_dst();
1252 brw_set_default_predicate_control(p
, inst
->predicate
);
1253 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1254 brw_set_default_saturate(p
, inst
->saturate
);
1255 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1256 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1258 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1260 generate_vec4_instruction(inst
, dst
, src
);
1262 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1263 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
1264 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1265 "emitting more than 1 instruction");
1267 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
1269 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1270 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1271 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1276 annotation_finalize(&annotation
, p
->next_insn_offset
);
1278 int before_size
= p
->next_insn_offset
;
1279 brw_compact_instructions(p
, 0, annotation
.ann_count
, annotation
.ann
);
1280 int after_size
= p
->next_insn_offset
;
1282 if (unlikely(debug_flag
)) {
1284 fprintf(stderr
, "Native code for %s vertex shader %d:\n",
1285 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1288 fprintf(stderr
, "Native code for vertex program %d:\n", prog
->Id
);
1290 fprintf(stderr
, "vec4 shader: %d instructions. Compacted %d to %d"
1291 " bytes (%.0f%%)\n",
1292 before_size
/ 16, before_size
, after_size
,
1293 100.0f
* (before_size
- after_size
) / before_size
);
1295 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
1296 ralloc_free(annotation
.ann
);
1301 vec4_generator::generate_assembly(exec_list
*instructions
,
1302 unsigned *assembly_size
)
1304 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1305 generate_code(instructions
);
1307 return brw_get_program(p
, assembly_size
);
1310 } /* namespace brw */