src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_vec4_gs_visitor.h"
  26
  27 namespace brw {
  28
  29 void
  30 vec4_gs_visitor::nir_setup_inputs()
  31 {
  32 }
  33
  34 void
  35 vec4_gs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  36 {
  37    dst_reg *reg;
  38
  39    switch (instr->intrinsic) {
  40    case nir_intrinsic_load_primitive_id:
  41       /* We'll just read g1 directly; don't create a temporary. */
  42       break;
  43
  44    case nir_intrinsic_load_invocation_id:
  45       reg = &this->nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
  46       if (reg->file == BAD_FILE)
  47          *reg = *this->make_reg_for_system_value(SYSTEM_VALUE_INVOCATION_ID,
  48                                                  glsl_type::int_type);
  49       break;
  50
  51    default:
  52       vec4_visitor::nir_setup_system_value_intrinsic(instr);
  53    }
  54
  55 }
  56
  57 void
  58 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
  59 {
  60    dst_reg dest;
  61    src_reg src;
  62
  63    switch (instr->intrinsic) {
  64    case nir_intrinsic_load_per_vertex_input_indirect:
  65       assert(!"EmitNoIndirectInput should prevent this.");
  66    case nir_intrinsic_load_per_vertex_input: {
  67       /* The EmitNoIndirectInput flag guarantees our vertex index will
  68        * be constant.  We should handle indirects someday.
  69        */
  70       nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
  71
  72       /* Make up a type...we have no way of knowing... */
  73       const glsl_type *const type = glsl_type::ivec(instr->num_components);
  74
  75       src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u[0] +
  76                           instr->const_index[0], type);
  77       dest = get_nir_dest(instr->dest, src.type);
  78       dest.writemask = brw_writemask_for_size(instr->num_components);
  79       emit(MOV(dest, src));
  80       break;
  81    }
  82
  83    case nir_intrinsic_load_input:
  84    case nir_intrinsic_load_input_indirect:
  85       unreachable("nir_lower_io should have produced per_vertex intrinsics");
  86
  87    case nir_intrinsic_emit_vertex_with_counter: {
  88       this->vertex_count =
  89          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
  90       int stream_id = instr->const_index[0];
  91       gs_emit_vertex(stream_id);
  92       break;
  93    }
  94
  95    case nir_intrinsic_end_primitive_with_counter:
  96       this->vertex_count =
  97          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
  98       gs_end_primitive();
  99       break;
 100
 101    case nir_intrinsic_set_vertex_count:
 102       this->vertex_count =
 103          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
 104       break;
 105
 106    case nir_intrinsic_load_primitive_id:
 107       assert(c->prog_data.include_primitive_id);
 108       dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 109       emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D)));
 110       break;
 111
 112    case nir_intrinsic_load_invocation_id: {
 113       src_reg invocation_id =
 114          src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]);
 115       assert(invocation_id.file != BAD_FILE);
 116       dest = get_nir_dest(instr->dest, invocation_id.type);
 117       emit(MOV(dest, invocation_id));
 118       break;
 119    }
 120
 121    default:
 122       vec4_visitor::nir_emit_intrinsic(instr);
 123    }
 124 }
 125 }