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25 * \file brw_vec4_gs_visitor.cpp
27 * Geometry-shader-specific code derived from the vec4_visitor class.
30 #include "brw_vec4_gs_visitor.h"
31 #include "gen6_gs_visitor.h"
37 vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler
*compiler
,
39 struct brw_gs_compile
*c
,
40 struct brw_gs_prog_data
*prog_data
,
41 const nir_shader
*shader
,
44 int shader_time_index
)
45 : vec4_visitor(compiler
, log_data
, &c
->key
.tex
,
46 &prog_data
->base
, shader
, mem_ctx
,
47 no_spills
, shader_time_index
),
49 gs_prog_data(prog_data
)
55 vec4_gs_visitor::make_reg_for_system_value(int location
,
56 const glsl_type
*type
)
58 dst_reg
*reg
= new(mem_ctx
) dst_reg(this, type
);
61 case SYSTEM_VALUE_INVOCATION_ID
:
62 this->current_annotation
= "initialize gl_InvocationID";
63 emit(GS_OPCODE_GET_INSTANCE_ID
, *reg
);
66 unreachable("not reached");
74 vec4_gs_visitor::setup_varying_inputs(int payload_reg
, int *attribute_map
,
75 int attributes_per_reg
)
77 /* For geometry shaders there are N copies of the input attributes, where N
78 * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT *
79 * i + j] represents attribute j for vertex i.
81 * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time,
82 * so the total number of input slots that will be delivered to the GS (and
83 * thus the stride of the input arrays) is urb_read_length * 2.
85 const unsigned num_input_vertices
= nir
->info
.gs
.vertices_in
;
86 assert(num_input_vertices
<= MAX_GS_INPUT_VERTICES
);
87 unsigned input_array_stride
= prog_data
->urb_read_length
* 2;
89 for (int slot
= 0; slot
< c
->input_vue_map
.num_slots
; slot
++) {
90 int varying
= c
->input_vue_map
.slot_to_varying
[slot
];
91 for (unsigned vertex
= 0; vertex
< num_input_vertices
; vertex
++) {
92 attribute_map
[BRW_VARYING_SLOT_COUNT
* vertex
+ varying
] =
93 attributes_per_reg
* payload_reg
+ input_array_stride
* vertex
+
98 int regs_used
= ALIGN(input_array_stride
* num_input_vertices
,
99 attributes_per_reg
) / attributes_per_reg
;
100 return payload_reg
+ regs_used
;
105 vec4_gs_visitor::setup_payload()
107 int attribute_map
[BRW_VARYING_SLOT_COUNT
* MAX_GS_INPUT_VERTICES
];
109 /* If we are in dual instanced or single mode, then attributes are going
110 * to be interleaved, so one register contains two attribute slots.
112 int attributes_per_reg
=
113 prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
? 1 : 2;
115 /* If a geometry shader tries to read from an input that wasn't written by
116 * the vertex shader, that produces undefined results, but it shouldn't
117 * crash anything. So initialize attribute_map to zeros--that ensures that
118 * these undefined results are read from r0.
120 memset(attribute_map
, 0, sizeof(attribute_map
));
124 /* The payload always contains important data in r0, which contains
125 * the URB handles that are passed on to the URB write at the end
130 /* If the shader uses gl_PrimitiveIDIn, that goes in r1. */
131 if (gs_prog_data
->include_primitive_id
)
132 attribute_map
[VARYING_SLOT_PRIMITIVE_ID
] = attributes_per_reg
* reg
++;
134 reg
= setup_uniforms(reg
);
136 reg
= setup_varying_inputs(reg
, attribute_map
, attributes_per_reg
);
138 lower_attributes_to_hw_regs(attribute_map
, attributes_per_reg
> 1);
140 this->first_non_payload_grf
= reg
;
145 vec4_gs_visitor::emit_prolog()
147 /* In vertex shaders, r0.2 is guaranteed to be initialized to zero. In
148 * geometry shaders, it isn't (it contains a bunch of information we don't
149 * need, like the input primitive type). We need r0.2 to be zero in order
150 * to build scratch read/write messages correctly (otherwise this value
151 * will be interpreted as a global offset, causing us to do our scratch
152 * reads/writes to garbage memory). So just set it to zero at the top of
155 this->current_annotation
= "clear r0.2";
156 dst_reg
r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD
));
157 vec4_instruction
*inst
= emit(GS_OPCODE_SET_DWORD_2
, r0
, brw_imm_ud(0u));
158 inst
->force_writemask_all
= true;
160 /* Create a virtual register to hold the vertex count */
161 this->vertex_count
= src_reg(this, glsl_type::uint_type
);
163 /* Initialize the vertex_count register to 0 */
164 this->current_annotation
= "initialize vertex_count";
165 inst
= emit(MOV(dst_reg(this->vertex_count
), brw_imm_ud(0u)));
166 inst
->force_writemask_all
= true;
168 if (c
->control_data_header_size_bits
> 0) {
169 /* Create a virtual register to hold the current set of control data
172 this->control_data_bits
= src_reg(this, glsl_type::uint_type
);
174 /* If we're outputting more than 32 control data bits, then EmitVertex()
175 * will set control_data_bits to 0 after emitting the first vertex.
176 * Otherwise, we need to initialize it to 0 here.
178 if (c
->control_data_header_size_bits
<= 32) {
179 this->current_annotation
= "initialize control data bits";
180 inst
= emit(MOV(dst_reg(this->control_data_bits
), brw_imm_ud(0u)));
181 inst
->force_writemask_all
= true;
185 /* If the geometry shader uses the gl_PointSize input, we need to fix it up
186 * to account for the fact that the vertex shader stored it in the w
187 * component of VARYING_SLOT_PSIZ.
189 if (nir
->info
.inputs_read
& VARYING_BIT_PSIZ
) {
190 this->current_annotation
= "swizzle gl_PointSize input";
191 for (int vertex
= 0; vertex
< (int)nir
->info
.gs
.vertices_in
; vertex
++) {
193 BRW_VARYING_SLOT_COUNT
* vertex
+ VARYING_SLOT_PSIZ
);
194 dst
.type
= BRW_REGISTER_TYPE_F
;
196 dst
.writemask
= WRITEMASK_X
;
197 src
.swizzle
= BRW_SWIZZLE_WWWW
;
198 inst
= emit(MOV(dst
, src
));
200 /* In dual instanced dispatch mode, dst has a width of 4, so we need
201 * to make sure the MOV happens regardless of which channels are
204 inst
->force_writemask_all
= true;
208 this->current_annotation
= NULL
;
212 vec4_gs_visitor::emit_thread_end()
214 if (c
->control_data_header_size_bits
> 0) {
215 /* During shader execution, we only ever call emit_control_data_bits()
216 * just prior to outputting a vertex. Therefore, the control data bits
217 * corresponding to the most recently output vertex still need to be
220 current_annotation
= "thread end: emit control data bits";
221 emit_control_data_bits();
224 /* MRF 0 is reserved for the debugger, so start with message header
229 bool static_vertex_count
= gs_prog_data
->static_vertex_count
!= -1;
231 /* If the previous instruction was a URB write, we don't need to issue
232 * a second one - we can just set the EOT bit on the previous write.
234 * Skip this on Gen8+ unless there's a static vertex count, as we also
235 * need to write the vertex count out, and combining the two may not be
236 * possible (or at least not straightforward).
238 vec4_instruction
*last
= (vec4_instruction
*) instructions
.get_tail();
239 if (last
&& last
->opcode
== GS_OPCODE_URB_WRITE
&&
240 !(INTEL_DEBUG
& DEBUG_SHADER_TIME
) &&
241 devinfo
->gen
>= 8 && static_vertex_count
) {
242 last
->urb_write_flags
= BRW_URB_WRITE_EOT
| last
->urb_write_flags
;
246 current_annotation
= "thread end";
247 dst_reg
mrf_reg(MRF
, base_mrf
);
248 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
249 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
250 inst
->force_writemask_all
= true;
251 if (devinfo
->gen
< 8 || !static_vertex_count
)
252 emit(GS_OPCODE_SET_VERTEX_COUNT
, mrf_reg
, this->vertex_count
);
253 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
254 emit_shader_time_end();
255 inst
= emit(GS_OPCODE_THREAD_END
);
256 inst
->base_mrf
= base_mrf
;
257 inst
->mlen
= devinfo
->gen
>= 8 && !static_vertex_count
? 2 : 1;
262 vec4_gs_visitor::emit_urb_write_header(int mrf
)
264 /* The SEND instruction that writes the vertex data to the VUE will use
265 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message
266 * header specify an offset (in multiples of 256 bits) into the URB entry
267 * at which the write should take place.
269 * So we have to prepare a message header with the appropriate offset
272 dst_reg
mrf_reg(MRF
, mrf
);
273 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
274 this->current_annotation
= "URB write header";
275 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
276 inst
->force_writemask_all
= true;
277 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, this->vertex_count
,
278 brw_imm_ud(gs_prog_data
->output_vertex_size_hwords
));
283 vec4_gs_visitor::emit_urb_write_opcode(bool complete
)
285 /* We don't care whether the vertex is complete, because in general
286 * geometry shaders output multiple vertices, and we don't terminate the
287 * thread until all vertices are complete.
291 vec4_instruction
*inst
= emit(GS_OPCODE_URB_WRITE
);
292 inst
->offset
= gs_prog_data
->control_data_header_size_hwords
;
294 /* We need to increment Global Offset by 1 to make room for Broadwell's
295 * extra "Vertex Count" payload at the beginning of the URB entry.
297 if (devinfo
->gen
>= 8 && gs_prog_data
->static_vertex_count
== -1)
300 inst
->urb_write_flags
= BRW_URB_WRITE_PER_SLOT_OFFSET
;
306 * Write out a batch of 32 control data bits from the control_data_bits
307 * register to the URB.
309 * The current value of the vertex_count register determines which DWORD in
310 * the URB receives the control data bits. The control_data_bits register is
311 * assumed to contain the correct data for the vertex that was most recently
312 * output, and all previous vertices that share the same DWORD.
314 * This function takes care of ensuring that if no vertices have been output
315 * yet, no control bits are emitted.
318 vec4_gs_visitor::emit_control_data_bits()
320 assert(c
->control_data_bits_per_vertex
!= 0);
322 /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized)
323 * granularity, we need to use two tricks to ensure that the batch of 32
324 * control data bits is written to the appropriate DWORD in the URB. To
325 * select which vec4 we are writing to, we use the "slot {0,1} offset"
326 * fields of the message header. To select which DWORD in the vec4 we are
327 * writing to, we use the channel mask fields of the message header. To
328 * avoid penalizing geometry shaders that emit a small number of vertices
329 * with extra bookkeeping, we only do each of these tricks when
330 * c->prog_data.control_data_header_size_bits is large enough to make it
333 * Note: this means that if we're outputting just a single DWORD of control
334 * data bits, we'll actually replicate it four times since we won't do any
335 * channel masking. But that's not a problem since in this case the
336 * hardware only pays attention to the first DWORD.
338 enum brw_urb_write_flags urb_write_flags
= BRW_URB_WRITE_OWORD
;
339 if (c
->control_data_header_size_bits
> 32)
340 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_USE_CHANNEL_MASKS
;
341 if (c
->control_data_header_size_bits
> 128)
342 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_PER_SLOT_OFFSET
;
344 /* If we are using either channel masks or a per-slot offset, then we
345 * need to figure out which DWORD we are trying to write to, using the
348 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
350 * Since bits_per_vertex is a power of two, and is known at compile
351 * time, this can be optimized to:
353 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
355 src_reg
dword_index(this, glsl_type::uint_type
);
356 if (urb_write_flags
) {
357 src_reg
prev_count(this, glsl_type::uint_type
);
358 emit(ADD(dst_reg(prev_count
), this->vertex_count
,
359 brw_imm_ud(0xffffffffu
)));
360 unsigned log2_bits_per_vertex
=
361 _mesa_fls(c
->control_data_bits_per_vertex
);
362 emit(SHR(dst_reg(dword_index
), prev_count
,
363 brw_imm_ud(6 - log2_bits_per_vertex
)));
366 /* Start building the URB write message. The first MRF gets a copy of
370 dst_reg
mrf_reg(MRF
, base_mrf
);
371 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
372 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
373 inst
->force_writemask_all
= true;
375 if (urb_write_flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
) {
376 /* Set the per-slot offset to dword_index / 4, to that we'll write to
377 * the appropriate OWORD within the control data header.
379 src_reg
per_slot_offset(this, glsl_type::uint_type
);
380 emit(SHR(dst_reg(per_slot_offset
), dword_index
, brw_imm_ud(2u)));
381 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, per_slot_offset
,
385 if (urb_write_flags
& BRW_URB_WRITE_USE_CHANNEL_MASKS
) {
386 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
387 * write to the appropriate DWORD within the OWORD. We need to do
388 * this computation with force_writemask_all, otherwise garbage data
389 * from invocation 0 might clobber the mask for invocation 1 when
390 * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
393 src_reg
channel(this, glsl_type::uint_type
);
394 inst
= emit(AND(dst_reg(channel
), dword_index
, brw_imm_ud(3u)));
395 inst
->force_writemask_all
= true;
396 src_reg
one(this, glsl_type::uint_type
);
397 inst
= emit(MOV(dst_reg(one
), brw_imm_ud(1u)));
398 inst
->force_writemask_all
= true;
399 src_reg
channel_mask(this, glsl_type::uint_type
);
400 inst
= emit(SHL(dst_reg(channel_mask
), one
, channel
));
401 inst
->force_writemask_all
= true;
402 emit(GS_OPCODE_PREPARE_CHANNEL_MASKS
, dst_reg(channel_mask
),
404 emit(GS_OPCODE_SET_CHANNEL_MASKS
, mrf_reg
, channel_mask
);
407 /* Store the control data bits in the message payload and send it. */
408 dst_reg
mrf_reg2(MRF
, base_mrf
+ 1);
409 inst
= emit(MOV(mrf_reg2
, this->control_data_bits
));
410 inst
->force_writemask_all
= true;
411 inst
= emit(GS_OPCODE_URB_WRITE
);
412 inst
->urb_write_flags
= urb_write_flags
;
413 /* We need to increment Global Offset by 256-bits to make room for
414 * Broadwell's extra "Vertex Count" payload at the beginning of the
415 * URB entry. Since this is an OWord message, Global Offset is counted
416 * in 128-bit units, so we must set it to 2.
418 if (devinfo
->gen
>= 8 && gs_prog_data
->static_vertex_count
== -1)
420 inst
->base_mrf
= base_mrf
;
425 vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id
)
427 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
429 /* Note: we are calling this *before* increasing vertex_count, so
430 * this->vertex_count == vertex_count - 1 in the formula above.
433 /* Stream mode uses 2 bits per vertex */
434 assert(c
->control_data_bits_per_vertex
== 2);
436 /* Must be a valid stream */
437 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
439 /* Control data bits are initialized to 0 so we don't have to set any
440 * bits when sending vertices to stream 0.
445 /* reg::sid = stream_id */
446 src_reg
sid(this, glsl_type::uint_type
);
447 emit(MOV(dst_reg(sid
), brw_imm_ud(stream_id
)));
449 /* reg:shift_count = 2 * (vertex_count - 1) */
450 src_reg
shift_count(this, glsl_type::uint_type
);
451 emit(SHL(dst_reg(shift_count
), this->vertex_count
, brw_imm_ud(1u)));
453 /* Note: we're relying on the fact that the GEN SHL instruction only pays
454 * attention to the lower 5 bits of its second source argument, so on this
455 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
456 * stream_id << ((2 * (vertex_count - 1)) % 32).
458 src_reg
mask(this, glsl_type::uint_type
);
459 emit(SHL(dst_reg(mask
), sid
, shift_count
));
460 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
464 vec4_gs_visitor::gs_emit_vertex(int stream_id
)
466 this->current_annotation
= "emit vertex: safety check";
468 /* Haswell and later hardware ignores the "Render Stream Select" bits
469 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
470 * and instead sends all primitives down the pipeline for rasterization.
471 * If the SOL stage is enabled, "Render Stream Select" is honored and
472 * primitives bound to non-zero streams are discarded after stream output.
474 * Since the only purpose of primives sent to non-zero streams is to
475 * be recorded by transform feedback, we can simply discard all geometry
476 * bound to these streams when transform feedback is disabled.
478 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
481 /* If we're outputting 32 control data bits or less, then we can wait
482 * until the shader is over to output them all. Otherwise we need to
483 * output them as we go. Now is the time to do it, since we're about to
484 * output the vertex_count'th vertex, so it's guaranteed that the
485 * control data bits associated with the (vertex_count - 1)th vertex are
488 if (c
->control_data_header_size_bits
> 32) {
489 this->current_annotation
= "emit vertex: emit control data bits";
490 /* Only emit control data bits if we've finished accumulating a batch
491 * of 32 bits. This is the case when:
493 * (vertex_count * bits_per_vertex) % 32 == 0
495 * (in other words, when the last 5 bits of vertex_count *
496 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
497 * integer n (which is always the case, since bits_per_vertex is
498 * always 1 or 2), this is equivalent to requiring that the last 5-n
499 * bits of vertex_count are 0:
501 * vertex_count & (2^(5-n) - 1) == 0
503 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
506 * vertex_count & (32 / bits_per_vertex - 1) == 0
508 vec4_instruction
*inst
=
509 emit(AND(dst_null_ud(), this->vertex_count
,
510 brw_imm_ud(32 / c
->control_data_bits_per_vertex
- 1)));
511 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
513 emit(IF(BRW_PREDICATE_NORMAL
));
515 /* If vertex_count is 0, then no control data bits have been
516 * accumulated yet, so we skip emitting them.
518 emit(CMP(dst_null_ud(), this->vertex_count
, brw_imm_ud(0u),
519 BRW_CONDITIONAL_NEQ
));
520 emit(IF(BRW_PREDICATE_NORMAL
));
521 emit_control_data_bits();
522 emit(BRW_OPCODE_ENDIF
);
524 /* Reset control_data_bits to 0 so we can start accumulating a new
527 * Note: in the case where vertex_count == 0, this neutralizes the
528 * effect of any call to EndPrimitive() that the shader may have
529 * made before outputting its first vertex.
531 inst
= emit(MOV(dst_reg(this->control_data_bits
), brw_imm_ud(0u)));
532 inst
->force_writemask_all
= true;
534 emit(BRW_OPCODE_ENDIF
);
537 this->current_annotation
= "emit vertex: vertex data";
540 /* In stream mode we have to set control data bits for all vertices
541 * unless we have disabled control data bits completely (which we do
542 * do for GL_POINTS outputs that don't use streams).
544 if (c
->control_data_header_size_bits
> 0 &&
545 gs_prog_data
->control_data_format
==
546 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
547 this->current_annotation
= "emit vertex: Stream control data bits";
548 set_stream_control_data_bits(stream_id
);
551 this->current_annotation
= NULL
;
555 vec4_gs_visitor::gs_end_primitive()
557 /* We can only do EndPrimitive() functionality when the control data
558 * consists of cut bits. Fortunately, the only time it isn't is when the
559 * output type is points, in which case EndPrimitive() is a no-op.
561 if (gs_prog_data
->control_data_format
!=
562 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
566 /* Cut bits use one bit per vertex. */
567 assert(c
->control_data_bits_per_vertex
== 1);
569 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
570 * vertex n, 0 otherwise. So all we need to do here is mark bit
571 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
572 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
573 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
575 * Note that if EndPrimitve() is called before emitting any vertices, this
576 * will cause us to set bit 31 of the control_data_bits register to 1.
577 * That's fine because:
579 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
580 * output, so the hardware will ignore cut bit 31.
582 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
583 * last vertex, so setting cut bit 31 has no effect (since the primitive
584 * is automatically ended when the GS terminates).
586 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
587 * control_data_bits register to 0 when the first vertex is emitted.
590 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
591 src_reg
one(this, glsl_type::uint_type
);
592 emit(MOV(dst_reg(one
), brw_imm_ud(1u)));
593 src_reg
prev_count(this, glsl_type::uint_type
);
594 emit(ADD(dst_reg(prev_count
), this->vertex_count
, brw_imm_ud(0xffffffffu
)));
595 src_reg
mask(this, glsl_type::uint_type
);
596 /* Note: we're relying on the fact that the GEN SHL instruction only pays
597 * attention to the lower 5 bits of its second source argument, so on this
598 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
599 * ((vertex_count - 1) % 32).
601 emit(SHL(dst_reg(mask
), one
, prev_count
));
602 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
605 extern "C" const unsigned *
606 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
608 const struct brw_gs_prog_key
*key
,
609 struct brw_gs_prog_data
*prog_data
,
610 const nir_shader
*src_shader
,
611 struct gl_shader_program
*shader_prog
,
612 int shader_time_index
,
613 unsigned *final_assembly_size
,
616 struct brw_gs_compile c
;
617 memset(&c
, 0, sizeof(c
));
620 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
621 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
,
622 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
]);
624 prog_data
->include_primitive_id
=
625 (shader
->info
.inputs_read
& VARYING_BIT_PRIMITIVE_ID
) != 0;
627 prog_data
->invocations
= shader
->info
.gs
.invocations
;
629 if (compiler
->devinfo
->gen
>= 8)
630 prog_data
->static_vertex_count
= nir_gs_count_vertices(shader
);
632 if (compiler
->devinfo
->gen
>= 7) {
633 if (shader
->info
.gs
.output_primitive
== GL_POINTS
) {
634 /* When the output type is points, the geometry shader may output data
635 * to multiple streams, and EndPrimitive() has no effect. So we
636 * configure the hardware to interpret the control data as stream ID.
638 prog_data
->control_data_format
= GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
;
640 /* We only have to emit control bits if we are using streams */
641 if (shader_prog
&& shader_prog
->Geom
.UsesStreams
)
642 c
.control_data_bits_per_vertex
= 2;
644 c
.control_data_bits_per_vertex
= 0;
646 /* When the output type is triangle_strip or line_strip, EndPrimitive()
647 * may be used to terminate the current strip and start a new one
648 * (similar to primitive restart), and outputting data to multiple
649 * streams is not supported. So we configure the hardware to interpret
650 * the control data as EndPrimitive information (a.k.a. "cut bits").
652 prog_data
->control_data_format
= GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
;
654 /* We only need to output control data if the shader actually calls
657 c
.control_data_bits_per_vertex
=
658 shader
->info
.gs
.uses_end_primitive
? 1 : 0;
661 /* There are no control data bits in gen6. */
662 c
.control_data_bits_per_vertex
= 0;
664 /* If it is using transform feedback, enable it */
665 if (shader
->info
.has_transform_feedback_varyings
)
666 prog_data
->gen6_xfb_enabled
= true;
668 prog_data
->gen6_xfb_enabled
= false;
670 c
.control_data_header_size_bits
=
671 shader
->info
.gs
.vertices_out
* c
.control_data_bits_per_vertex
;
673 /* 1 HWORD = 32 bytes = 256 bits */
674 prog_data
->control_data_header_size_hwords
=
675 ALIGN(c
.control_data_header_size_bits
, 256) / 256;
677 /* Compute the output vertex size.
679 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 STATE_GS - Output Vertex
682 * [0,62] indicating [1,63] 16B units
684 * Specifies the size of each vertex stored in the GS output entry
685 * (following any Control Header data) as a number of 128-bit units
688 * Programming Restrictions: The vertex size must be programmed as a
689 * multiple of 32B units with the following exception: Rendering is
690 * disabled (as per SOL stage state) and the vertex size output by the
693 * If rendering is enabled (as per SOL state) the vertex size must be
694 * programmed as a multiple of 32B units. In other words, the only time
695 * software can program a vertex size with an odd number of 16B units
696 * is when rendering is disabled.
698 * Note: B=bytes in the above text.
700 * It doesn't seem worth the extra trouble to optimize the case where the
701 * vertex size is 16B (especially since this would require special-casing
702 * the GEN assembly that writes to the URB). So we just set the vertex
703 * size to a multiple of 32B (2 vec4's) in all cases.
705 * The maximum output vertex size is 62*16 = 992 bytes (31 hwords). We
706 * budget that as follows:
708 * 512 bytes for varyings (a varying component is 4 bytes and
709 * gl_MaxGeometryOutputComponents = 128)
710 * 16 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
712 * 16 bytes overhead for gl_Position (we allocate it a slot in the VUE
713 * even if it's not used)
714 * 32 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
715 * whenever clip planes are enabled, even if the shader doesn't
716 * write to gl_ClipDistance)
717 * 16 bytes overhead since the VUE size must be a multiple of 32 bytes
718 * (see below)--this causes up to 1 VUE slot to be wasted
719 * 400 bytes available for varying packing overhead
721 * Worst-case varying packing overhead is 3/4 of a varying slot (12 bytes)
722 * per interpolation type, so this is plenty.
725 unsigned output_vertex_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 16;
726 assert(compiler
->devinfo
->gen
== 6 ||
727 output_vertex_size_bytes
<= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES
);
728 prog_data
->output_vertex_size_hwords
=
729 ALIGN(output_vertex_size_bytes
, 32) / 32;
731 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
732 * That divides up as follows:
734 * 64 bytes for the control data header (cut indices or StreamID bits)
735 * 4096 bytes for varyings (a varying component is 4 bytes and
736 * gl_MaxGeometryTotalOutputComponents = 1024)
737 * 4096 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
738 * bytes/vertex and gl_MaxGeometryOutputVertices is 256)
739 * 4096 bytes overhead for gl_Position (we allocate it a slot in the VUE
740 * even if it's not used)
741 * 8192 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
742 * whenever clip planes are enabled, even if the shader doesn't
743 * write to gl_ClipDistance)
744 * 4096 bytes overhead since the VUE size must be a multiple of 32
745 * bytes (see above)--this causes up to 1 VUE slot to be wasted
746 * 8128 bytes available for varying packing overhead
748 * Worst-case varying packing overhead is 3/4 of a varying slot per
749 * interpolation type, which works out to 3072 bytes, so this would allow
750 * us to accommodate 2 interpolation types without any danger of running
753 * In practice, the risk of running out of URB space is very small, since
754 * the above figures are all worst-case, and most of them scale with the
755 * number of output vertices. So we'll just calculate the amount of space
756 * we need, and if it's too large, fail to compile.
758 * The above is for gen7+ where we have a single URB entry that will hold
759 * all the output. In gen6, we will have to allocate URB entries for every
760 * vertex we emit, so our URB entries only need to be large enough to hold
761 * a single vertex. Also, gen6 does not have a control data header.
763 unsigned output_size_bytes
;
764 if (compiler
->devinfo
->gen
>= 7) {
766 prog_data
->output_vertex_size_hwords
* 32 * shader
->info
.gs
.vertices_out
;
767 output_size_bytes
+= 32 * prog_data
->control_data_header_size_hwords
;
769 output_size_bytes
= prog_data
->output_vertex_size_hwords
* 32;
772 /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output,
773 * which comes before the control header.
775 if (compiler
->devinfo
->gen
>= 8)
776 output_size_bytes
+= 32;
778 assert(output_size_bytes
>= 1);
779 unsigned max_output_size_bytes
= GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES
;
780 if (compiler
->devinfo
->gen
== 6)
781 max_output_size_bytes
= GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES
;
782 if (output_size_bytes
> max_output_size_bytes
)
786 /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and
787 * a multiple of 128 bytes in gen6.
789 if (compiler
->devinfo
->gen
>= 7)
790 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
792 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 128) / 128;
794 prog_data
->output_topology
=
795 get_hw_prim_for_gl_prim(shader
->info
.gs
.output_primitive
);
797 /* The GLSL linker will have already matched up GS inputs and the outputs
798 * of prior stages. The driver does extend VS outputs in some cases, but
799 * only for legacy OpenGL or Gen4-5 hardware, neither of which offer
800 * geometry shader support. So we can safely ignore that.
802 * For SSO pipelines, we use a fixed VUE map layout based on variable
803 * locations, so we can rely on rendezvous-by-location making this work.
805 * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not
806 * written by previous stages and shows up via payload magic.
808 GLbitfield64 inputs_read
=
809 shader
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
;
810 brw_compute_vue_map(compiler
->devinfo
,
811 &c
.input_vue_map
, inputs_read
,
812 shader
->info
.separate_shader
);
814 /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
815 * need to program a URB read length of ceiling(num_slots / 2).
817 prog_data
->base
.urb_read_length
= (c
.input_vue_map
.num_slots
+ 1) / 2;
819 /* Now that prog_data setup is done, we are ready to actually compile the
822 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
823 fprintf(stderr
, "GS Input ");
824 brw_print_vue_map(stderr
, &c
.input_vue_map
);
825 fprintf(stderr
, "GS Output ");
826 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
829 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
]) {
830 /* TODO: Support instanced GS. We have basically no tests... */
831 assert(prog_data
->invocations
== 1);
833 fs_visitor
v(compiler
, log_data
, mem_ctx
, &c
, prog_data
, shader
,
836 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
838 fs_generator
g(compiler
, log_data
, mem_ctx
, &c
.key
,
839 &prog_data
->base
.base
, v
.promoted_constants
,
841 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
843 shader
->info
.label
? shader
->info
.label
: "unnamed";
844 char *name
= ralloc_asprintf(mem_ctx
, "%s geometry shader %s",
845 label
, shader
->info
.name
);
846 g
.enable_debug(name
);
848 g
.generate_code(v
.cfg
, 8);
849 return g
.get_assembly(final_assembly_size
);
853 if (compiler
->devinfo
->gen
>= 7) {
854 /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
855 * so without spilling. If the GS invocations count > 1, then we can't use
858 if (prog_data
->invocations
<= 1 &&
859 likely(!(INTEL_DEBUG
& DEBUG_NO_DUAL_OBJECT_GS
))) {
860 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
862 vec4_gs_visitor
v(compiler
, log_data
, &c
, prog_data
, shader
,
863 mem_ctx
, true /* no_spills */, shader_time_index
);
865 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
866 shader
, &prog_data
->base
, v
.cfg
,
867 final_assembly_size
);
872 /* Either we failed to compile in DUAL_OBJECT mode (probably because it
873 * would have required spilling) or DUAL_OBJECT mode is disabled. So fall
874 * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers.
876 * FIXME: Single dispatch mode requires that the driver can handle
877 * interleaving of input registers, but this is already supported (dual
878 * instance mode has the same requirement). However, to take full advantage
879 * of single dispatch mode to reduce register pressure we would also need to
880 * do interleaved outputs, but currently, the vec4 visitor and generator
881 * classes do not support this, so at the moment register pressure in
882 * single and dual instance modes is the same.
884 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS"
885 * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely
886 * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode
887 * is also supported. When InstanceCount=1 (one instance per object) software
888 * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be
889 * the best choice for performance, followed by SINGLE mode."
891 * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE
892 * mode is more performant when invocations > 1. Gen6 only supports
895 if (prog_data
->invocations
<= 1 || compiler
->devinfo
->gen
< 7)
896 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X1_SINGLE
;
898 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_INSTANCE
;
900 vec4_gs_visitor
*gs
= NULL
;
901 const unsigned *ret
= NULL
;
903 if (compiler
->devinfo
->gen
>= 7)
904 gs
= new vec4_gs_visitor(compiler
, log_data
, &c
, prog_data
,
905 shader
, mem_ctx
, false /* no_spills */,
908 gs
= new gen6_gs_visitor(compiler
, log_data
, &c
, prog_data
, shader_prog
,
909 shader
, mem_ctx
, false /* no_spills */,
914 *error_str
= ralloc_strdup(mem_ctx
, gs
->fail_msg
);
916 ret
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, shader
,
917 &prog_data
->base
, gs
->cfg
,
918 final_assembly_size
);
926 } /* namespace brw */