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25 * \file brw_vec4_gs_visitor.cpp
27 * Geometry-shader-specific code derived from the vec4_visitor class.
30 #include "brw_vec4_gs_visitor.h"
31 #include "gen6_gs_visitor.h"
33 const unsigned MAX_GS_INPUT_VERTICES
= 6;
37 vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler
*compiler
,
39 struct brw_gs_compile
*c
,
40 struct gl_shader_program
*prog
,
43 int shader_time_index
)
44 : vec4_visitor(compiler
, log_data
,
45 &c
->gp
->program
.Base
, &c
->key
.tex
,
46 &c
->prog_data
.base
, prog
, MESA_SHADER_GEOMETRY
, mem_ctx
,
47 no_spills
, shader_time_index
),
54 vec4_gs_visitor::make_reg_for_system_value(int location
,
55 const glsl_type
*type
)
57 dst_reg
*reg
= new(mem_ctx
) dst_reg(this, type
);
60 case SYSTEM_VALUE_INVOCATION_ID
:
61 this->current_annotation
= "initialize gl_InvocationID";
62 emit(GS_OPCODE_GET_INSTANCE_ID
, *reg
);
65 unreachable("not reached");
73 vec4_gs_visitor::setup_varying_inputs(int payload_reg
, int *attribute_map
,
74 int attributes_per_reg
)
76 /* For geometry shaders there are N copies of the input attributes, where N
77 * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT *
78 * i + j] represents attribute j for vertex i.
80 * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time,
81 * so the total number of input slots that will be delivered to the GS (and
82 * thus the stride of the input arrays) is urb_read_length * 2.
84 const unsigned num_input_vertices
= c
->gp
->program
.VerticesIn
;
85 assert(num_input_vertices
<= MAX_GS_INPUT_VERTICES
);
86 unsigned input_array_stride
= c
->prog_data
.base
.urb_read_length
* 2;
88 for (int slot
= 0; slot
< c
->input_vue_map
.num_slots
; slot
++) {
89 int varying
= c
->input_vue_map
.slot_to_varying
[slot
];
90 for (unsigned vertex
= 0; vertex
< num_input_vertices
; vertex
++) {
91 attribute_map
[BRW_VARYING_SLOT_COUNT
* vertex
+ varying
] =
92 attributes_per_reg
* payload_reg
+ input_array_stride
* vertex
+
97 int regs_used
= ALIGN(input_array_stride
* num_input_vertices
,
98 attributes_per_reg
) / attributes_per_reg
;
99 return payload_reg
+ regs_used
;
104 vec4_gs_visitor::setup_payload()
106 int attribute_map
[BRW_VARYING_SLOT_COUNT
* MAX_GS_INPUT_VERTICES
];
108 /* If we are in dual instanced or single mode, then attributes are going
109 * to be interleaved, so one register contains two attribute slots.
111 int attributes_per_reg
=
112 c
->prog_data
.base
.dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
? 1 : 2;
114 /* If a geometry shader tries to read from an input that wasn't written by
115 * the vertex shader, that produces undefined results, but it shouldn't
116 * crash anything. So initialize attribute_map to zeros--that ensures that
117 * these undefined results are read from r0.
119 memset(attribute_map
, 0, sizeof(attribute_map
));
123 /* The payload always contains important data in r0, which contains
124 * the URB handles that are passed on to the URB write at the end
129 /* If the shader uses gl_PrimitiveIDIn, that goes in r1. */
130 if (c
->prog_data
.include_primitive_id
)
131 attribute_map
[VARYING_SLOT_PRIMITIVE_ID
] = attributes_per_reg
* reg
++;
133 reg
= setup_uniforms(reg
);
135 reg
= setup_varying_inputs(reg
, attribute_map
, attributes_per_reg
);
137 lower_attributes_to_hw_regs(attribute_map
, attributes_per_reg
> 1);
139 this->first_non_payload_grf
= reg
;
144 vec4_gs_visitor::emit_prolog()
146 /* In vertex shaders, r0.2 is guaranteed to be initialized to zero. In
147 * geometry shaders, it isn't (it contains a bunch of information we don't
148 * need, like the input primitive type). We need r0.2 to be zero in order
149 * to build scratch read/write messages correctly (otherwise this value
150 * will be interpreted as a global offset, causing us to do our scratch
151 * reads/writes to garbage memory). So just set it to zero at the top of
154 this->current_annotation
= "clear r0.2";
155 dst_reg
r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD
));
156 vec4_instruction
*inst
= emit(GS_OPCODE_SET_DWORD_2
, r0
, 0u);
157 inst
->force_writemask_all
= true;
159 /* Create a virtual register to hold the vertex count */
160 this->vertex_count
= src_reg(this, glsl_type::uint_type
);
162 /* Initialize the vertex_count register to 0 */
163 this->current_annotation
= "initialize vertex_count";
164 inst
= emit(MOV(dst_reg(this->vertex_count
), 0u));
165 inst
->force_writemask_all
= true;
167 if (c
->control_data_header_size_bits
> 0) {
168 /* Create a virtual register to hold the current set of control data
171 this->control_data_bits
= src_reg(this, glsl_type::uint_type
);
173 /* If we're outputting more than 32 control data bits, then EmitVertex()
174 * will set control_data_bits to 0 after emitting the first vertex.
175 * Otherwise, we need to initialize it to 0 here.
177 if (c
->control_data_header_size_bits
<= 32) {
178 this->current_annotation
= "initialize control data bits";
179 inst
= emit(MOV(dst_reg(this->control_data_bits
), 0u));
180 inst
->force_writemask_all
= true;
184 /* If the geometry shader uses the gl_PointSize input, we need to fix it up
185 * to account for the fact that the vertex shader stored it in the w
186 * component of VARYING_SLOT_PSIZ.
188 if (c
->gp
->program
.Base
.InputsRead
& VARYING_BIT_PSIZ
) {
189 this->current_annotation
= "swizzle gl_PointSize input";
190 for (int vertex
= 0; vertex
< c
->gp
->program
.VerticesIn
; vertex
++) {
192 BRW_VARYING_SLOT_COUNT
* vertex
+ VARYING_SLOT_PSIZ
);
193 dst
.type
= BRW_REGISTER_TYPE_F
;
195 dst
.writemask
= WRITEMASK_X
;
196 src
.swizzle
= BRW_SWIZZLE_WWWW
;
197 inst
= emit(MOV(dst
, src
));
199 /* In dual instanced dispatch mode, dst has a width of 4, so we need
200 * to make sure the MOV happens regardless of which channels are
203 inst
->force_writemask_all
= true;
207 this->current_annotation
= NULL
;
212 vec4_gs_visitor::emit_program_code()
214 /* We don't support NV_geometry_program4. */
215 unreachable("Unreached");
220 vec4_gs_visitor::emit_thread_end()
222 if (c
->control_data_header_size_bits
> 0) {
223 /* During shader execution, we only ever call emit_control_data_bits()
224 * just prior to outputting a vertex. Therefore, the control data bits
225 * corresponding to the most recently output vertex still need to be
228 current_annotation
= "thread end: emit control data bits";
229 emit_control_data_bits();
232 /* MRF 0 is reserved for the debugger, so start with message header
237 current_annotation
= "thread end";
238 dst_reg
mrf_reg(MRF
, base_mrf
);
239 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
240 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
241 inst
->force_writemask_all
= true;
242 emit(GS_OPCODE_SET_VERTEX_COUNT
, mrf_reg
, this->vertex_count
);
243 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
244 emit_shader_time_end();
245 inst
= emit(GS_OPCODE_THREAD_END
);
246 inst
->base_mrf
= base_mrf
;
252 vec4_gs_visitor::emit_urb_write_header(int mrf
)
254 /* The SEND instruction that writes the vertex data to the VUE will use
255 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message
256 * header specify an offset (in multiples of 256 bits) into the URB entry
257 * at which the write should take place.
259 * So we have to prepare a message header with the appropriate offset
262 dst_reg
mrf_reg(MRF
, mrf
);
263 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
264 this->current_annotation
= "URB write header";
265 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
266 inst
->force_writemask_all
= true;
267 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, this->vertex_count
,
268 (uint32_t) c
->prog_data
.output_vertex_size_hwords
);
273 vec4_gs_visitor::emit_urb_write_opcode(bool complete
)
275 /* We don't care whether the vertex is complete, because in general
276 * geometry shaders output multiple vertices, and we don't terminate the
277 * thread until all vertices are complete.
281 vec4_instruction
*inst
= emit(GS_OPCODE_URB_WRITE
);
282 inst
->offset
= c
->prog_data
.control_data_header_size_hwords
;
284 /* We need to increment Global Offset by 1 to make room for Broadwell's
285 * extra "Vertex Count" payload at the beginning of the URB entry.
287 if (devinfo
->gen
>= 8)
290 inst
->urb_write_flags
= BRW_URB_WRITE_PER_SLOT_OFFSET
;
296 vec4_gs_visitor::compute_array_stride(ir_dereference_array
*ir
)
298 /* Geometry shader inputs are arrays, but they use an unusual array layout:
299 * instead of all array elements for a given geometry shader input being
300 * stored consecutively, all geometry shader inputs are interleaved into
301 * one giant array. At this stage of compilation, we assume that the
302 * stride of the array is BRW_VARYING_SLOT_COUNT. Later,
303 * setup_attributes() will remap our accesses to the actual input array.
305 ir_dereference_variable
*deref_var
= ir
->array
->as_dereference_variable();
306 if (deref_var
&& deref_var
->var
->data
.mode
== ir_var_shader_in
)
307 return BRW_VARYING_SLOT_COUNT
;
309 return vec4_visitor::compute_array_stride(ir
);
314 * Write out a batch of 32 control data bits from the control_data_bits
315 * register to the URB.
317 * The current value of the vertex_count register determines which DWORD in
318 * the URB receives the control data bits. The control_data_bits register is
319 * assumed to contain the correct data for the vertex that was most recently
320 * output, and all previous vertices that share the same DWORD.
322 * This function takes care of ensuring that if no vertices have been output
323 * yet, no control bits are emitted.
326 vec4_gs_visitor::emit_control_data_bits()
328 assert(c
->control_data_bits_per_vertex
!= 0);
330 /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized)
331 * granularity, we need to use two tricks to ensure that the batch of 32
332 * control data bits is written to the appropriate DWORD in the URB. To
333 * select which vec4 we are writing to, we use the "slot {0,1} offset"
334 * fields of the message header. To select which DWORD in the vec4 we are
335 * writing to, we use the channel mask fields of the message header. To
336 * avoid penalizing geometry shaders that emit a small number of vertices
337 * with extra bookkeeping, we only do each of these tricks when
338 * c->prog_data.control_data_header_size_bits is large enough to make it
341 * Note: this means that if we're outputting just a single DWORD of control
342 * data bits, we'll actually replicate it four times since we won't do any
343 * channel masking. But that's not a problem since in this case the
344 * hardware only pays attention to the first DWORD.
346 enum brw_urb_write_flags urb_write_flags
= BRW_URB_WRITE_OWORD
;
347 if (c
->control_data_header_size_bits
> 32)
348 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_USE_CHANNEL_MASKS
;
349 if (c
->control_data_header_size_bits
> 128)
350 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_PER_SLOT_OFFSET
;
352 /* If we are using either channel masks or a per-slot offset, then we
353 * need to figure out which DWORD we are trying to write to, using the
356 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
358 * Since bits_per_vertex is a power of two, and is known at compile
359 * time, this can be optimized to:
361 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
363 src_reg
dword_index(this, glsl_type::uint_type
);
364 if (urb_write_flags
) {
365 src_reg
prev_count(this, glsl_type::uint_type
);
366 emit(ADD(dst_reg(prev_count
), this->vertex_count
, 0xffffffffu
));
367 unsigned log2_bits_per_vertex
=
368 _mesa_fls(c
->control_data_bits_per_vertex
);
369 emit(SHR(dst_reg(dword_index
), prev_count
,
370 (uint32_t) (6 - log2_bits_per_vertex
)));
373 /* Start building the URB write message. The first MRF gets a copy of
377 dst_reg
mrf_reg(MRF
, base_mrf
);
378 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
379 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
380 inst
->force_writemask_all
= true;
382 if (urb_write_flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
) {
383 /* Set the per-slot offset to dword_index / 4, to that we'll write to
384 * the appropriate OWORD within the control data header.
386 src_reg
per_slot_offset(this, glsl_type::uint_type
);
387 emit(SHR(dst_reg(per_slot_offset
), dword_index
, 2u));
388 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, per_slot_offset
, 1u);
391 if (urb_write_flags
& BRW_URB_WRITE_USE_CHANNEL_MASKS
) {
392 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
393 * write to the appropriate DWORD within the OWORD. We need to do
394 * this computation with force_writemask_all, otherwise garbage data
395 * from invocation 0 might clobber the mask for invocation 1 when
396 * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
399 src_reg
channel(this, glsl_type::uint_type
);
400 inst
= emit(AND(dst_reg(channel
), dword_index
, 3u));
401 inst
->force_writemask_all
= true;
402 src_reg
one(this, glsl_type::uint_type
);
403 inst
= emit(MOV(dst_reg(one
), 1u));
404 inst
->force_writemask_all
= true;
405 src_reg
channel_mask(this, glsl_type::uint_type
);
406 inst
= emit(SHL(dst_reg(channel_mask
), one
, channel
));
407 inst
->force_writemask_all
= true;
408 emit(GS_OPCODE_PREPARE_CHANNEL_MASKS
, dst_reg(channel_mask
),
410 emit(GS_OPCODE_SET_CHANNEL_MASKS
, mrf_reg
, channel_mask
);
413 /* Store the control data bits in the message payload and send it. */
414 dst_reg
mrf_reg2(MRF
, base_mrf
+ 1);
415 inst
= emit(MOV(mrf_reg2
, this->control_data_bits
));
416 inst
->force_writemask_all
= true;
417 inst
= emit(GS_OPCODE_URB_WRITE
);
418 inst
->urb_write_flags
= urb_write_flags
;
419 /* We need to increment Global Offset by 256-bits to make room for
420 * Broadwell's extra "Vertex Count" payload at the beginning of the
421 * URB entry. Since this is an OWord message, Global Offset is counted
422 * in 128-bit units, so we must set it to 2.
424 if (devinfo
->gen
>= 8)
426 inst
->base_mrf
= base_mrf
;
431 vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id
)
433 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
435 /* Note: we are calling this *before* increasing vertex_count, so
436 * this->vertex_count == vertex_count - 1 in the formula above.
439 /* Stream mode uses 2 bits per vertex */
440 assert(c
->control_data_bits_per_vertex
== 2);
442 /* Must be a valid stream */
443 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
445 /* Control data bits are initialized to 0 so we don't have to set any
446 * bits when sending vertices to stream 0.
451 /* reg::sid = stream_id */
452 src_reg
sid(this, glsl_type::uint_type
);
453 emit(MOV(dst_reg(sid
), stream_id
));
455 /* reg:shift_count = 2 * (vertex_count - 1) */
456 src_reg
shift_count(this, glsl_type::uint_type
);
457 emit(SHL(dst_reg(shift_count
), this->vertex_count
, 1u));
459 /* Note: we're relying on the fact that the GEN SHL instruction only pays
460 * attention to the lower 5 bits of its second source argument, so on this
461 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
462 * stream_id << ((2 * (vertex_count - 1)) % 32).
464 src_reg
mask(this, glsl_type::uint_type
);
465 emit(SHL(dst_reg(mask
), sid
, shift_count
));
466 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
470 vec4_gs_visitor::gs_emit_vertex(int stream_id
)
472 this->current_annotation
= "emit vertex: safety check";
474 /* Haswell and later hardware ignores the "Render Stream Select" bits
475 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
476 * and instead sends all primitives down the pipeline for rasterization.
477 * If the SOL stage is enabled, "Render Stream Select" is honored and
478 * primitives bound to non-zero streams are discarded after stream output.
480 * Since the only purpose of primives sent to non-zero streams is to
481 * be recorded by transform feedback, we can simply discard all geometry
482 * bound to these streams when transform feedback is disabled.
484 if (stream_id
> 0 && shader_prog
->TransformFeedback
.NumVarying
== 0)
487 /* To ensure that we don't output more vertices than the shader specified
488 * using max_vertices, do the logic inside a conditional of the form "if
489 * (vertex_count < MAX)"
491 unsigned num_output_vertices
= c
->gp
->program
.VerticesOut
;
492 emit(CMP(dst_null_d(), this->vertex_count
,
493 src_reg(num_output_vertices
), BRW_CONDITIONAL_L
));
494 emit(IF(BRW_PREDICATE_NORMAL
));
496 /* If we're outputting 32 control data bits or less, then we can wait
497 * until the shader is over to output them all. Otherwise we need to
498 * output them as we go. Now is the time to do it, since we're about to
499 * output the vertex_count'th vertex, so it's guaranteed that the
500 * control data bits associated with the (vertex_count - 1)th vertex are
503 if (c
->control_data_header_size_bits
> 32) {
504 this->current_annotation
= "emit vertex: emit control data bits";
505 /* Only emit control data bits if we've finished accumulating a batch
506 * of 32 bits. This is the case when:
508 * (vertex_count * bits_per_vertex) % 32 == 0
510 * (in other words, when the last 5 bits of vertex_count *
511 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
512 * integer n (which is always the case, since bits_per_vertex is
513 * always 1 or 2), this is equivalent to requiring that the last 5-n
514 * bits of vertex_count are 0:
516 * vertex_count & (2^(5-n) - 1) == 0
518 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
521 * vertex_count & (32 / bits_per_vertex - 1) == 0
523 vec4_instruction
*inst
=
524 emit(AND(dst_null_d(), this->vertex_count
,
525 (uint32_t) (32 / c
->control_data_bits_per_vertex
- 1)));
526 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
528 emit(IF(BRW_PREDICATE_NORMAL
));
530 /* If vertex_count is 0, then no control data bits have been
531 * accumulated yet, so we skip emitting them.
533 emit(CMP(dst_null_d(), this->vertex_count
, 0u,
534 BRW_CONDITIONAL_NEQ
));
535 emit(IF(BRW_PREDICATE_NORMAL
));
536 emit_control_data_bits();
537 emit(BRW_OPCODE_ENDIF
);
539 /* Reset control_data_bits to 0 so we can start accumulating a new
542 * Note: in the case where vertex_count == 0, this neutralizes the
543 * effect of any call to EndPrimitive() that the shader may have
544 * made before outputting its first vertex.
546 inst
= emit(MOV(dst_reg(this->control_data_bits
), 0u));
547 inst
->force_writemask_all
= true;
549 emit(BRW_OPCODE_ENDIF
);
552 this->current_annotation
= "emit vertex: vertex data";
555 /* In stream mode we have to set control data bits for all vertices
556 * unless we have disabled control data bits completely (which we do
557 * do for GL_POINTS outputs that don't use streams).
559 if (c
->control_data_header_size_bits
> 0 &&
560 c
->prog_data
.control_data_format
==
561 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
562 this->current_annotation
= "emit vertex: Stream control data bits";
563 set_stream_control_data_bits(stream_id
);
566 this->current_annotation
= "emit vertex: increment vertex count";
567 emit(ADD(dst_reg(this->vertex_count
), this->vertex_count
,
570 emit(BRW_OPCODE_ENDIF
);
572 this->current_annotation
= NULL
;
576 vec4_gs_visitor::visit(ir_emit_vertex
*ir
)
578 gs_emit_vertex(ir
->stream_id());
582 vec4_gs_visitor::gs_end_primitive()
584 /* We can only do EndPrimitive() functionality when the control data
585 * consists of cut bits. Fortunately, the only time it isn't is when the
586 * output type is points, in which case EndPrimitive() is a no-op.
588 if (c
->prog_data
.control_data_format
!=
589 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
593 /* Cut bits use one bit per vertex. */
594 assert(c
->control_data_bits_per_vertex
== 1);
596 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
597 * vertex n, 0 otherwise. So all we need to do here is mark bit
598 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
599 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
600 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
602 * Note that if EndPrimitve() is called before emitting any vertices, this
603 * will cause us to set bit 31 of the control_data_bits register to 1.
604 * That's fine because:
606 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
607 * output, so the hardware will ignore cut bit 31.
609 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
610 * last vertex, so setting cut bit 31 has no effect (since the primitive
611 * is automatically ended when the GS terminates).
613 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
614 * control_data_bits register to 0 when the first vertex is emitted.
617 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
618 src_reg
one(this, glsl_type::uint_type
);
619 emit(MOV(dst_reg(one
), 1u));
620 src_reg
prev_count(this, glsl_type::uint_type
);
621 emit(ADD(dst_reg(prev_count
), this->vertex_count
, 0xffffffffu
));
622 src_reg
mask(this, glsl_type::uint_type
);
623 /* Note: we're relying on the fact that the GEN SHL instruction only pays
624 * attention to the lower 5 bits of its second source argument, so on this
625 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
626 * ((vertex_count - 1) % 32).
628 emit(SHL(dst_reg(mask
), one
, prev_count
));
629 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
633 vec4_gs_visitor::visit(ir_end_primitive
*)
638 static const unsigned *
639 generate_assembly(struct brw_context
*brw
,
640 struct gl_shader_program
*shader_prog
,
641 struct gl_program
*prog
,
642 struct brw_vue_prog_data
*prog_data
,
645 unsigned *final_assembly_size
)
647 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
648 shader_prog
, prog
, prog_data
, mem_ctx
,
649 INTEL_DEBUG
& DEBUG_GS
, "geometry", "GS");
650 return g
.generate_assembly(cfg
, final_assembly_size
);
653 extern "C" const unsigned *
654 brw_gs_emit(struct brw_context
*brw
,
655 struct gl_shader_program
*prog
,
656 struct brw_gs_compile
*c
,
658 unsigned *final_assembly_size
)
660 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
661 struct brw_shader
*shader
=
662 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
664 brw_dump_ir("geometry", prog
, &shader
->base
, NULL
);
668 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
669 st_index
= brw_get_shader_time_index(brw
, prog
, NULL
, ST_GS
);
672 /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
673 * so without spilling. If the GS invocations count > 1, then we can't use
676 if (c
->prog_data
.invocations
<= 1 &&
677 likely(!(INTEL_DEBUG
& DEBUG_NO_DUAL_OBJECT_GS
))) {
678 c
->prog_data
.base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
680 vec4_gs_visitor
v(brw
->intelScreen
->compiler
, brw
,
681 c
, prog
, mem_ctx
, true /* no_spills */, st_index
);
683 return generate_assembly(brw
, prog
, &c
->gp
->program
.Base
,
684 &c
->prog_data
.base
, mem_ctx
, v
.cfg
,
685 final_assembly_size
);
690 /* Either we failed to compile in DUAL_OBJECT mode (probably because it
691 * would have required spilling) or DUAL_OBJECT mode is disabled. So fall
692 * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers.
694 * FIXME: Single dispatch mode requires that the driver can handle
695 * interleaving of input registers, but this is already supported (dual
696 * instance mode has the same requirement). However, to take full advantage
697 * of single dispatch mode to reduce register pressure we would also need to
698 * do interleaved outputs, but currently, the vec4 visitor and generator
699 * classes do not support this, so at the moment register pressure in
700 * single and dual instance modes is the same.
702 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS"
703 * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely
704 * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode
705 * is also supported. When InstanceCount=1 (one instance per object) software
706 * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be
707 * the best choice for performance, followed by SINGLE mode."
709 * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE
710 * mode is more performant when invocations > 1. Gen6 only supports
713 if (c
->prog_data
.invocations
<= 1 || brw
->gen
< 7)
714 c
->prog_data
.base
.dispatch_mode
= DISPATCH_MODE_4X1_SINGLE
;
716 c
->prog_data
.base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_INSTANCE
;
718 vec4_gs_visitor
*gs
= NULL
;
719 const unsigned *ret
= NULL
;
722 gs
= new vec4_gs_visitor(brw
->intelScreen
->compiler
, brw
,
723 c
, prog
, mem_ctx
, false /* no_spills */,
726 gs
= new gen6_gs_visitor(brw
->intelScreen
->compiler
, brw
,
727 c
, prog
, mem_ctx
, false /* no_spills */,
731 prog
->LinkStatus
= false;
732 ralloc_strcat(&prog
->InfoLog
, gs
->fail_msg
);
734 ret
= generate_assembly(brw
, prog
, &c
->gp
->program
.Base
,
735 &c
->prog_data
.base
, mem_ctx
, gs
->cfg
,
736 final_assembly_size
);
744 } /* namespace brw */