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25 * \file brw_vec4_gs_visitor.cpp
27 * Geometry-shader-specific code derived from the vec4_visitor class.
30 #include "brw_vec4_gs_visitor.h"
32 const unsigned MAX_GS_INPUT_VERTICES
= 6;
36 vec4_gs_visitor::vec4_gs_visitor(struct brw_context
*brw
,
37 struct brw_gs_compile
*c
,
38 struct gl_shader_program
*prog
,
41 : vec4_visitor(brw
, &c
->base
, &c
->gp
->program
.Base
, &c
->key
.base
,
42 &c
->prog_data
.base
, prog
, MESA_SHADER_GEOMETRY
, mem_ctx
,
43 INTEL_DEBUG
& DEBUG_GS
, no_spills
,
44 ST_GS
, ST_GS_WRITTEN
, ST_GS_RESET
),
51 vec4_gs_visitor::make_reg_for_system_value(ir_variable
*ir
)
53 dst_reg
*reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
55 switch (ir
->data
.location
) {
56 case SYSTEM_VALUE_INVOCATION_ID
:
57 this->current_annotation
= "initialize gl_InvocationID";
58 emit(GS_OPCODE_GET_INSTANCE_ID
, *reg
);
61 assert(!"not reached");
70 vec4_gs_visitor::setup_varying_inputs(int payload_reg
, int *attribute_map
,
71 int attributes_per_reg
)
73 /* For geometry shaders there are N copies of the input attributes, where N
74 * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT *
75 * i + j] represents attribute j for vertex i.
77 * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time,
78 * so the total number of input slots that will be delivered to the GS (and
79 * thus the stride of the input arrays) is urb_read_length * 2.
81 const unsigned num_input_vertices
= c
->gp
->program
.VerticesIn
;
82 assert(num_input_vertices
<= MAX_GS_INPUT_VERTICES
);
83 unsigned input_array_stride
= c
->prog_data
.base
.urb_read_length
* 2;
85 for (int slot
= 0; slot
< c
->input_vue_map
.num_slots
; slot
++) {
86 int varying
= c
->input_vue_map
.slot_to_varying
[slot
];
87 for (unsigned vertex
= 0; vertex
< num_input_vertices
; vertex
++) {
88 attribute_map
[BRW_VARYING_SLOT_COUNT
* vertex
+ varying
] =
89 attributes_per_reg
* payload_reg
+ input_array_stride
* vertex
+
94 int regs_used
= ALIGN(input_array_stride
* num_input_vertices
,
95 attributes_per_reg
) / attributes_per_reg
;
96 return payload_reg
+ regs_used
;
101 vec4_gs_visitor::setup_payload()
103 int attribute_map
[BRW_VARYING_SLOT_COUNT
* MAX_GS_INPUT_VERTICES
];
105 /* If we are in dual instanced mode, then attributes are going to be
106 * interleaved, so one register contains two attribute slots.
108 int attributes_per_reg
= c
->prog_data
.dual_instanced_dispatch
? 2 : 1;
110 /* If a geometry shader tries to read from an input that wasn't written by
111 * the vertex shader, that produces undefined results, but it shouldn't
112 * crash anything. So initialize attribute_map to zeros--that ensures that
113 * these undefined results are read from r0.
115 memset(attribute_map
, 0, sizeof(attribute_map
));
119 /* The payload always contains important data in r0, which contains
120 * the URB handles that are passed on to the URB write at the end
125 /* If the shader uses gl_PrimitiveIDIn, that goes in r1. */
126 if (c
->prog_data
.include_primitive_id
)
127 attribute_map
[VARYING_SLOT_PRIMITIVE_ID
] = attributes_per_reg
* reg
++;
129 reg
= setup_uniforms(reg
);
131 reg
= setup_varying_inputs(reg
, attribute_map
, attributes_per_reg
);
133 lower_attributes_to_hw_regs(attribute_map
,
134 c
->prog_data
.dual_instanced_dispatch
);
136 this->first_non_payload_grf
= reg
;
141 vec4_gs_visitor::emit_prolog()
143 /* In vertex shaders, r0.2 is guaranteed to be initialized to zero. In
144 * geometry shaders, it isn't (it contains a bunch of information we don't
145 * need, like the input primitive type). We need r0.2 to be zero in order
146 * to build scratch read/write messages correctly (otherwise this value
147 * will be interpreted as a global offset, causing us to do our scratch
148 * reads/writes to garbage memory). So just set it to zero at the top of
151 this->current_annotation
= "clear r0.2";
152 dst_reg
r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD
));
153 vec4_instruction
*inst
= emit(GS_OPCODE_SET_DWORD_2_IMMED
, r0
, 0u);
154 inst
->force_writemask_all
= true;
156 /* Create a virtual register to hold the vertex count */
157 this->vertex_count
= src_reg(this, glsl_type::uint_type
);
159 /* Initialize the vertex_count register to 0 */
160 this->current_annotation
= "initialize vertex_count";
161 inst
= emit(MOV(dst_reg(this->vertex_count
), 0u));
162 inst
->force_writemask_all
= true;
164 if (c
->control_data_header_size_bits
> 0) {
165 /* Create a virtual register to hold the current set of control data
168 this->control_data_bits
= src_reg(this, glsl_type::uint_type
);
170 /* If we're outputting more than 32 control data bits, then EmitVertex()
171 * will set control_data_bits to 0 after emitting the first vertex.
172 * Otherwise, we need to initialize it to 0 here.
174 if (c
->control_data_header_size_bits
<= 32) {
175 this->current_annotation
= "initialize control data bits";
176 inst
= emit(MOV(dst_reg(this->control_data_bits
), 0u));
177 inst
->force_writemask_all
= true;
181 /* If the geometry shader uses the gl_PointSize input, we need to fix it up
182 * to account for the fact that the vertex shader stored it in the w
183 * component of VARYING_SLOT_PSIZ.
185 if (c
->gp
->program
.Base
.InputsRead
& VARYING_BIT_PSIZ
) {
186 this->current_annotation
= "swizzle gl_PointSize input";
187 for (int vertex
= 0; vertex
< c
->gp
->program
.VerticesIn
; vertex
++) {
189 BRW_VARYING_SLOT_COUNT
* vertex
+ VARYING_SLOT_PSIZ
);
190 dst
.type
= BRW_REGISTER_TYPE_F
;
192 dst
.writemask
= WRITEMASK_X
;
193 src
.swizzle
= BRW_SWIZZLE_WWWW
;
194 inst
= emit(MOV(dst
, src
));
196 /* In dual instanced dispatch mode, dst has a width of 4, so we need
197 * to make sure the MOV happens regardless of which channels are
200 inst
->force_writemask_all
= true;
204 this->current_annotation
= NULL
;
209 vec4_gs_visitor::emit_program_code()
211 /* We don't support NV_geometry_program4. */
212 assert(!"Unreached");
217 vec4_gs_visitor::emit_thread_end()
219 if (c
->control_data_header_size_bits
> 0) {
220 /* During shader execution, we only ever call emit_control_data_bits()
221 * just prior to outputting a vertex. Therefore, the control data bits
222 * corresponding to the most recently output vertex still need to be
225 current_annotation
= "thread end: emit control data bits";
226 emit_control_data_bits();
229 /* MRF 0 is reserved for the debugger, so start with message header
234 current_annotation
= "thread end";
235 dst_reg
mrf_reg(MRF
, base_mrf
);
236 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
237 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
238 inst
->force_writemask_all
= true;
239 emit(GS_OPCODE_SET_VERTEX_COUNT
, mrf_reg
, this->vertex_count
);
240 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
241 emit_shader_time_end();
242 inst
= emit(GS_OPCODE_THREAD_END
);
243 inst
->base_mrf
= base_mrf
;
249 vec4_gs_visitor::emit_urb_write_header(int mrf
)
251 /* The SEND instruction that writes the vertex data to the VUE will use
252 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message
253 * header specify an offset (in multiples of 256 bits) into the URB entry
254 * at which the write should take place.
256 * So we have to prepare a message header with the appropriate offset
259 dst_reg
mrf_reg(MRF
, mrf
);
260 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
261 this->current_annotation
= "URB write header";
262 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
263 inst
->force_writemask_all
= true;
264 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, this->vertex_count
,
265 (uint32_t) c
->prog_data
.output_vertex_size_hwords
);
270 vec4_gs_visitor::emit_urb_write_opcode(bool complete
)
272 /* We don't care whether the vertex is complete, because in general
273 * geometry shaders output multiple vertices, and we don't terminate the
274 * thread until all vertices are complete.
278 vec4_instruction
*inst
= emit(GS_OPCODE_URB_WRITE
);
279 inst
->offset
= c
->prog_data
.control_data_header_size_hwords
;
281 /* We need to increment Global Offset by 1 to make room for Broadwell's
282 * extra "Vertex Count" payload at the beginning of the URB entry.
287 inst
->urb_write_flags
= BRW_URB_WRITE_PER_SLOT_OFFSET
;
293 vec4_gs_visitor::compute_array_stride(ir_dereference_array
*ir
)
295 /* Geometry shader inputs are arrays, but they use an unusual array layout:
296 * instead of all array elements for a given geometry shader input being
297 * stored consecutively, all geometry shader inputs are interleaved into
298 * one giant array. At this stage of compilation, we assume that the
299 * stride of the array is BRW_VARYING_SLOT_COUNT. Later,
300 * setup_attributes() will remap our accesses to the actual input array.
302 ir_dereference_variable
*deref_var
= ir
->array
->as_dereference_variable();
303 if (deref_var
&& deref_var
->var
->data
.mode
== ir_var_shader_in
)
304 return BRW_VARYING_SLOT_COUNT
;
306 return vec4_visitor::compute_array_stride(ir
);
311 * Write out a batch of 32 control data bits from the control_data_bits
312 * register to the URB.
314 * The current value of the vertex_count register determines which DWORD in
315 * the URB receives the control data bits. The control_data_bits register is
316 * assumed to contain the correct data for the vertex that was most recently
317 * output, and all previous vertices that share the same DWORD.
319 * This function takes care of ensuring that if no vertices have been output
320 * yet, no control bits are emitted.
323 vec4_gs_visitor::emit_control_data_bits()
325 assert(c
->control_data_bits_per_vertex
!= 0);
327 /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized)
328 * granularity, we need to use two tricks to ensure that the batch of 32
329 * control data bits is written to the appropriate DWORD in the URB. To
330 * select which vec4 we are writing to, we use the "slot {0,1} offset"
331 * fields of the message header. To select which DWORD in the vec4 we are
332 * writing to, we use the channel mask fields of the message header. To
333 * avoid penalizing geometry shaders that emit a small number of vertices
334 * with extra bookkeeping, we only do each of these tricks when
335 * c->prog_data.control_data_header_size_bits is large enough to make it
338 * Note: this means that if we're outputting just a single DWORD of control
339 * data bits, we'll actually replicate it four times since we won't do any
340 * channel masking. But that's not a problem since in this case the
341 * hardware only pays attention to the first DWORD.
343 enum brw_urb_write_flags urb_write_flags
= BRW_URB_WRITE_OWORD
;
344 if (c
->control_data_header_size_bits
> 32)
345 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_USE_CHANNEL_MASKS
;
346 if (c
->control_data_header_size_bits
> 128)
347 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_PER_SLOT_OFFSET
;
349 /* If vertex_count is 0, then no control data bits have been accumulated
350 * yet, so we should do nothing.
352 emit(CMP(dst_null_d(), this->vertex_count
, 0u, BRW_CONDITIONAL_NEQ
));
353 emit(IF(BRW_PREDICATE_NORMAL
));
355 /* If we are using either channel masks or a per-slot offset, then we
356 * need to figure out which DWORD we are trying to write to, using the
359 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
361 * Since bits_per_vertex is a power of two, and is known at compile
362 * time, this can be optimized to:
364 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
366 src_reg
dword_index(this, glsl_type::uint_type
);
367 if (urb_write_flags
) {
368 src_reg
prev_count(this, glsl_type::uint_type
);
369 emit(ADD(dst_reg(prev_count
), this->vertex_count
, 0xffffffffu
));
370 unsigned log2_bits_per_vertex
=
371 _mesa_fls(c
->control_data_bits_per_vertex
);
372 emit(SHR(dst_reg(dword_index
), prev_count
,
373 (uint32_t) (6 - log2_bits_per_vertex
)));
376 /* Start building the URB write message. The first MRF gets a copy of
380 dst_reg
mrf_reg(MRF
, base_mrf
);
381 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
382 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
383 inst
->force_writemask_all
= true;
385 if (urb_write_flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
) {
386 /* Set the per-slot offset to dword_index / 4, to that we'll write to
387 * the appropriate OWORD within the control data header.
389 src_reg
per_slot_offset(this, glsl_type::uint_type
);
390 emit(SHR(dst_reg(per_slot_offset
), dword_index
, 2u));
391 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, per_slot_offset
, 1u);
394 if (urb_write_flags
& BRW_URB_WRITE_USE_CHANNEL_MASKS
) {
395 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
396 * write to the appropriate DWORD within the OWORD. We need to do
397 * this computation with force_writemask_all, otherwise garbage data
398 * from invocation 0 might clobber the mask for invocation 1 when
399 * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
402 src_reg
channel(this, glsl_type::uint_type
);
403 inst
= emit(AND(dst_reg(channel
), dword_index
, 3u));
404 inst
->force_writemask_all
= true;
405 src_reg
one(this, glsl_type::uint_type
);
406 inst
= emit(MOV(dst_reg(one
), 1u));
407 inst
->force_writemask_all
= true;
408 src_reg
channel_mask(this, glsl_type::uint_type
);
409 inst
= emit(SHL(dst_reg(channel_mask
), one
, channel
));
410 inst
->force_writemask_all
= true;
411 emit(GS_OPCODE_PREPARE_CHANNEL_MASKS
, dst_reg(channel_mask
));
412 emit(GS_OPCODE_SET_CHANNEL_MASKS
, mrf_reg
, channel_mask
);
415 /* Store the control data bits in the message payload and send it. */
416 dst_reg
mrf_reg2(MRF
, base_mrf
+ 1);
417 inst
= emit(MOV(mrf_reg2
, this->control_data_bits
));
418 inst
->force_writemask_all
= true;
419 inst
= emit(GS_OPCODE_URB_WRITE
);
420 inst
->urb_write_flags
= urb_write_flags
;
421 /* We need to increment Global Offset by 256-bits to make room for
422 * Broadwell's extra "Vertex Count" payload at the beginning of the
423 * URB entry. Since this is an OWord message, Global Offset is counted
424 * in 128-bit units, so we must set it to 2.
428 inst
->base_mrf
= base_mrf
;
431 emit(BRW_OPCODE_ENDIF
);
436 vec4_gs_visitor::visit(ir_emit_vertex
*)
438 this->current_annotation
= "emit vertex: safety check";
440 /* To ensure that we don't output more vertices than the shader specified
441 * using max_vertices, do the logic inside a conditional of the form "if
442 * (vertex_count < MAX)"
444 unsigned num_output_vertices
= c
->gp
->program
.VerticesOut
;
445 emit(CMP(dst_null_d(), this->vertex_count
,
446 src_reg(num_output_vertices
), BRW_CONDITIONAL_L
));
447 emit(IF(BRW_PREDICATE_NORMAL
));
449 /* If we're outputting 32 control data bits or less, then we can wait
450 * until the shader is over to output them all. Otherwise we need to
451 * output them as we go. Now is the time to do it, since we're about to
452 * output the vertex_count'th vertex, so it's guaranteed that the
453 * control data bits associated with the (vertex_count - 1)th vertex are
456 if (c
->control_data_header_size_bits
> 32) {
457 this->current_annotation
= "emit vertex: emit control data bits";
458 /* Only emit control data bits if we've finished accumulating a batch
459 * of 32 bits. This is the case when:
461 * (vertex_count * bits_per_vertex) % 32 == 0
463 * (in other words, when the last 5 bits of vertex_count *
464 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
465 * integer n (which is always the case, since bits_per_vertex is
466 * always 1 or 2), this is equivalent to requiring that the last 5-n
467 * bits of vertex_count are 0:
469 * vertex_count & (2^(5-n) - 1) == 0
471 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
474 * vertex_count & (32 / bits_per_vertex - 1) == 0
476 vec4_instruction
*inst
=
477 emit(AND(dst_null_d(), this->vertex_count
,
478 (uint32_t) (32 / c
->control_data_bits_per_vertex
- 1)));
479 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
480 emit(IF(BRW_PREDICATE_NORMAL
));
482 emit_control_data_bits();
484 /* Reset control_data_bits to 0 so we can start accumulating a new
487 * Note: in the case where vertex_count == 0, this neutralizes the
488 * effect of any call to EndPrimitive() that the shader may have
489 * made before outputting its first vertex.
491 inst
= emit(MOV(dst_reg(this->control_data_bits
), 0u));
492 inst
->force_writemask_all
= true;
494 emit(BRW_OPCODE_ENDIF
);
497 this->current_annotation
= "emit vertex: vertex data";
500 this->current_annotation
= "emit vertex: increment vertex count";
501 emit(ADD(dst_reg(this->vertex_count
), this->vertex_count
,
504 emit(BRW_OPCODE_ENDIF
);
506 this->current_annotation
= NULL
;
510 vec4_gs_visitor::visit(ir_end_primitive
*)
512 /* We can only do EndPrimitive() functionality when the control data
513 * consists of cut bits. Fortunately, the only time it isn't is when the
514 * output type is points, in which case EndPrimitive() is a no-op.
516 if (c
->prog_data
.control_data_format
!=
517 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
521 /* Cut bits use one bit per vertex. */
522 assert(c
->control_data_bits_per_vertex
== 1);
524 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
525 * vertex n, 0 otherwise. So all we need to do here is mark bit
526 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
527 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
528 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
530 * Note that if EndPrimitve() is called before emitting any vertices, this
531 * will cause us to set bit 31 of the control_data_bits register to 1.
532 * That's fine because:
534 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
535 * output, so the hardware will ignore cut bit 31.
537 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
538 * last vertex, so setting cut bit 31 has no effect (since the primitive
539 * is automatically ended when the GS terminates).
541 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
542 * control_data_bits register to 0 when the first vertex is emitted.
545 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
546 src_reg
one(this, glsl_type::uint_type
);
547 emit(MOV(dst_reg(one
), 1u));
548 src_reg
prev_count(this, glsl_type::uint_type
);
549 emit(ADD(dst_reg(prev_count
), this->vertex_count
, 0xffffffffu
));
550 src_reg
mask(this, glsl_type::uint_type
);
551 /* Note: we're relying on the fact that the GEN SHL instruction only pays
552 * attention to the lower 5 bits of its second source argument, so on this
553 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
554 * ((vertex_count - 1) % 32).
556 emit(SHL(dst_reg(mask
), one
, prev_count
));
557 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
560 static const unsigned *
561 generate_assembly(struct brw_context
*brw
,
562 struct gl_shader_program
*shader_prog
,
563 struct gl_program
*prog
,
564 struct brw_vec4_prog_data
*prog_data
,
566 exec_list
*instructions
,
567 unsigned *final_assembly_size
)
570 gen8_vec4_generator
g(brw
, shader_prog
, prog
, prog_data
, mem_ctx
,
571 INTEL_DEBUG
& DEBUG_GS
);
572 return g
.generate_assembly(instructions
, final_assembly_size
);
574 vec4_generator
g(brw
, shader_prog
, prog
, prog_data
, mem_ctx
,
575 INTEL_DEBUG
& DEBUG_GS
);
576 return g
.generate_assembly(instructions
, final_assembly_size
);
580 extern "C" const unsigned *
581 brw_gs_emit(struct brw_context
*brw
,
582 struct gl_shader_program
*prog
,
583 struct brw_gs_compile
*c
,
585 unsigned *final_assembly_size
)
587 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
588 struct brw_shader
*shader
=
589 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
591 brw_dump_ir(brw
, "geometry", prog
, &shader
->base
, NULL
);
594 /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
595 * so without spilling. If the GS invocations count > 1, then we can't use
598 if (c
->prog_data
.invocations
<= 1 &&
599 likely(!(INTEL_DEBUG
& DEBUG_NO_DUAL_OBJECT_GS
))) {
600 c
->prog_data
.dual_instanced_dispatch
= false;
602 vec4_gs_visitor
v(brw
, c
, prog
, mem_ctx
, true /* no_spills */);
604 return generate_assembly(brw
, prog
, &c
->gp
->program
.Base
,
605 &c
->prog_data
.base
, mem_ctx
, &v
.instructions
,
606 final_assembly_size
);
610 /* Either we failed to compile in DUAL_OBJECT mode (probably because it
611 * would have required spilling) or DUAL_OBJECT mode is disabled. So fall
612 * back to DUAL_INSTANCED mode, which consumes fewer registers.
614 * FIXME: In an ideal world we'd fall back to SINGLE mode, which would
615 * allow us to interleave general purpose registers (resulting in even less
616 * likelihood of spilling). But at the moment, the vec4 generator and
617 * visitor classes don't have the infrastructure to interleave general
618 * purpose registers, so DUAL_INSTANCED is the best we can do.
620 c
->prog_data
.dual_instanced_dispatch
= true;
622 vec4_gs_visitor
v(brw
, c
, prog
, mem_ctx
, false /* no_spills */);
624 prog
->LinkStatus
= false;
625 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
629 return generate_assembly(brw
, prog
, &c
->gp
->program
.Base
, &c
->prog_data
.base
,
630 mem_ctx
, &v
.instructions
, final_assembly_size
);
634 } /* namespace brw */