44eed1ca6588326b9061586e2f841e0081d330f5
2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_vec4_live_variables.h"
33 /** @file brw_vec4_live_variables.cpp
35 * Support for computing at the basic block level which variables
36 * (virtual GRFs in our case) are live at entry and exit.
38 * See Muchnick's Advanced Compiler Design and Implementation, section
43 * Sets up the use[] and def[] arrays.
45 * The basic-block-level live variable analysis needs to know which
46 * variables get used before they're completely defined, and which
47 * variables are completely defined before they're used.
49 * We independently track each channel of a vec4. This is because we need to
50 * be able to recognize a sequence like:
55 * MUL result.xy tmp.xy e.xy
58 * as having tmp live only across that sequence (assuming it's used nowhere
59 * else), because it's a common pattern. A more conservative approach that
60 * doesn't get tmp marked a deffed in this block will tend to result in
64 vec4_live_variables::setup_def_use()
68 foreach_block (block
, cfg
) {
69 assert(ip
== block
->start_ip
);
71 assert(cfg
->blocks
[block
->num
- 1]->end_ip
== ip
- 1);
73 foreach_inst_in_block(vec4_instruction
, inst
, block
) {
74 /* Set use[] for this instruction */
75 for (unsigned int i
= 0; i
< 3; i
++) {
76 if (inst
->src
[i
].file
== GRF
) {
77 int reg
= inst
->src
[i
].reg
;
79 for (int j
= 0; j
< 4; j
++) {
80 int c
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
81 if (!BITSET_TEST(bd
[block
->num
].def
, reg
* 4 + c
))
82 BITSET_SET(bd
[block
->num
].use
, reg
* 4 + c
);
87 /* Check for unconditional writes to whole registers. These
88 * are the things that screen off preceding definitions of a
89 * variable, and thus qualify for being in def[].
91 if (inst
->dst
.file
== GRF
&&
92 v
->virtual_grf_sizes
[inst
->dst
.reg
] == 1 &&
94 for (int c
= 0; c
< 4; c
++) {
95 if (inst
->dst
.writemask
& (1 << c
)) {
96 int reg
= inst
->dst
.reg
;
97 if (!BITSET_TEST(bd
[block
->num
].use
, reg
* 4 + c
))
98 BITSET_SET(bd
[block
->num
].def
, reg
* 4 + c
);
109 * The algorithm incrementally sets bits in liveout and livein,
110 * propagating it through control flow. It will eventually terminate
111 * because it only ever adds bits, and stops when no bits are added in
115 vec4_live_variables::compute_live_variables()
122 foreach_block (block
, cfg
) {
124 for (int i
= 0; i
< bitset_words
; i
++) {
125 BITSET_WORD new_livein
= (bd
[block
->num
].use
[i
] |
126 (bd
[block
->num
].liveout
[i
] &
127 ~bd
[block
->num
].def
[i
]));
128 if (new_livein
& ~bd
[block
->num
].livein
[i
]) {
129 bd
[block
->num
].livein
[i
] |= new_livein
;
135 foreach_list_typed(bblock_link
, child_link
, link
, &block
->children
) {
136 bblock_t
*child
= child_link
->block
;
138 for (int i
= 0; i
< bitset_words
; i
++) {
139 BITSET_WORD new_liveout
= (bd
[child
->num
].livein
[i
] &
140 ~bd
[block
->num
].liveout
[i
]);
142 bd
[block
->num
].liveout
[i
] |= new_liveout
;
151 vec4_live_variables::vec4_live_variables(vec4_visitor
*v
, cfg_t
*cfg
)
154 mem_ctx
= ralloc_context(NULL
);
156 num_vars
= v
->virtual_grf_count
* 4;
157 bd
= rzalloc_array(mem_ctx
, struct block_data
, cfg
->num_blocks
);
159 bitset_words
= BITSET_WORDS(num_vars
);
160 for (int i
= 0; i
< cfg
->num_blocks
; i
++) {
161 bd
[i
].def
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
162 bd
[i
].use
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
163 bd
[i
].livein
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
164 bd
[i
].liveout
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
168 compute_live_variables();
171 vec4_live_variables::~vec4_live_variables()
173 ralloc_free(mem_ctx
);
176 #define MAX_INSTRUCTION (1 << 30)
179 * Computes a conservative start/end of the live intervals for each virtual GRF.
181 * We could expose per-channel live intervals to the consumer based on the
182 * information we computed in vec4_live_variables, except that our only
183 * current user is virtual_grf_interferes(). So we instead union the
184 * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
187 * We could potentially have virtual_grf_interferes() do the test per-channel,
188 * which would let some interesting register allocation occur (particularly on
189 * code-generated GLSL sequences from the Cg compiler which does register
190 * allocation at the GLSL level and thus reuses components of the variable
191 * with distinct lifetimes). But right now the complexity of doing so doesn't
192 * seem worth it, since having virtual_grf_interferes() be cheap is important
193 * for register allocation performance.
196 vec4_visitor::calculate_live_intervals()
198 if (this->live_intervals
)
201 int *start
= ralloc_array(mem_ctx
, int, this->virtual_grf_count
* 4);
202 int *end
= ralloc_array(mem_ctx
, int, this->virtual_grf_count
* 4);
203 ralloc_free(this->virtual_grf_start
);
204 ralloc_free(this->virtual_grf_end
);
205 this->virtual_grf_start
= start
;
206 this->virtual_grf_end
= end
;
208 for (int i
= 0; i
< this->virtual_grf_count
* 4; i
++) {
209 start
[i
] = MAX_INSTRUCTION
;
213 /* Start by setting up the intervals with no knowledge of control
217 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
218 for (unsigned int i
= 0; i
< 3; i
++) {
219 if (inst
->src
[i
].file
== GRF
) {
220 int reg
= inst
->src
[i
].reg
;
222 for (int j
= 0; j
< 4; j
++) {
223 int c
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
225 start
[reg
* 4 + c
] = MIN2(start
[reg
* 4 + c
], ip
);
226 end
[reg
* 4 + c
] = ip
;
231 if (inst
->dst
.file
== GRF
) {
232 int reg
= inst
->dst
.reg
;
234 for (int c
= 0; c
< 4; c
++) {
235 if (inst
->dst
.writemask
& (1 << c
)) {
236 start
[reg
* 4 + c
] = MIN2(start
[reg
* 4 + c
], ip
);
237 end
[reg
* 4 + c
] = ip
;
245 /* Now, extend those intervals using our analysis of control flow.
247 * The control flow-aware analysis was done at a channel level, while at
248 * this point we're distilling it down to vgrfs.
250 this->live_intervals
= new(mem_ctx
) vec4_live_variables(this, cfg
);
252 foreach_block (block
, cfg
) {
253 for (int i
= 0; i
< live_intervals
->num_vars
; i
++) {
254 if (BITSET_TEST(live_intervals
->bd
[block
->num
].livein
, i
)) {
255 start
[i
] = MIN2(start
[i
], block
->start_ip
);
256 end
[i
] = MAX2(end
[i
], block
->start_ip
);
259 if (BITSET_TEST(live_intervals
->bd
[block
->num
].liveout
, i
)) {
260 start
[i
] = MIN2(start
[i
], block
->end_ip
);
261 end
[i
] = MAX2(end
[i
], block
->end_ip
);
268 vec4_visitor::invalidate_live_intervals()
270 ralloc_free(live_intervals
);
271 live_intervals
= NULL
;
275 vec4_visitor::virtual_grf_interferes(int a
, int b
)
277 int start_a
= MIN2(MIN2(virtual_grf_start
[a
* 4 + 0],
278 virtual_grf_start
[a
* 4 + 1]),
279 MIN2(virtual_grf_start
[a
* 4 + 2],
280 virtual_grf_start
[a
* 4 + 3]));
281 int start_b
= MIN2(MIN2(virtual_grf_start
[b
* 4 + 0],
282 virtual_grf_start
[b
* 4 + 1]),
283 MIN2(virtual_grf_start
[b
* 4 + 2],
284 virtual_grf_start
[b
* 4 + 3]));
285 int end_a
= MAX2(MAX2(virtual_grf_end
[a
* 4 + 0],
286 virtual_grf_end
[a
* 4 + 1]),
287 MAX2(virtual_grf_end
[a
* 4 + 2],
288 virtual_grf_end
[a
* 4 + 3]));
289 int end_b
= MAX2(MAX2(virtual_grf_end
[b
* 4 + 0],
290 virtual_grf_end
[b
* 4 + 1]),
291 MAX2(virtual_grf_end
[b
* 4 + 2],
292 virtual_grf_end
[b
* 4 + 3]));
293 return !(end_a
<= start_b
||