src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_cfg.h"
  29 #include "brw_vec4_live_variables.h"
  30
  31 using namespace brw;
  32
  33 /** @file brw_vec4_live_variables.cpp
  34  *
  35  * Support for computing at the basic block level which variables
  36  * (virtual GRFs in our case) are live at entry and exit.
  37  *
  38  * See Muchnick's Advanced Compiler Design and Implementation, section
  39  * 14.1 (p444).
  40  */
  41
  42 /**
  43  * Sets up the use[] and def[] arrays.
  44  *
  45  * The basic-block-level live variable analysis needs to know which
  46  * variables get used before they're completely defined, and which
  47  * variables are completely defined before they're used.
  48  *
  49  * We independently track each channel of a vec4.  This is because we need to
  50  * be able to recognize a sequence like:
  51  *
  52  * ...
  53  * DP4 tmp.x a b;
  54  * DP4 tmp.y c d;
  55  * MUL result.xy tmp.xy e.xy
  56  * ...
  57  *
  58  * as having tmp live only across that sequence (assuming it's used nowhere
  59  * else), because it's a common pattern.  A more conservative approach that
  60  * doesn't get tmp marked a deffed in this block will tend to result in
  61  * spilling.
  62  */
  63 void
  64 vec4_live_variables::setup_def_use()
  65 {
  66    int ip = 0;
  67
  68    foreach_block (block, cfg) {
  69       assert(ip == block->start_ip);
  70       if (block->num > 0)
  71          assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
  72
  73       foreach_inst_in_block(vec4_instruction, inst, block) {
  74          struct block_data *bd = &block_data[block->num];
  75
  76          /* Set use[] for this instruction */
  77          for (unsigned int i = 0; i < 3; i++) {
  78             if (inst->src[i].file == GRF) {
  79                for (int c = 0; c < 4; c++) {
  80                   const unsigned v = var_from_reg(alloc, inst->src[i], c);
  81                   if (!BITSET_TEST(bd->def, v))
  82                      BITSET_SET(bd->use, v);
  83                }
  84             }
  85          }
  86          if (inst->reads_flag()) {
  87             if (!BITSET_TEST(bd->flag_def, 0)) {
  88                BITSET_SET(bd->flag_use, 0);
  89             }
  90          }
  91
  92          /* Check for unconditional writes to whole registers. These
  93           * are the things that screen off preceding definitions of a
  94           * variable, and thus qualify for being in def[].
  95           */
  96          if (inst->dst.file == GRF &&
  97              alloc.sizes[inst->dst.reg] == 1 &&
  98              !inst->predicate) {
  99             for (int c = 0; c < 4; c++) {
 100                if (inst->dst.writemask & (1 << c)) {
 101                   const unsigned v = var_from_reg(alloc, inst->dst, c);
 102                   if (!BITSET_TEST(bd->use, v))
 103                      BITSET_SET(bd->def, v);
 104                }
 105             }
 106          }
 107          if (inst->writes_flag()) {
 108             if (!BITSET_TEST(bd->flag_use, 0)) {
 109                BITSET_SET(bd->flag_def, 0);
 110             }
 111          }
 112
 113          ip++;
 114       }
 115    }
 116 }
 117
 118 /**
 119  * The algorithm incrementally sets bits in liveout and livein,
 120  * propagating it through control flow.  It will eventually terminate
 121  * because it only ever adds bits, and stops when no bits are added in
 122  * a pass.
 123  */
 124 void
 125 vec4_live_variables::compute_live_variables()
 126 {
 127    bool cont = true;
 128
 129    while (cont) {
 130       cont = false;
 131
 132       foreach_block (block, cfg) {
 133          struct block_data *bd = &block_data[block->num];
 134
 135          /* Update livein */
 136          for (int i = 0; i < bitset_words; i++) {
 137             BITSET_WORD new_livein = (bd->use[i] |
 138                                       (bd->liveout[i] &
 139                                        ~bd->def[i]));
 140             if (new_livein & ~bd->livein[i]) {
 141                bd->livein[i] |= new_livein;
 142                cont = true;
 143             }
 144          }
 145          BITSET_WORD new_livein = (bd->flag_use[0] |
 146                                    (bd->flag_liveout[0] &
 147                                     ~bd->flag_def[0]));
 148          if (new_livein & ~bd->flag_livein[0]) {
 149             bd->flag_livein[0] |= new_livein;
 150             cont = true;
 151          }
 152
 153          /* Update liveout */
 154          foreach_list_typed(bblock_link, child_link, link, &block->children) {
 155             struct block_data *child_bd = &block_data[child_link->block->num];
 156
 157             for (int i = 0; i < bitset_words; i++) {
 158                BITSET_WORD new_liveout = (child_bd->livein[i] &
 159                                           ~bd->liveout[i]);
 160                if (new_liveout) {
 161                   bd->liveout[i] |= new_liveout;
 162                   cont = true;
 163                }
 164             }
 165             BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
 166                                        ~bd->flag_liveout[0]);
 167             if (new_liveout) {
 168                bd->flag_liveout[0] |= new_liveout;
 169                cont = true;
 170             }
 171          }
 172       }
 173    }
 174 }
 175
 176 vec4_live_variables::vec4_live_variables(const simple_allocator &alloc,
 177                                          cfg_t *cfg)
 178    : alloc(alloc), cfg(cfg)
 179 {
 180    mem_ctx = ralloc_context(NULL);
 181
 182    num_vars = alloc.count * 4;
 183    block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
 184
 185    bitset_words = BITSET_WORDS(num_vars);
 186    for (int i = 0; i < cfg->num_blocks; i++) {
 187       block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 188       block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 189       block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 190       block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 191
 192       block_data[i].flag_def[0] = 0;
 193       block_data[i].flag_use[0] = 0;
 194       block_data[i].flag_livein[0] = 0;
 195       block_data[i].flag_liveout[0] = 0;
 196    }
 197
 198    setup_def_use();
 199    compute_live_variables();
 200 }
 201
 202 vec4_live_variables::~vec4_live_variables()
 203 {
 204    ralloc_free(mem_ctx);
 205 }
 206
 207 #define MAX_INSTRUCTION (1 << 30)
 208
 209 /**
 210  * Computes a conservative start/end of the live intervals for each virtual GRF.
 211  *
 212  * We could expose per-channel live intervals to the consumer based on the
 213  * information we computed in vec4_live_variables, except that our only
 214  * current user is virtual_grf_interferes().  So we instead union the
 215  * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
 216  * virtual_grf_end[].
 217  *
 218  * We could potentially have virtual_grf_interferes() do the test per-channel,
 219  * which would let some interesting register allocation occur (particularly on
 220  * code-generated GLSL sequences from the Cg compiler which does register
 221  * allocation at the GLSL level and thus reuses components of the variable
 222  * with distinct lifetimes).  But right now the complexity of doing so doesn't
 223  * seem worth it, since having virtual_grf_interferes() be cheap is important
 224  * for register allocation performance.
 225  */
 226 void
 227 vec4_visitor::calculate_live_intervals()
 228 {
 229    if (this->live_intervals)
 230       return;
 231
 232    int *start = ralloc_array(mem_ctx, int, this->alloc.count * 4);
 233    int *end = ralloc_array(mem_ctx, int, this->alloc.count * 4);
 234    ralloc_free(this->virtual_grf_start);
 235    ralloc_free(this->virtual_grf_end);
 236    this->virtual_grf_start = start;
 237    this->virtual_grf_end = end;
 238
 239    for (unsigned i = 0; i < this->alloc.count * 4; i++) {
 240       start[i] = MAX_INSTRUCTION;
 241       end[i] = -1;
 242    }
 243
 244    /* Start by setting up the intervals with no knowledge of control
 245     * flow.
 246     */
 247    int ip = 0;
 248    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 249       for (unsigned int i = 0; i < 3; i++) {
 250          if (inst->src[i].file == GRF) {
 251             for (int c = 0; c < 4; c++) {
 252                const unsigned v = var_from_reg(alloc, inst->src[i], c);
 253                start[v] = MIN2(start[v], ip);
 254                end[v] = ip;
 255             }
 256          }
 257       }
 258
 259       if (inst->dst.file == GRF) {
 260          for (int c = 0; c < 4; c++) {
 261             if (inst->dst.writemask & (1 << c)) {
 262                const unsigned v = var_from_reg(alloc, inst->dst, c);
 263                start[v] = MIN2(start[v], ip);
 264                end[v] = ip;
 265             }
 266          }
 267       }
 268
 269       ip++;
 270    }
 271
 272    /* Now, extend those intervals using our analysis of control flow.
 273     *
 274     * The control flow-aware analysis was done at a channel level, while at
 275     * this point we're distilling it down to vgrfs.
 276     */
 277    this->live_intervals = new(mem_ctx) vec4_live_variables(alloc, cfg);
 278
 279    foreach_block (block, cfg) {
 280       struct block_data *bd = &live_intervals->block_data[block->num];
 281
 282       for (int i = 0; i < live_intervals->num_vars; i++) {
 283          if (BITSET_TEST(bd->livein, i)) {
 284             start[i] = MIN2(start[i], block->start_ip);
 285             end[i] = MAX2(end[i], block->start_ip);
 286          }
 287
 288          if (BITSET_TEST(bd->liveout, i)) {
 289             start[i] = MIN2(start[i], block->end_ip);
 290             end[i] = MAX2(end[i], block->end_ip);
 291          }
 292       }
 293    }
 294 }
 295
 296 void
 297 vec4_visitor::invalidate_live_intervals()
 298 {
 299    ralloc_free(live_intervals);
 300    live_intervals = NULL;
 301 }
 302
 303 bool
 304 vec4_visitor::virtual_grf_interferes(int a, int b)
 305 {
 306    int start_a = MIN2(MIN2(virtual_grf_start[a * 4 + 0],
 307                            virtual_grf_start[a * 4 + 1]),
 308                       MIN2(virtual_grf_start[a * 4 + 2],
 309                            virtual_grf_start[a * 4 + 3]));
 310    int start_b = MIN2(MIN2(virtual_grf_start[b * 4 + 0],
 311                            virtual_grf_start[b * 4 + 1]),
 312                       MIN2(virtual_grf_start[b * 4 + 2],
 313                            virtual_grf_start[b * 4 + 3]));
 314    int end_a = MAX2(MAX2(virtual_grf_end[a * 4 + 0],
 315                          virtual_grf_end[a * 4 + 1]),
 316                     MAX2(virtual_grf_end[a * 4 + 2],
 317                          virtual_grf_end[a * 4 + 3]));
 318    int end_b = MAX2(MAX2(virtual_grf_end[b * 4 + 0],
 319                          virtual_grf_end[b * 4 + 1]),
 320                     MAX2(virtual_grf_end[b * 4 + 2],
 321                          virtual_grf_end[b * 4 + 3]));
 322    return !(end_a <= start_b ||
 323             end_b <= start_a);
 324 }