5bc2f9f3896177fe55b83468e82543015c08e93c
2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_vec4_live_variables.h"
33 /** @file brw_vec4_live_variables.cpp
35 * Support for computing at the basic block level which variables
36 * (virtual GRFs in our case) are live at entry and exit.
38 * See Muchnick's Advanced Compiler Design and Implementation, section
43 * Sets up the use[] and def[] arrays.
45 * The basic-block-level live variable analysis needs to know which
46 * variables get used before they're completely defined, and which
47 * variables are completely defined before they're used.
49 * We independently track each channel of a vec4. This is because we need to
50 * be able to recognize a sequence like:
55 * MUL result.xy tmp.xy e.xy
58 * as having tmp live only across that sequence (assuming it's used nowhere
59 * else), because it's a common pattern. A more conservative approach that
60 * doesn't get tmp marked a deffed in this block will tend to result in
64 vec4_live_variables::setup_def_use()
68 for (int b
= 0; b
< cfg
->num_blocks
; b
++) {
69 bblock_t
*block
= cfg
->blocks
[b
];
71 assert(ip
== block
->start_ip
);
73 assert(cfg
->blocks
[b
- 1]->end_ip
== ip
- 1);
75 for (vec4_instruction
*inst
= (vec4_instruction
*)block
->start
;
76 inst
!= block
->end
->next
;
77 inst
= (vec4_instruction
*)inst
->next
) {
79 /* Set use[] for this instruction */
80 for (unsigned int i
= 0; i
< 3; i
++) {
81 if (inst
->src
[i
].file
== GRF
) {
82 int reg
= inst
->src
[i
].reg
;
84 for (int j
= 0; j
< 4; j
++) {
85 int c
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
86 if (!BITSET_TEST(bd
[b
].def
, reg
* 4 + c
))
87 BITSET_SET(bd
[b
].use
, reg
* 4 + c
);
92 /* Check for unconditional writes to whole registers. These
93 * are the things that screen off preceding definitions of a
94 * variable, and thus qualify for being in def[].
96 if (inst
->dst
.file
== GRF
&&
97 v
->virtual_grf_sizes
[inst
->dst
.reg
] == 1 &&
99 for (int c
= 0; c
< 4; c
++) {
100 if (inst
->dst
.writemask
& (1 << c
)) {
101 int reg
= inst
->dst
.reg
;
102 if (!BITSET_TEST(bd
[b
].use
, reg
* 4 + c
))
103 BITSET_SET(bd
[b
].def
, reg
* 4 + c
);
114 * The algorithm incrementally sets bits in liveout and livein,
115 * propagating it through control flow. It will eventually terminate
116 * because it only ever adds bits, and stops when no bits are added in
120 vec4_live_variables::compute_live_variables()
127 for (int b
= 0; b
< cfg
->num_blocks
; b
++) {
129 for (int i
= 0; i
< bitset_words
; i
++) {
130 BITSET_WORD new_livein
= (bd
[b
].use
[i
] |
131 (bd
[b
].liveout
[i
] & ~bd
[b
].def
[i
]));
132 if (new_livein
& ~bd
[b
].livein
[i
]) {
133 bd
[b
].livein
[i
] |= new_livein
;
139 foreach_list(block_node
, &cfg
->blocks
[b
]->children
) {
140 bblock_link
*link
= (bblock_link
*)block_node
;
141 bblock_t
*block
= link
->block
;
143 for (int i
= 0; i
< bitset_words
; i
++) {
144 BITSET_WORD new_liveout
= (bd
[block
->block_num
].livein
[i
] &
147 bd
[b
].liveout
[i
] |= new_liveout
;
156 vec4_live_variables::vec4_live_variables(vec4_visitor
*v
, cfg_t
*cfg
)
159 mem_ctx
= ralloc_context(NULL
);
161 num_vars
= v
->virtual_grf_count
* 4;
162 bd
= rzalloc_array(mem_ctx
, struct block_data
, cfg
->num_blocks
);
164 bitset_words
= BITSET_WORDS(num_vars
);
165 for (int i
= 0; i
< cfg
->num_blocks
; i
++) {
166 bd
[i
].def
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
167 bd
[i
].use
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
168 bd
[i
].livein
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
169 bd
[i
].liveout
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
173 compute_live_variables();
176 vec4_live_variables::~vec4_live_variables()
178 ralloc_free(mem_ctx
);
181 #define MAX_INSTRUCTION (1 << 30)
184 * Computes a conservative start/end of the live intervals for each virtual GRF.
186 * We could expose per-channel live intervals to the consumer based on the
187 * information we computed in vec4_live_variables, except that our only
188 * current user is virtual_grf_interferes(). So we instead union the
189 * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
192 * We could potentially have virtual_grf_interferes() do the test per-channel,
193 * which would let some interesting register allocation occur (particularly on
194 * code-generated GLSL sequences from the Cg compiler which does register
195 * allocation at the GLSL level and thus reuses components of the variable
196 * with distinct lifetimes). But right now the complexity of doing so doesn't
197 * seem worth it, since having virtual_grf_interferes() be cheap is important
198 * for register allocation performance.
201 vec4_visitor::calculate_live_intervals()
203 if (this->live_intervals_valid
)
206 int *start
= ralloc_array(mem_ctx
, int, this->virtual_grf_count
);
207 int *end
= ralloc_array(mem_ctx
, int, this->virtual_grf_count
);
208 ralloc_free(this->virtual_grf_start
);
209 ralloc_free(this->virtual_grf_end
);
210 this->virtual_grf_start
= start
;
211 this->virtual_grf_end
= end
;
213 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
214 start
[i
] = MAX_INSTRUCTION
;
218 /* Start by setting up the intervals with no knowledge of control
222 foreach_list(node
, &this->instructions
) {
223 vec4_instruction
*inst
= (vec4_instruction
*)node
;
225 for (unsigned int i
= 0; i
< 3; i
++) {
226 if (inst
->src
[i
].file
== GRF
) {
227 int reg
= inst
->src
[i
].reg
;
229 start
[reg
] = MIN2(start
[reg
], ip
);
234 if (inst
->dst
.file
== GRF
) {
235 int reg
= inst
->dst
.reg
;
237 start
[reg
] = MIN2(start
[reg
], ip
);
244 /* Now, extend those intervals using our analysis of control flow.
246 * The control flow-aware analysis was done at a channel level, while at
247 * this point we're distilling it down to vgrfs.
250 vec4_live_variables
livevars(this, &cfg
);
252 for (int b
= 0; b
< cfg
.num_blocks
; b
++) {
253 for (int i
= 0; i
< livevars
.num_vars
; i
++) {
254 if (BITSET_TEST(livevars
.bd
[b
].livein
, i
)) {
255 start
[i
/ 4] = MIN2(start
[i
/ 4], cfg
.blocks
[b
]->start_ip
);
256 end
[i
/ 4] = MAX2(end
[i
/ 4], cfg
.blocks
[b
]->start_ip
);
259 if (BITSET_TEST(livevars
.bd
[b
].liveout
, i
)) {
260 start
[i
/ 4] = MIN2(start
[i
/ 4], cfg
.blocks
[b
]->end_ip
);
261 end
[i
/ 4] = MAX2(end
[i
/ 4], cfg
.blocks
[b
]->end_ip
);
266 this->live_intervals_valid
= true;
270 vec4_visitor::invalidate_live_intervals()
272 live_intervals_valid
= false;
276 vec4_visitor::virtual_grf_interferes(int a
, int b
)
278 return !(virtual_grf_end
[a
] <= virtual_grf_start
[b
] ||
279 virtual_grf_end
[b
] <= virtual_grf_start
[a
]);