2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_vec4_live_variables.h"
33 /** @file brw_vec4_live_variables.cpp
35 * Support for computing at the basic block level which variables
36 * (virtual GRFs in our case) are live at entry and exit.
38 * See Muchnick's Advanced Compiler Design and Implementation, section
43 * Sets up the use[] and def[] arrays.
45 * The basic-block-level live variable analysis needs to know which
46 * variables get used before they're completely defined, and which
47 * variables are completely defined before they're used.
49 * We independently track each channel of a vec4. This is because we need to
50 * be able to recognize a sequence like:
55 * MUL result.xy tmp.xy e.xy
58 * as having tmp live only across that sequence (assuming it's used nowhere
59 * else), because it's a common pattern. A more conservative approach that
60 * doesn't get tmp marked a deffed in this block will tend to result in
64 vec4_live_variables::setup_def_use()
68 foreach_block (block
, cfg
) {
69 assert(ip
== block
->start_ip
);
71 assert(cfg
->blocks
[block
->num
- 1]->end_ip
== ip
- 1);
73 foreach_inst_in_block(vec4_instruction
, inst
, block
) {
74 struct block_data
*bd
= &block_data
[block
->num
];
76 /* Set use[] for this instruction */
77 for (unsigned int i
= 0; i
< 3; i
++) {
78 if (inst
->src
[i
].file
== VGRF
) {
79 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++) {
80 for (int c
= 0; c
< 4; c
++) {
83 byte_offset(inst
->src
[i
], j
* REG_SIZE
),
85 if (!BITSET_TEST(bd
->def
, v
))
86 BITSET_SET(bd
->use
, v
);
91 for (unsigned c
= 0; c
< 4; c
++) {
92 if (inst
->reads_flag(c
) &&
93 !BITSET_TEST(bd
->flag_def
, c
)) {
94 BITSET_SET(bd
->flag_use
, c
);
98 /* Check for unconditional writes to whole registers. These
99 * are the things that screen off preceding definitions of a
100 * variable, and thus qualify for being in def[].
102 if (inst
->dst
.file
== VGRF
&&
103 (!inst
->predicate
|| inst
->opcode
== BRW_OPCODE_SEL
)) {
104 for (unsigned i
= 0; i
< regs_written(inst
); i
++) {
105 for (int c
= 0; c
< 4; c
++) {
106 if (inst
->dst
.writemask
& (1 << c
)) {
109 byte_offset(inst
->dst
, i
* REG_SIZE
), c
);
110 if (!BITSET_TEST(bd
->use
, v
))
111 BITSET_SET(bd
->def
, v
);
116 if (inst
->writes_flag()) {
117 for (unsigned c
= 0; c
< 4; c
++) {
118 if ((inst
->dst
.writemask
& (1 << c
)) &&
119 !BITSET_TEST(bd
->flag_use
, c
)) {
120 BITSET_SET(bd
->flag_def
, c
);
131 * The algorithm incrementally sets bits in liveout and livein,
132 * propagating it through control flow. It will eventually terminate
133 * because it only ever adds bits, and stops when no bits are added in
137 vec4_live_variables::compute_live_variables()
144 foreach_block_reverse (block
, cfg
) {
145 struct block_data
*bd
= &block_data
[block
->num
];
148 foreach_list_typed(bblock_link
, child_link
, link
, &block
->children
) {
149 struct block_data
*child_bd
= &block_data
[child_link
->block
->num
];
151 for (int i
= 0; i
< bitset_words
; i
++) {
152 BITSET_WORD new_liveout
= (child_bd
->livein
[i
] &
155 bd
->liveout
[i
] |= new_liveout
;
159 BITSET_WORD new_liveout
= (child_bd
->flag_livein
[0] &
160 ~bd
->flag_liveout
[0]);
162 bd
->flag_liveout
[0] |= new_liveout
;
168 for (int i
= 0; i
< bitset_words
; i
++) {
169 BITSET_WORD new_livein
= (bd
->use
[i
] |
172 if (new_livein
& ~bd
->livein
[i
]) {
173 bd
->livein
[i
] |= new_livein
;
177 BITSET_WORD new_livein
= (bd
->flag_use
[0] |
178 (bd
->flag_liveout
[0] &
180 if (new_livein
& ~bd
->flag_livein
[0]) {
181 bd
->flag_livein
[0] |= new_livein
;
188 vec4_live_variables::vec4_live_variables(const simple_allocator
&alloc
,
190 : alloc(alloc
), cfg(cfg
)
192 mem_ctx
= ralloc_context(NULL
);
194 num_vars
= alloc
.total_size
* 4;
195 block_data
= rzalloc_array(mem_ctx
, struct block_data
, cfg
->num_blocks
);
197 bitset_words
= BITSET_WORDS(num_vars
);
198 for (int i
= 0; i
< cfg
->num_blocks
; i
++) {
199 block_data
[i
].def
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
200 block_data
[i
].use
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
201 block_data
[i
].livein
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
202 block_data
[i
].liveout
= rzalloc_array(mem_ctx
, BITSET_WORD
, bitset_words
);
204 block_data
[i
].flag_def
[0] = 0;
205 block_data
[i
].flag_use
[0] = 0;
206 block_data
[i
].flag_livein
[0] = 0;
207 block_data
[i
].flag_liveout
[0] = 0;
211 compute_live_variables();
214 vec4_live_variables::~vec4_live_variables()
216 ralloc_free(mem_ctx
);
219 #define MAX_INSTRUCTION (1 << 30)
222 * Computes a conservative start/end of the live intervals for each virtual GRF.
224 * We could expose per-channel live intervals to the consumer based on the
225 * information we computed in vec4_live_variables, except that our only
226 * current user is virtual_grf_interferes(). So we instead union the
227 * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
230 * We could potentially have virtual_grf_interferes() do the test per-channel,
231 * which would let some interesting register allocation occur (particularly on
232 * code-generated GLSL sequences from the Cg compiler which does register
233 * allocation at the GLSL level and thus reuses components of the variable
234 * with distinct lifetimes). But right now the complexity of doing so doesn't
235 * seem worth it, since having virtual_grf_interferes() be cheap is important
236 * for register allocation performance.
239 vec4_visitor::calculate_live_intervals()
241 if (this->live_intervals
)
244 int *start
= ralloc_array(mem_ctx
, int, this->alloc
.total_size
* 4);
245 int *end
= ralloc_array(mem_ctx
, int, this->alloc
.total_size
* 4);
246 ralloc_free(this->virtual_grf_start
);
247 ralloc_free(this->virtual_grf_end
);
248 this->virtual_grf_start
= start
;
249 this->virtual_grf_end
= end
;
251 for (unsigned i
= 0; i
< this->alloc
.total_size
* 4; i
++) {
252 start
[i
] = MAX_INSTRUCTION
;
256 /* Start by setting up the intervals with no knowledge of control
260 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
261 for (unsigned int i
= 0; i
< 3; i
++) {
262 if (inst
->src
[i
].file
== VGRF
) {
263 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++) {
264 for (int c
= 0; c
< 4; c
++) {
267 byte_offset(inst
->src
[i
], j
* REG_SIZE
), c
);
268 start
[v
] = MIN2(start
[v
], ip
);
275 if (inst
->dst
.file
== VGRF
) {
276 for (unsigned i
= 0; i
< regs_written(inst
); i
++) {
277 for (int c
= 0; c
< 4; c
++) {
278 if (inst
->dst
.writemask
& (1 << c
)) {
281 byte_offset(inst
->dst
, i
* REG_SIZE
), c
);
282 start
[v
] = MIN2(start
[v
], ip
);
292 /* Now, extend those intervals using our analysis of control flow.
294 * The control flow-aware analysis was done at a channel level, while at
295 * this point we're distilling it down to vgrfs.
297 this->live_intervals
= new(mem_ctx
) vec4_live_variables(alloc
, cfg
);
299 foreach_block (block
, cfg
) {
300 struct block_data
*bd
= &live_intervals
->block_data
[block
->num
];
302 for (int i
= 0; i
< live_intervals
->num_vars
; i
++) {
303 if (BITSET_TEST(bd
->livein
, i
)) {
304 start
[i
] = MIN2(start
[i
], block
->start_ip
);
305 end
[i
] = MAX2(end
[i
], block
->start_ip
);
308 if (BITSET_TEST(bd
->liveout
, i
)) {
309 start
[i
] = MIN2(start
[i
], block
->end_ip
);
310 end
[i
] = MAX2(end
[i
], block
->end_ip
);
317 vec4_visitor::invalidate_live_intervals()
319 ralloc_free(live_intervals
);
320 live_intervals
= NULL
;
324 vec4_visitor::var_range_start(unsigned v
, unsigned n
) const
328 for (unsigned i
= 0; i
< n
; i
++)
329 start
= MIN2(start
, virtual_grf_start
[v
+ i
]);
335 vec4_visitor::var_range_end(unsigned v
, unsigned n
) const
339 for (unsigned i
= 0; i
< n
; i
++)
340 end
= MAX2(end
, virtual_grf_end
[v
+ i
]);
346 vec4_visitor::virtual_grf_interferes(int a
, int b
)
348 return !((var_range_end(4 * alloc
.offsets
[a
], 4 * alloc
.sizes
[a
]) <=
349 var_range_start(4 * alloc
.offsets
[b
], 4 * alloc
.sizes
[b
])) ||
350 (var_range_end(4 * alloc
.offsets
[b
], 4 * alloc
.sizes
[b
]) <=
351 var_range_start(4 * alloc
.offsets
[a
], 4 * alloc
.sizes
[a
])));